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DataSheet.in
SRK2000
Synchronous rectifier smart driver for LLC resonant converter
Preliminary data
Features

Secondary-side synchronous rectifier controller optimized for LLC resonant converter Safe management of load transient, light load and start-up condition Intelligent automatic sleep mode at light load Dual gate driver for n-channel MOSFETs with 1 A source and 3.5 A sink drive current Operating voltage range 4.5 to 32 V Programmable UVLO with hysteresis 250 A quiescent consumption Operating frequency up to 500 kHz SO8 package SO-8 switched off as its current goes to zero. A unique feature of this IC is its intelligent automatic sleep mode. It allows the detection of a low-power operating condition for the converter and puts the IC in a low consumption sleep-mode where gate driving is stopped and quiescent consumption is reduced. In this way, converter's efficiency improves at light load, where synchronous rectification is no more beneficial. The IC automatically exits from sleep-mode and restarts switching as it recognizes that the load for the converter has increased. A noticeable feature is the very low external component count required. Figure 1. Internal block diagram
Applications

All-in-one PC High-power AC-DC adapters 80+/85+ compliant ATX SMPS 90+/92+ compliant server SMPS Industrial SMPS
Description
The SRK2000 smart driver implements a control scheme specific for secondary-side synchronous rectification in LLC resonant converters that use a transformer with center-tap secondary winding for full-wave rectification. It provides two high-current gate-drive outputs, each capable of driving one or more N-channel Power MOSFETS. Each gate driver is controlled separately and an interlock logic circuit prevents the two synchronous rectifier MOSFETS from conducting simultaneously. The control scheme in this IC provides for each synchronous rectifier being switched on as the corresponding half-winding starts conducting and
Table 1.
Device summary
Package SO-8 Packing Tube Tape and reel
Order code SRK2000D SRK2000DTR
August 2010
Doc ID 17811 Rev 1
1/17
www.st.com 17
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
DataSheet.in
Contents
SRK2000
Contents
1 2 3 4 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1 EN pin: pin function and usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1.1 5.1.2 5.1.3 Pull-up resistor configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Resistor divider configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Remote on/off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2 5.3 5.4 5.5
Drain voltage sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Gate driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Intelligent automatic sleep-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6 7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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SRK2000
Pin description
1
Pin description
Figure 2. Pin configuration
SGND EN DVS1 DVS2
1 2 3 4
8 7 6 5
Vcc GD1 PGND GD2
Table 2.
n. 1
Pin description
Name SGND Function Signal Ground. Return of the bias current of the device and 0 volt reference for drain-to-source voltage monitors of both sections. Route directly this pin to PGND. Drain voltage threshold setting for synchronous rectifier MOSFET turn-off. UVLO threshold programming. This pin will typically be biased by either a pull-up resistor connected to Vcc or by a resistor divider sensing Vcc. Pulling the pin to ground will disable the gate driver outputs GD1 and GD2, thus it can be used as Enable input as well. Drain voltage sensing for sections 1 and 2. These pins are to be connected to the respective drain terminals of the corresponding synchronous rectifier MOSFET via limiting resistors. When the voltage on either pin goes negative, the corresponding synchronous rectifier MOSFET is switched on; as its (negative) voltage exceeds a threshold defined by the EN pin, the MOSFET is switched off. An internal logic rejects switching noise, however extreme care in a proper routing of the drain connection is recommended. Gate driver output for sections 2 and 1. Each totem pole output stage is able to drive power MOSFETs with a peak current of 1 A source and 3.5 A sink. The high-level voltage of these pins is clamped at about 12V to avoid excessive gate voltages in case the device is supplied with a high Vcc. Power ground. Return for gate drive currents. Route this pin to the common point where the source terminals of both synchronous rectifier MOSFETs are connected. Supply Voltage of the device. A small bypass capacitor (0.1 F typ.) to SGND, located as close to IC's pins as possible, might be useful to get a clean supply voltage for the internal control circuitry. A similar bypass capacitor to PGND, again located as close to IC's pins as possible, might be an effective energy buffer for the pulsed gate-drive currents.
2
EN
3 4
DVS1 DVS2
5 7
GD2 GD1
6
PGND
8
Vcc
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Pin description Figure 3. Typical system block diagram
SRK2000
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SRK2000
Maximum ratings
2
Maximum ratings
Table 3.
Symbol Vcc IccZ --IDVS1,2_sk IDVS1,2_sr
Absolute maximum ratings
Pin 8 8 2, 3, 4 3, 4 3, 4 Dc supply voltage Internal Zener maximum current Analog inputs voltage rating Analog inputs max. sink current (single pin) Analog inputs max. source current (single pin) Parameter Value -0.3 to VccZ 25 -0.3 to VccZ 25 -5 Unit V mA V mA mA
Table 4.
Symbol RthJA Ptot TJ Tstg
Thermal data
Parameter Max. thermal resistance, junction-to-ambient Power dissipation @TA = 50 C Junction temperature operating range Storage temperature Value 150 0.65 -40 to 150 -55 to 150 Unit C/W W C C
3
Typical application schematic
Figure 4. Typical application schematic
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Electrical characteristics
SRK2000
4
Electrical characteristics
TJ = -25 to 125 C, VCC = 12 V, CGD1 = CGD2 = 4.7 nF, EN = VCC; unless otherwise specified; typical values refer to TJ = 25 C Table 5.
Symbol Supply voltage VCC VCCOn VCCOff Hys VccZ Operating range Turn-on threshold Turn-off threshold Hysteresis Zener voltage IccZ = 20 mA 33 After turn-on
(1) (1)
Electrical characteristics
Parameter Test condition Min. Typ. Max. Unit
4.5 4.25 4 4.5 4.25 0.25 36
32 4.75 4.5
V V V V
39
V
Supply current Istart-up Iq ICC Iq Start-up current Quiescent current Operating supply current Quiescent current Before turn-on, Vcc = 4 V After turn-on @ 300 kHz EN = SGND 45 250 35 150 250 70 500 A A mA A
Drain sensing inputs and synch functions VDVS1,2_H IDVS1,2_b VDVS1,2_A VDVS1,2_PT Upper clamp voltage Input bias current Arming voltage (positive-going edge) Pre-triggering voltage (negative-going edge) -250 VDVS1,2 = -250 mV R = 680 k from EN to Vcc R = 270 k from EN to Vcc After sourcing IDS1,2_On After crossing VDS1,2_Off 150 40 60 -18 -9 IDVS1,2 = 20 mA VDVS1,2 = 0 to Vcc (2) -1 1.4 0.7 -200 -50 -25 -12.5 250 60 -32 mV -16 ns ns ns % % -180 A VccZ 1 V A V V
VDVS1,2_TH Turn-on threshold IDVS1,2_On Turn-on source current VDVS1,2_Off TPD_On TPD_Off TON_min DOFF DON Turn-off threshold (positive-going edge) Turn-on debounce delay Turn-off propagation delay Minimum ON-time Min. operating duty-cycle Restart duty-cycle
Gate-drive enable function VEN_On Hyst Enable threshold Hysteresis Positive going edge (1) Below VEN_On 1.7 1.8 45 1.9 V mV
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SRK2000 Table 5.
Symbol IEN
Electrical characteristics Electrical characteristics (continued)
Parameter Bias current Test condition VEN = VEN_On Min. Typ. Max. Unit 1 A
Turn-off threshold selection VEN-Th IEN Selection threshold Pull-down current VCC = VCCOn VEN = VEN_Th, VCC = VCCOn 0.32 7 0.36 10 0.40 13 V A
Gate drivers VGDH Output high voltage IGDsource= 5 mA IGDsource= 5 mA, Vcc = 5 V Output low voltage Output source peak current Output sink peak current Fall time Rise time Output clamp voltage IGDsource = 5 mA; Vcc = 20 V Vcc = 0 to VCCon Isink = 5 mA 12 IGDsink = 200 mA IGDsink = 200 mA, Vcc = 5 V 11.75 4.75 11.9 V 4.9 0.2 V 0.2 -1 3.5 18 40 13 1 15 1.3 A A ns ns V V
VGDL Isourcepk Isinkpk tf tr VGDclamp
VGDL_UVLO UVLO saturation
1. Parameters tracking each other
2. For Vcc>30 V IDVS1,2_b could be greater than 1 A because of the possible current contribution of the internal clamp zener (few tens of A)
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Application information
SRK2000
5
5.1
Application information
EN pin: pin function and usage
The pin may perform three different functions: it sets the threshold VDVS1,2_Off for the drainto-source voltage of either Synchronous Rectifier (SR) power MOSFET to determine their turn-off in each conduction cycle; it allows the user to program the UVLO thresholds of the gate drivers and can be used as Enable (remote on/off control).
5.1.1
Pull-up resistor configuration
At start-up, an internal 10 A current sink (IEN) is active as long as the device supply voltage Vcc is below the start-up threshold VCCOn. The moment Vcc equals VCCOn, (4.5 V typical) the voltage VEN on the EN pin determines the turn-off threshold VDVS1,2_Off for the drain voltage of both synchronous rectifiers during their cycle-by-cycle operation: if VEN < VEN_Th (= 0.36 V) the threshold will be set at -25 mV, otherwise at -12 mV. Once the decision is made, the setting will be frozen as long as Vcc is greater than the turn-off level VCCOff (4.25 V typical). A simple pull-up resistor R1 to Vcc can be used to set VDVS1,2_Off turn-off threshold. The voltage on the EN pin as the device turns on is given by:
VEN = VCCOn - IEN R1
Then, considering worst-case scenarios, we have:
R1 > 633 k
VDVS1,2 _ Off = -25 mV
R1 < 296 k
VDVS1,2 _ Off = -12 mV
Some additional margin (equal to resistor's tolerance) needs to be considered; assuming 5% tolerance, it is possible to suggest the use of the standard values R1 = 680 k in the first case and R1 = 270 k in the second case. Figure 5. EN pin biased with a pull-up resistor (for logic-level MOSFET driving)
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SRK2000
Application information
As Vcc exceeds VCCOn the internal current sink IEN is switched off and the enable function is activated. The voltage on the pin is then compared to an internal reference VEN_On set at 1.8 V: if this threshold is exceeded the gate drivers GD1 and GD2 will be enabled and the SR MOSFETs will be operated; otherwise, the device will stay in an idle condition and the SR MOSFETs in the off state. Using the pull-up resistor RP the voltage on the EN pin will rise as IEN is switched off and tend to Vcc, thus exceeding VEN_On and enabling the operation of both SR MOSFETs. Essentially, this results in enabling gate driving as Vcc exceeds VCCOn and disabling it as Vcc falls below VCCOn. This configuration is thereby suggested when SR MOSFETs are logic-level type.
5.1.2
Resistor divider configuration
To enable gate-driving with a Vcc voltage higher than a predefined value VCC_G, to properly drive standard SR MOSFET, the EN pin will be biased by a resistor divider (R1 upper resistor, R2 lower resistor) whose values will be chosen so as to exceed VEN_On when Vcc = VCC_G and set the desired VDVS1,2_Off level as well. Note that, with a falling Vcc, gate-driving will be disabled at a Vcc level about 2.5% lower than VCC_G, because of the 45 mV hysteresis of the comparator.
The equations that describe the circuit in the two crucial conditions Vcc = VCCOn (when the decision of the VDVS1,2_Off level is made) and Vcc = VCC_G (when gate driving is to be enabled) are respectively: Figure 6. EN pin biased with a resistor divider to program the gate-drive UVLO threshold VCC_G
Equation 1
V VCCOn - VEN = IEN + EN R1 R2 R2 VCC _ G = VEN _ On R1 + R2
Solving these equations for R1 and R2 we get:
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Application information Equation 2
SRK2000
V VCCOn - VEN CC _ G VEN _ On R1 = IEN VEN _ On R2 = R1 VCC _ G - VEN _ On If VCC_G is not too low (<8/9 V) its tolerance is not critical because related only to that of VEN_On (5.6%) and of the external resistors R1, R2 (1% each is recommended). Then, some care needs to be used only as far as the selection of the -12/-25 mV threshold is concerned: in fact, the large spread of IEN will considerably affect the voltage on the EN pin as the device turns on, value that can be found by solving the first of (1) for VEN:
Equation 3
VEN =
VCCOn - IEN R1 R1 1+ R2
A couple of examples will clarify the suggested calculation methodology.
Example 1 VCC_G = 10 V, VDVS1,2_Off = - 25 mV.
In this case VEN must be definitely lower than the minimum value of VEN_Th (= 0.32 V). From the second of (2), the nominal ratio of R1 to R2 will be (10 - 1.8) / 1.8 = 4.555. Substituting the appropriate extreme values in (3) it must be (4.75 - 7*10-6*R1) / (1 + 4.555) < 0.32; solving for R1 yields R1 > 425 k; let us consider an additional 4% margin to take both the tolerance and the granularity of the R1 and R2 values into account, so that: R1 > 425*1.04 = 442 k. Choose R1 = 442 k (E48 standard value) and, from the second of (2), R2 = 442/4.555 = 97 k; use 97.6 k (E48 standard value).
Example 2 VCC_G = 10 V, VDVS1,2_Off = - 12 mV.
In this case VEN must be definitely higher than the maximum value of VEN_Th (= 0.40 V). from the second of (2), the nominal ratio of R1 to R2 will be (10 - 1.8) / 1.8 = 4.555. Substituting the appropriate extreme values in (3) it must be (4.25 - 13*10-6*R1) / (1 + 4.555) > 0.4; solving for R1 yields R1 < 156 k; with 4% additional margin R1 < 156/1.04 = 150 k. Choose R1 = 147 k (E48 standard value) and, from the second of (2), R2 = 147/4.555 = 32.3 k; use 32.4 k (E48 standard value).
Note: In both examples the gate drivers will be disabled as Vcc falls below 9.75 V (nominal value), as the voltage on the EN pin falls 45 mV below VEN_On.
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SRK2000
Application information
5.1.3
Remote on/off control
Whichever configuration is used, since a voltage on the EN pin 45 mV below VEN_On disables the gate drivers, any small-signal transistor can be used to pull down the EN pin and force the gate drivers in an off state.
Finally, it should be noted that during power-up, power-down and under overload or short circuit conditions the gate drivers will be shut down if the Vcc voltage is insufficient: < VCCOff in case of pull-up resistor configuration, < 0.975VCC_G in case of resistor divider configuration (the coefficient 0.975 depends on the hysteresis on the enable pin threshold).
5.2
Drain voltage sensing
In the following explanations, it is assumed that the reader is familiar with the LLC resonant half-bridge topology and its waveforms, especially those on the secondary side with a center-tap transformer winding for full-wave rectification. To understand the polarity and the level of the current flowing in the SR MOSFETs (or their body diodes, or diodes in parallel to the MOSFETs) the IC is provided with two pins, DVS12, able to sense the voltage level of the MOSFET's drain.
Figure 7. Typical waveform seen on the drain voltage sensing pins
The logic that controls the driving of the two SR MOSFETs is based on two gate-driver state machines working in parallel in an interlocked way to avoid switching on both gate drivers at the same time. There are four significant drain voltage thresholds: the first one, VDVS1,2_A (= 1.4 V), sensitive to positive-going edges, arms the opposite gate driver (interlock function); the second one VDVS1,2_PT (=0.7 V), sensitive to negative-going edges provides a pre-trigger of the gate driver; the third one is the (negative) threshold VTH-ON that triggers the gate driver as the body diode of the SR MOSFET starts conducting; the fourth one is the internal (negative) threshold VDVS1,2_Off where the SR MOSFET is switched off (selectable between -12 mV or -25 mV by properly biasing the EN pin. The value of the on threshold VTH-ON is affected by the external resistor in series to each pin DVS1-2 needed essentially to limit the current that might be injected into the pins when one SR MOSFET is off and the other SR MOSFET is conducting. In fact, on the one hand, when one MOSFET is off (and the other one is conducting) its drain-to-source voltage is slightly
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Application information
SRK2000
higher than twice the output voltage; if this exceeds the voltage rating of the internal clamp (VccZ = 36 V typ.) a series resistor RD has to limit the injected current below an appropriate value, lower than the maximum rating (25 mA) and taking the related power dissipation into account. On the other hand, when current starts flowing into the body diode of one MOSFET (or in the diode in parallel with the MOSFET), the drain-to-source voltage is negative (-0.7 V); when the voltage on pins VDS1-2 reaches the threshold VDVS1,2_TH (-0.2V typ.) an internal current source IDVS1,2_On is activated; as this current exceeds 50 A, the gate of the MOSFET is turned on. Therefore, the actual triggering threshold can be determined by the following formula:
VTH-ON = RD IDVS1,2 On + VDVS1,2 _ TH
For instance, with RD = 2 k, the triggering threshold will be located at -(2 k 50 A) - 0.2 V = -0.3 V. To avoid false triggering of the gate driver, a debounce delay TPD_On (= 250 ns) is used after sourcing IDS1,2_On (i.e. the current sourced by the pin must exceed 50 A for more than 250 ns before the gate driver is turned on). This delay is not critical for the converter's efficiency because the initial current is close to zero or anyway much lower than the peak value. Once the SR MOSFET has been switched on, its drain-to-source voltage drops to a value given by the flowing current times the MOSFET RDS(on). Again, since the initial current is low, the voltage drop across the RDS(on) might exceed the turn-off threshold VDVS1,2_Off, and determine an improper turn-off. To prevent this, the state machine enables the turn-off comparator referenced to VDVS1,2_Off only in the second half of the conduction cycle, based on the information of the duration of the previous cycle. In the first half of the conduction cycle only an additional comparator, referenced to zero, is active to prevent the current of the SR MOSFET from reversing, which would impair the operation of the LLC converter. Once the threshold VDVS1,2_Off is crossed (in the second half of the conduction cycle) and the GATE is turned off, the current will again flow through the body diode causing the drainto-source voltage to have a negative jump, going again below VTH-ON. The interlock logic, however, prevents a false turn-on. It is worth pointing out that, due to the fact that each MOSFET is turned on after its body diode starts conducting, the ON transition happens with the drain-source voltage equal to the body diode forward drop; therefore there is neither Miller effect nor switching losses at MOSFET turn-on. Also at turn-off the switching losses are not present, in fact the current is always flowing from source to drain and, when the MOSFET is switched off, it goes on flowing through the body diode (or the external diode in parallel to the MOSFET). Unlike at turn-on, the turn-off speed is critical to avoid current reversal on the secondary side, especially when the converter operates above the resonance frequency, where the current flowing through the MOSFET exhibits a very steep edge while decreasing down to zero: the turn-off propagation TPD_Off delay has a maximum value of 60 ns. The interlock logic, in addition to checking for consistent secondary voltage waveforms (one MOSFET can be turned on only if the other one has a positive drain-to-source voltage > VDVS1,2_A) to prevent simultaneous conduction, allows only one switching per cycle: after one gate driver has been turned off, it cannot be turned on again before the other gate drive has had its own on/off cycle.
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SRK2000 Figure 8.
Application information Typical connection of the SRK2000 to the SR MOSFET
ISR1
To Xformer SRK2000 RD DVS1 SR1 RG
GD1
5.3
Gate driving
The IC is provided with two high-current gate-drive outputs (1A source and 3.5 A sink), each capable of driving one or more N-channel Power MOSFETs. Thanks to the programmable gate-drive UVLO, it is possible to drive both standard MOSFETs and logic level MOSFETs. The high-level voltage provided by the driver is clamped at VGDclamp (=12 V) to avoid excessive voltage levels on the gate in case the device is supplied with a high Vcc. The two gate drivers have a pull down capability that ensures the SR MOSFETs cannot be spuriously turned on even at low Vcc: in fact the drivers have a 1V (typical) UVLO saturation level at Vcc below the turn-on threshold.
5.4
Intelligent automatic sleep-mode
A unique feature of this IC is its intelligent automatic sleep-mode. The logic circuitry is able to detect a light load condition for the converter and stop gate driving, reducing also IC's quiescent consumption. This improves converter's efficiency at light load, where the power losses on the rectification body diodes (or external diodes in parallel to the MOSFETs) become lower than the power losses in the MOSFETs and those related to their driving. The IC is also able to detect an increase of the converter's load and automatically restart gate driving. The algorithm used by the intelligent automatic sleep-mode is based on a dual time measurement system. The duration of a switching cycle of an SR MOSFET (that is one half of the resonant converter switching period) is measured using a combination of the negative-going edge of the drain-to-source voltage falling below VDVS1,2_PT and the positive-going edge exceeding VDVS1,2_A.; the duration of the SR MOSFET conduction is measured from the moment its body diode starts conducting (drain-to source voltage falling below VTH-ON) to the moment the gate drive is turned off (in case the device is operating) or to the moment the body diode ceases to conduct (drain-to source voltage going over VTHON). While at full load the SR MOSFET conduction time occupies almost 100% of the switching cycle, as the load is reduced, the conduction time is reduced and as it falls below 40% (DOFF) of the SR MOSFET switching cycle the device enter sleep-mode. To prevent wrong decisions, the sleep mode condition must be confirmed for 16 consecutive switching
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Application information
SRK2000
cycles of the resonant converter (i.e. 16 consecutive cycles for each SR MOSFET of the center-tap). Once in sleep mode, SR MOSFET gate driving is re-enabled when the conduction time of the body diode (or the external diodes in parallel to the MOSFET) exceed 60% (DON) of the switching cycles. Also in this case the decision is made considering the measurement on 8 consecutive switching cycles (i.e. 8 consecutive cycles for each SR MOSFET of the centertap). Furthermore, after each sleep mode entering/exiting transition, the timing is ignored for a certain number of cycles, to let the resulting transient in the output current fade out; then the time check is enabled. The number of ignored resonant converter switching cycles switching cycles is 128 after entering sleep mode and 256 after exiting the sleep mode.
5.5
Layout guidelines
The IC is designed with two grounds, SGND and PGND. SGND is used as the ground reference for all the internal high precision analog blocks. PGND, instead, is the ground reference for all the noisy digital blocks, as well as the current return for the gate drivers. Additionally, it is also the ground for the ESD protection circuits. SGND is protected by ESD events versus PGND through two anti-parallel diodes. When laying out the PCB, care must be taken in keeping the source terminals of both SR MOSFETS as close to one another as possible and routing the trace that goes to PGND separately from the load current return path. This trace should be as short as possible and be as close to the physical source terminals as possible. Doing the layout as more geometrically symmetrical as possible will help make the circuit operation as much electrically symmetrical as possible. SGND should be directly connected to PGND using a path as short as possible (under the device body). Also drain voltage sensing should be done as physically close to the drain terminals as possible: any stray inductance involved by the load current that is in the drain-to-source voltage sensing circuit may significantly alter the current reading, leading to a premature turn-off of the SR MOSFET. It is worth mentioning that, especially in higher power applications or at higher operating frequencies, even the stray inductance of the internal wire bonding can be detrimental. In this case a cautious selection of the SR MOSFET package is required. The usage of bypass capacitors between Vcc and both SGND and PGND is recommended. They should be low-ESR, low-ESL type and located as close to the IC pins as possible. Sometimes, a series resistor (in the ten) between the converter's output voltage and the Vcc pin, forming an RC filter along with the bypass capacitor, is useful to get a cleaner Vcc voltage.
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SRK2000
Package mechanical data
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark.
Table 1. SO-8 mechanical data
mm. Dim. Min A 1.35 Typ Max 1.75 Min 0.053 Typ Max 0.069 inch
A1 A2 B C
D
0.10 1.10 0.33 0.19 4.80 3.80 1.27 5.80 0.25 0.40
0.25 1.65 0.51 0.25 5.00 4.00
0.004 0.043 0.013 0.007 0.189 0.15 0.050
0.010 0.065 0.020 0.010 0.197 0.157
(1)
E e H h L k ddd
6.20 0.50 1.27
0.228 0.010 0.016
0.244 0.020 0.050
0 (min.), 8 (max.) 0.10 0.004
1. Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.15mm (.006inch) in total (both side).
Figure 9.
Package dimensions
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Revision history
SRK2000
7
Revision history
Table 6.
Date 10-Aug-2010
Document revision history
Revision 1 Initial release. Changes
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SRK2000
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