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hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001570-04 1-1/1 no. dpbcl0001570-04 dec. 18, 2007 liquid crystal display module technical dat a TX07D24VM0AAA target specification 13-1/4 - 4/4 pa cking specifica tions 14-1/1 12-1/1 11-1/4 - 4/4 10-1/3 - 3/3 9-1/1 8-1/8 - 8/8 7-1/1 6-1/2 - 2/2 5-1/1 4-1/1 3-1/1 2-1/1 1-1/1 3284ps 2614-tx05d48vm1asa-1 3284ps 2613-tx05d48vm1asa-1 3284ps 2612-tx05d48vm1asa-1 3284ps 2611-tx05d48vm1asa-1 3284ps 2610-tx05d48vm1asa-1 dpbcl0001570-04 dpbcl0001570-04 dpbcl0001570-04 dpbcl0001570-04 dpbcl0001570-04 dpbcl0001570-04 dpbcl0001570-04 dpbcl0001570-04 dpbcl0001570-04 preca utions for use designa tion of lot ma rk preca utions in design visual inspection dimensiona l outline interfa ce block diagram optica l cha ra cteristics electrica l cha ra cteristics a bsolute ma ximum ra tings genera l da ta record of rev isions cov er page sheet no. item 14 13 12 11 10 9 8 7 6 5 4 3 2 1 no. contents (notes) 1. this document may, w holly or partially, be subject to change w ithout notice. 2. all rights are reserved ; no one is permitted to reproduce or duplicate, in any form, the w hole or part of this document w ithout hitachi's permission. 3. no one is permitted to explain contents of this document to third parties w ithout hitachi's permission. 4. hitachi w ill not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document, any previous reports or oral discussions. 5. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachi's products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 6. no license is granted by implication or otherw ise under any patents or other rights of any third party or hitachi, ltd. 7 . l ife support a ppl ica tions : hitachi's products are not authorized for use in life support systems. tentative www..net
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001570-04 2-1/1 record of revisions summary sheet no. date
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001570-04 3-1/1 3. general data (1) product name (2) module dimensions (3) active area dimensions ( 4 ) pix e l pit c h (5) resolution (6) color pixel arrangement (7) display mode (8) number of colors (9) view ing direction (10) backlight (11) weight (12) pow er supply voltage (13) interface i/o pow er supply (14) lcd driver ic (15) interface TX07D24VM0AAA 50.0 (w) mm x 70.0(h) mm x 2.15 (t) mm 43.2 (w) mm x 57.6 (h) mm 0.18 (w) mm x 0.18 (h) mm 240 x 3 (r, g, b) (w) x 320 (h) dots rgb vertical stripe transmissive type, normally black mode, ips 65,536 colors (8-bit, 16-bit cpu - i/f) 262,144 colors (9-bit, 18-bit cpu - i/f) - light emitting diode (led) five leds connected in series 14.5g vcc = 2.8 v (typ) 1.75v < v ddi/o < vcc s6d0154 8-bit / 9-bit / 16-bit / 18-bit cpu bus (80 cpu series)
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001570-04 4-1/1 4 . absol u te maximu m r atin gs 4. 1 electrical absolute maximum ratings of lcd 4. 2 environmental absolute maximum ratings notes (1) ta < 40 c: 85% rh max. ta > 40 c: absolute humidity must be low er than the humidity of 85%rh at 40 c. the polarizer quality is not assured by the above values. (2) background color slightly changes depending on ambient temperature and view ing angle. vss = 0 v notes (1) all voltage values are referred to gnd. (2) vddi/o < vcc (3) applies to the reset*, rd*, wr*, cs*, rs, vsync*, im0, im3 and db17-0 pins. (4) ta = 25 deg c, per piece of led. (5) relationship betw een ambient temperature and allow able forw ard current the operating current should be decided after considering the ambient maximum temperature of leds. (6) 100 pf, 1.5 kohm, 25 c, 70% rh. static electricity discharge point is the center of lcd's surface. (1), (4) v 5 - vr led reverse voltage kv 2 - - ma 35 - iled v vddi/o+0.3 -0.3 v in v 4.6 -0.3 vddi/o v 4.6 -0.3 vcc unit max min symbol (4), (5) (6) (1), (3) (1), (2) (1), (2) note static electricity led forw ard current input voltage pow er supply for interface pow er supply for logic and analog item no condensation note ( 2) comment corrosive gas humidity ambient temperature item 80 c -30 c 70 c -20 c max min max min not acceptable not acceptable note (1) note (1) storage operating ambient temperature ta ( c) 30 20 10 0 0 20 40 60 80 100 40 50 8.5 allowable forward current if ( ma )
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001570-04 5-1/1 5. electrical characteristics electrica l cha ra cteristics of lcd ta = 25 c, v ss = 0 v notes (1) applies to the reset*, rd*, wr*, cs*, rs, vsync*, im0, im3 and db17-0 pins. (2) applies to the flm and db17-0 pins. (3) vcc = vddi/o = 2.8 v, fflm = 85 hz (4) partial pattern (5) vcc = vddi/o = 2.8 v, standby mode (6) refer to item 4.1 40 lines: white 280 lines: black 40 lines: white 280 lines: black fflm = 85 hz 8-color mode (2) (1) power supply voltage f or intef ace vddi/o - 1.75 - vcc - note (6) (5) (4) (3) a ma a 1.0 - -1.0 - ili input/output leak current note ma hz 85 - - fflm frame frequency v power supply voltage f or logic and analog - ma/led v v v 0 0.8 x vddi/o 0.8 x vddi/o 1.0 8.0 12.0 0.2 x i/ovcc 0.2 x vddi/o vddi/o 2.88 20 3.2 0.1 6.0 9.3 2.8 2.72 standby partial all white "l" lev el "l" lev el "h" lev el "h" lev el - 3.5 - - - - - - - - - - - - i led vled icc vo vi vcc unit max ty p min condition sy mbol led forward current led forward voltage power supply current output voltage f or logic circuits input voltage f or logic circuits item
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001570-04 optica l cha ra cteristics of lcd ( ba cklight on) 6. optical characteristics 6-1/2 notes (1) definition of brightness "b" sensor : topcon / bm-5a or equivalent measurement point : center of lcd's active area 500 mm sensor lcd module common conditions for measurement measurement environment ambient temperature sequence pow er supply voltage backlight current : dark room : ta = 25 c : follow item 8.4.2, sequence. : vcc = vddi/o = 2.8 v : 20 ma (2) display image for measurement : white 80 - 0.38 0.32 0.26 0.37 0.31 0.25 0.16 0.10 0.04 0.20 0.14 0.08 0.65 0.59 0.53 0.40 0.34 0.28 0.41 0.35 0.29 0.69 0.63 0.57 70 40 - - 70 - 160 - - 160 - 400 200 - 300 200 max ty p min (1) (8) (2), (3), (5) (4), (6), (7) (1), (6) (1), (2) - ms % deg - cd/m 2 =0 =0 maximum gradient =0 , =0 ta=25 c =0 , =0 =90 , k> 10 =0 , k> 10 =0 , =0 =0 , =0 color tone (primary color) white blue green red y y y x x x y x tr + tf - 1 + 2 k b response time brightness uniformity view ing angle contrast ratio brightness note unit condition symbol item
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001570-04 6-2/2 (8) definition of optical response time black white black display data % t r: rise time 0 10 90 100 t f: fall time optical responce time k = brightness w hen displaying black raster brightness w hen displaying white raster (6) definition of contrast "k" (5) definition of the brightness uniformity (7) definition of view ing angle 1 and 2 = 0 sensor sensor : bm-5a or equivalent 2.0 1 2 1 < 0 < 2 view ing angle (4) definitions of and notes (3) measurement point 120 50 190 200 270 50 (pixel) p1 p2 p3 p4 p5 p6 p7 p9 p8 x y ( = 180 ) y' ( = 0 ) x' z 2 1
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001570-04 7-1/1 7. block diagram rs, cs*, wr*, rd*, v sy nc* gn d vcc reset* vddi/o db17- db0 s6d0154 tft-lcd 240(h) x rgb x 320(v) r g b im0, im3 g2 g320 s720 s1 g319 g1 led an ca led led led flm led
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001570-04 8-1/8 8. interface 8.1 internal pin connection (8 / 9 / 16/18-bit cpu bus corres pondence) suitable connector : hirose fh26-39s-0.3shw(5) line synchronous signal vsync* frame head pulse signal flm nc (no connection) nc gnd gnd 39 38 37 36 gnd f or led pow er supply for led nc (no connection) pow er supply for logic and analog pow er supply for interface chip select data/command identification write read data bus (instruction & display data) data bus (instruction & display data) data bus (instruction & display data) data bus (instruction & display data) data bus (instruction & display data) data bus (instruction & display data) data bus (instruction & display data) data bus (instruction & display data) data bus (instruction & display data) data bus (instruction & display data) data bus (instruction & display data) data bus (instruction & display data) data bus (instruction & display data) data bus (instruction & display data) data bus (instruction & display data) data bus (instruction & display data) reset data bus (instruction & display data) data bus (instruction & display data) mpu interface sw itching mpu interface sw itching id( v ddi/o) gnd pow er supply for logic and analog pow er supply for interface gnd 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 ca an nc v cc v cc vddi/o vddi/o cs* rs wr* rd* db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 reset* im3 im0 id gnd gnd function signal pin no. 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 function signal pin no.
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001570-04 8.2 cpu interfa ce mode setting 8-2/8 unused data bus pins are to be set at gnd or vddi/o. 8.2.2 unused data bus connection 8.2.3 display data input select the interface mode and colors by setting bits of im0 and im3. 8.2.1 cpu interface mode selection g0 g3 b1 b2 b3 b4 g1 g2 g3 g4 b0 b1 b2 b3 b4 b5 g0 g1 g2 g3 g4 g5 g3 g4 b0 b1 b2 b3 b4 b5 g0 g1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - b1 b2 b3 b4 g4 g5 r1 r2 r3 r4 r5 r0 g2 g5 r0 r1 r2 r3 r4 r5 g5 r1 r2 r3 r4 r0 r1 b5 b0 b5 b0 g0 g1 g2 r5 r0 r2 r3 r4 r5 transfer 2 transfer 2 transfer 1 transfer 1 transfer 1 transfer 1 8-bit 9-bit 16-bit 18-bit data bus db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 gnd vddi/o vddi/o vddi/o gnd gnd vddi/o gnd im3 im0 5 4 65k colors 262k colors 65k colors 262k colors signal pin no. 8-bit 9-bit 16-bit 18-bit 80-system bus interface gnd or vddi/o gnd or vddi/o gnd or vddi/o gnd or vddi/o gnd or vddi/o gnd or vddi/o gnd or vddi/o gnd or vddi/o gnd or vddi/o gnd or vddi/o gnd or vddi/o gnd or vddi/o gnd or vddi/o gnd or vddi/o gnd or vddi/o gnd or vddi/o gnd or vddi/o gnd or vddi/o gnd or vddi/o gnd or vddi/o gnd or vddi/o db9-0 db8-0 db9,db0 - db17-10 db17-9 db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 d b 11 db12 db13 db14 db15 db16 db17 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 db17-10 db8-1 db17-0 8-bit 9-bit 16-bit 18-bit signal pin no. unused data bus pins data bus pins bus interface
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001570-04 8-3/8 8.3.1 80-system bus interface timing characteristics <<18 bits / 16 bits / 9 bits / 8 bits>> 8.3 interface timing rs to cs, wr(rd) hold time rs to cs, wr(rd) setup time pulse w idth high pulse w idth low read write read write - - - - 3 11 ns ns tah80 tas80 - - 105 ns tcycw80 write read data hold time read data delay time write data hold time write data set up time cs towr(rd) time pulse rise / fall time read cycle time trdh80 trdd80 twdh80 twds80 tct80 twhr80 twhw80 twlr80 twlw80 tr , tf tcycr80 ns ns ns ns ns ns ns ns ns ns ns item - - 190 - - - - - - - - - - - - - - - 14 - - - 11 - 11 21 16 263 35 263 35 - 525 min max ty p unit symbol [normal write mode, vddi/o = 1.75 to 2.8 v] vcc = 2.8 v
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001570-04 8-4/8 notes (1) twlw80 and twlr80 are determined by the overlap period of low cs and low wr or low cs and low rd. vih vil vih vil write data voh 1 vol 1 voh 1 vol 1 read data trdh80 trdd80 twds80 twrh80 tcycw80,tcycr80 tr tf vih vil vih vil vih twlw80, twlr80 twhw80, twhr80 vil vih tas80 tah80 vih vil vih vil rs cs* wr* rd* db17-db0 db17-db0 bus timing tcw80
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001570-04 8.3.2 reset timing characteristics [ vddi/o=1.75 to 2.8v] vcc = 2.8 v reset low pulse w idth tres ms item - - 10 min max ty p unit symbol reset timing vil reset* vil tres notes (1) res et low puls e width s horter than 10us do not m ake res et. it m eans undes ired s hort puls e s uch as glitch, bouncing nois e or electros tatic dis charge do not caus e irregular s ys tem res et. pleas e refer to the table below. action not determined betw een 5 us and 10 us res et longer than 10 us no r es et shorter than 5 us itres puls e 1. us er m ay or m ay not us e resetb pin. in order to us e it, us er s hould s atis fy the conditions des cribed in the above tables . but when not wants to us e resetb, us er may fix this pin to vdd3 level because internally generated por (power-on-reset) isused. 2. spike rejection also applies during a valid reset pulse as shown below: 8-5/8
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001570-04 8-6/8 8.4.1 state transition diagram of operation mode 8.4 register setting vcc, vci : on display : off fosc : on internal power : off vcc, vci : on display : on 262k/65k-color full screen fosc : on internal power : on power off (a) power on reset (b) display on (h) external power off vcc, vci : on display : off fosc : off internal power : on (s) standby vcc, vci : on display : off fosc : off internal power : off (d) deep standby vcc, vci : on display : on 8-color 40-line display fosc : on internal power : on (p) partial
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001570-04 8-7/8 8.4.2 sequence last proposal last proposal 1 power on vcc on 1 display off r07h 0x0012 2 iovcc on 2 power control r10h 0x0100 3 vci on 3 r12h 0x2232 4reset wait 1 ms min. 4 vertical scroll control r30h 0x0000 5 reset* = "l" 5 vertical scroll control e r31h 0x0027 6 wait 1 ms min. 6 vertical scroll control s r32h 0x0000 7 reset* = "h" 7 vertical scroll control s r33h 0x0000 8 wait 10 ms min. 8 partial screen driving position end r34h 0x0027 9 partial screen driving position start r35h 0x0000 10 horizontal ram address position e r36h 0x00ef last proposal 11 horizontal ram address position s r37h 0x0000 1 power off vci off 12 vertical ram address position e r38h 0x0027 2 iovcc off13 vertical ram address position s r39h 0x0000 3 vcc off 14 wait 2 frames min. 15 8-color r07h 0x001a 16 wait 2 frames min. last proposal 17 display on r07h 0x101b 1 display off wait 20 ms min. 18 image refresh r20h 0x0000 2 power off vci off 19 r21h 0x0000 3 iovcc off 20 r22h - 4 vcc off 21 display data write 240x40 last proposal 1 display off r15h 0x0000 last proposal 2 r07h 0x0012 1 display off r07h 0x0012 3 wait 2 frames min. 2 power control r10h 0x0710 4 r07h 0x0000 3 power control r12h 0x2000 5 wait 1 frame min. 4 vertical scroll control r30h 0x0000 6 deep standby r10h 0x0002 5 vertical scroll control e r31h 0x013f 6 vertical scroll control s r32h 0x0000 7 vertical scroll control s r33h 0x0000 last proposal 8 partial screen driving position end r34h 0x013f 1 reset reset* = "l" 9 partial screen driving position start r35h 0x0000 2 wait 10 s min. 10 horizontal ram address position e r36h 0x00ef 3 reset* = "h" 11 horizontal ram address position s r37h 0x0000 4 wait 10 ms 12 vertical ram address position e r38h 0x013f otherwise, set csb as follows (low pulse width >10 s) 13 vertical ram address position s r39h 0x0000 and sequentially put "wait 10ms". 14 wait 2 frames min. 1 15 262k-color r07h 0x1012 16 wait 2 frames min. 17 display on r07h 0x1013 18 image refresh r20h 0x0000 19 r21h 0x0000 20 r22h - 21 display data write 240x320 2 wait 10ms last proposal 1 display off r15h 0x0000 2 r07h 0x0012 3 wait 2 frames min. 4 r07h 0x0000 5 wait 1 frame min. 6 standby r10h 0x0001 state (h) to (a) state (a) to (h) state (b) to (s) state (b) to (p) state (p) to (b) state (d) to (a) state (s) to (h) state (b) to (d)
hitachi displays, ltd. sh. no. page date dec. 18, 2007 dpbcl0001570-04 8-8/8 last proposal last proposal 1 power setting (1) r11h 0x001a 1 standby return r10h 0x0000 2 r12h 0x2000 2 wait 10ms 3 r13h 0x0070 3 power setting (1) r11h 0x001a 4 r14h 0x24e9 4 r12h 0x2000 5 equalizing control r15h 0x0070 5 r13h 0x0070 6 r10h 0x07 0 6 r14h 0x24e9 7 wait 10ms 7 equalizing control r15h 0x0070 8 power control (1) r11h 0x0110 8 r10h 0x07 0 9 wait 10ms 9 wait 10ms 10 power control (2) r11h 0x0312 10 power control (1) r11h 0x0110 11 wait 10ms 11 wait 10ms 12 power control (3) r11h 0x0712 12 power control (2) r11h 0x0312 13 wait 10ms 13 wait 10ms 14 power control (4) r11h 0x0f1a 14 power control (3) r11h 0x0712 15 wait 20ms 15 wait 10ms 16 power control (5) r11h 0x0f3a 16 power control (4) r11h 0x0f1a 17 wait 30ms 17 wait 20ms 18 driver output control r01h 0x0528 18 power control (5) r11h 0x0f3a 19 lcd-driving-waveform control r02h 0x0100 0x0000 19 wait 30ms 20 entry mode r03h 0x1130 20 driver output control r01h 0x0528 21 display control (1) r07h 0x0000 21 lcd-driving-waveform control r02h 0x0100 0x0000 22 display control (2) r08h 0x0808 (fp=8, bp=8) 22 entry mode r03h 0x1130 23 frame cycle control r0bh 0x2102 0x2107 23 display control (1) r07h 0x0000 24 external display interface control r0ch 0x0000 24 display control (2) r08h 0x0808 25 r0eh 0x0200 25 frame cycle control r0bh 0x2102 26 r0fh 0x1801 26 external display interface control r0ch 0x0000 27 wait 10ms 27 r0eh 0x0200 28 gamma setting r50h 0x0500 28 r0fh 0x1801 29 r51h 0x000b 29 wait 10ms 30 r52h 0x0200 30 gamma setting r50h 0x0500 31 r53h 0x0003 31 r51h 0x000b 32 r54h 0x0002 32 r52h 0x0200 33 r55h 0x0b00 33 r53h 0x0003 34 r56h 0x0005 34 r54h 0x0002 35 r57h 0x0300 35 r55h 0x0b00 36 r58h 0x0000 36 r56h 0x0005 37 r59h 0x0000 37 r57h 0x0300 38 vertical scroll control r30h 0x0000 38 r58h 0x0000 39 vertical scroll control e r31h 0x013f 39 r59h 0x0000 40 vertical scroll control s r32h 0x0000 40 vertical scroll control r30h 0x0000 41 vertical scroll control s r33h 0x0000 41 vertical scroll control e r31h 0x013f 42 horizontal ram address position e r36h 0x00ef 42 vertical scroll control s r32h 0x0000 43 horizontal ram address position s r37h 0x0000 43 vertical scroll control s r33h 0x0000 44 vertical ram address position e r38h 0x013f 44 r36h 0x00ef 45 vertical ram address position s r39h 0x0000 45 r37h 0x0000 46 wait 2 frames min. 46 r38h 0x013f 47 r07h 0x0012 47 r39h 0x0000 48 wait 2 frames min. 48 wait 2 frames min. 49 display on r07h 0x1013 flm on 49 r07h 0x0012 50 wait 2 frames min. 50 image refresh r20h 0x0000 51 display on r07h 0x1013 51 r21h 0x0000 52 r22h - 52 image refresh r20h 0x0000 53 display data write 240x320 53 r21h 0x0000 54 r22h - 55 display data write 240x320 state (a) to (b) state (s) to (b)

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