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vishay siliconix SI4276DY document number: 66599 s10-1289-rev. a, 31-may-10 www.vishay.com 1 dual n-channel 30 v (d-s) mosfet product summary v ds (v) r ds(on) ( )i d (a) a q g (typ.) channel 1 30 0.0153 at v gs = 10 v 8 e 8.4 0.0184 at v gs = 4.5 v 8 e channel 2 30 0.0280 at v gs = 10 v 8 3.6 0.0340 at v gs = 4.5 v 7.1 notes: a. based on t c = 25 c. b. surface mounted on 1" x 1" fr4 board. c. t = 10 s. d. maximum under steady state conditions is 107 c/w (ch 1) and 110 c/w (ch 2). e. package limited. absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol channel 1 channel 2 unit drain-source voltage v ds 30 v gate-source voltage v gs 20 continuous drain current (t j = 150 c) t c = 25 c i d 8 e 8 a t c = 70 c 8 e 6.4 t a = 25 c 8 b, c, e 6.8 b, c t a = 70 c 7.6 b, c 5.5 b, c pulsed drain current (10 s pulse width) i dm 50 30 source-drain current diode current t c = 25 c i s 3.0 2.3 t a = 25 c 1.7 b, c 1.7 b, c single pulse avalanche current l = 0.1 mh i as 20 10 avalanche energy e as 20 5 mj maximum power dissipation t c = 25 c p d 3.6 2.8 w t c = 70 c 2.3 1.8 t a = 25 c 2.1 b, c 2.0 b, c t a = 70 c 1.3 b, c 1.3 b, c operating junction and storage temperature range t j , t stg - 55 to 150 c thermal resistance ratings parameter symbol channel 1 channel 2 unit typical maximum typical maximum maximum junction-to-ambient b, d t 10 s r thja 47 60 58 62.5 c/w maximum junction-to-foot (drain) steady r thjf 30 35 38 45 s 1 d 1 g 1 d 1 s 2 d 2 g 2 d 2 so-8 5 6 7 8 top v ie w 2 3 4 1 orderin g information: SI4276DY-t1-ge3 (lead (p b )-free and halogen-free) n -channel mosfet d 1 g 1 s 1 d 2 g 2 s 2 n -channel mosfet features ? halogen-free according to iec 61249-2-21 definition ?trenchfet ? power mosfet ? 100 % r g te s t e d ? 100 % uis tested ? compliant to rohs directive 2002/95/ec applications ? dc/dc for notebook pc
www.vishay.com 2 document number: 66599 s10-1289-rev. a, 31-may-10 vishay siliconix SI4276DY specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. a max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a ch 1 30 v v gs = 0 v, i d = 250 a ch 2 30 v ds temperature coefficient v ds /t j i d = 250 a ch 1 29 mv/c i d = 250 a ch 2 30 v gs(th) temperature coefficient v gs(th) /t j i d = 250 a ch 1 - 5.2 i d = 250 a ch 2 - 4.4 gate threshold voltage v gs(th) v ds = v gs , i d = 250 a ch 1 1.2 2.5 v v ds = v gs , i d = 250 a ch 2 1.2 2.5 gate-body leakage i gss v ds = 0 v, v gs = 20 v ch 1 100 na ch 2 100 zero gate voltage drain current i dss v ds = 30 v, v gs = 0 v ch 1 1 a v ds = 30 v, v gs = 0 v ch 2 1 v ds = 30 v, v gs = 0 v, t j = 55 c ch 1 10 v ds = 30 v, v gs = 0 v, t j = 55 c ch 2 10 on-state drain current b i d(on) v ds = 5 v, v gs = 10 v ch 1 10 a v ds = 5 v, v gs = 10 v ch 2 10 drain-source on-state resistance b r ds(on) v gs = 10 v, i d = 9.5 a ch 1 0.0127 0.0153 v gs = 10 v, i d = 6.8 a ch 2 0.0230 0.0280 v gs = 4.5 v, i d = 8.7 a ch 1 0.0146 0.0184 v gs = 4.5 v, i d = 6.1 a ch 2 0.0280 0.0340 forward transconductance b g fs v ds = 15 v, i d = 9.5 a ch 1 43 s v ds = 15 v, i d = 6.8 a ch 2 17 dynamic a input capacitance c iss channel 1 v ds = 15 v, v gs = 0 v, f = 1 mhz channel 2 v ds = 15 v, v gs = 0 v, f = 1 mhz ch 1 1000 pf ch 2 366 output capacitance c oss ch 1 215 ch 2 82 reverse transfer capacitance c rss ch 1 85 ch 2 45 total gate charge q g v ds = 15 v, v gs = 10 v, i d = 9.5 a ch 1 17.2 26 nc v ds = 15 v, v gs = 10 v, i d = 6.8 a ch 2 7.3 15 channel 1 v ds = 15 v, v gs = 4.5 v, i d = 9.5 a channel 2 v ds = 15 v, v gs = 4.5 v, i d = 6.8 a ch 1 8.4 17 ch 2 3.6 8 gate-source charge q gs ch 1 3 ch 2 1.1 gate-drain charge q gd ch 1 2.6 ch 2 1.3 gate resistance r g f = 1 mhz ch 1 0.6 3.1 6.2 ch 2 0.5 2.6 5.2
document number: 66599 s10-1289-rev. a, 31-may-10 www.vishay.com 3 vishay siliconix SI4276DY notes: a. guaranteed by design, not subject to production testing. b. pulse test; pulse width 300 s, duty cycle 2 %. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indi cated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended per iods may affect device reliability. parameter symbol test conditions min. typ. a max. unit dynamic a tu r n - o n d e l ay t i m e t d(on) channel 1 v dd = 15 v, r l = 2 i d ? 7.6 a, v gen = 10 v, r g = 1 channel 2 v dd = 15 v, r l = 2.7 i d ? 5.5 a, v gen = 10 v, r g = 1 ch 1 8 16 ns ch 2 4 8 rise time t r ch 1 10 20 ch 2 8 16 turn-off delaytime t d(off) ch 1 20 30 ch 2 11 20 fall time t f ch 1 7 14 ch 2 7 14 tu r n - o n d e l ay t i m e t d(on) channel 1 v dd = 15 v, r l = 2 i d ? 7.6 a, v gen = 4.5 v, r g = 1 channel 2 v dd = 15 v, r l = 2.7 i d ? 5.5 a, v gen = 4.5 v, r g = 1 ch 1 14 21 ch 2 8 16 rise time t r ch 1 11 20 ch 2 10 20 turn-off delay time t d(off) ch 1 18 27 ch 2 10 20 fall time t f ch 1 7 14 ch 2 7 14 drain-source body diode characteristics continous source-drain diode current i s t c = 25 c ch 1 3 a ch 2 2.3 pulse diode forward current a i sm ch 1 50 ch 2 30 body diode voltage v sd i s = 7.6 a ch 1 0.82 1.2 v i s = 5.5 a ch 2 0.85 1.2 body diode reverse recovery time t rr channel 1 i f = 7.7 a, di/dt = 100 a/s, t j = 25 c channel 2 i f = 5.5 a, di/dt = 100 a/s, t j = 25 c ch 1 20 30 ns ch 2 13 20 body diode reverse recovery charge q rr ch 1 12 20 nc ch 2 6 12 reverse recovery fall time t a ch 1 11 ns ch 2 7 reverse recovery rise time t b ch 1 9 ch 2 6 specifications t j = 25 c, unless otherwise noted
www.vishay.com 4 document number: 66599 s10-1289-rev. a, 31-may-10 vishay siliconix SI4276DY channel-1 typical characteristics 25 c, unless otherwise noted output characteristics on-resistance vs. drain current gate charge 0 10 20 30 40 50 0.0 0.5 1.0 1.5 2.0 v gs =10vthru4v v gs =3v v ds - drain-to-source voltage (v) - drain current (a) i d 0.010 0.012 0.014 0.016 0.018 0.020 0 1020304050 v gs =10v v gs =4.5v - on-resistance ( ) r ds(on) i d - drain current (a) 0 2 4 6 8 10 0369121518 i d =9.5a v ds =7.5v v ds =24v v ds =15v - gate-to-source voltage (v) q g - total gate charge (nc) v gs transfer characteristics capacitance on-resistance vs. junction temperature 0 2 4 6 8 10 0.0 0.6 1.2 1.8 2.4 3.0 t c = 25 c t c = 125 c t c = - 55 c v gs - gate-to-source voltage (v) - drain current (a) i d 0 350 700 1050 1400 0 6 12 18 24 30 c iss c oss c rss v ds - drain-to-source voltage (v) c - capacitance (pf) 0.7 0.9 1.1 1.3 1.5 1.7 - 50 - 25 0 25 50 75 100 125 150 v gs =4.5v i d =8.7a v gs =10v;i d =9.5a t j - junction temperature (c) (normalized) - on-resistance r ds(on)
vishay siliconix SI4276DY document number: 66599 s10-1289-rev. a, 31-may-10 www.vishay.com 5 channel-1 typical characteristics 25 c, unless otherwise noted source-drain diode forward voltage threshold voltage 0.1 1 10 100 0.0 0.3 0.6 0.9 1.2 t j = 25 c t j = 150 c v sd - source-to-drain voltage (v) - source current (a) i s 0.9 1.2 1.5 1.8 2.1 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a (v) v gs(th) t j - temperature (c) on-resistance vs. gate-to-source voltage single pulse power, junction-to-ambient 0.010 0.015 0.020 0.025 0.030 0246810 t j = 25 c i d =9.5a t j = 125 c - on-resistance ( ) r ds(on) v gs - gate-to-source voltage (v) 0.001 0 1 100 40 60 10 0.1 time (s) 20 80 power (w) 0.01 safe operating area, junction-to-ambient 100 1 0.1 1 10 100 0.01 10 0.1 t a = 25 c single pulse 1s 10 s limited by r ds(on) * bvdss limited 1ms 100 s 10 ms dc 100 ms v ds - drain-to-source voltage (v) *v gs > minimum v gs at which r ds(on) is specied - drain current (a) i d
www.vishay.com 6 document number: 66599 s10-1289-rev. a, 31-may-10 vishay siliconix SI4276DY channel-1 typical characteristics 25 c, unless otherwise noted * the power dissipation p d is based on t j(max) = 150 c, using junction-to-case thermal resistanc e, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. it is used to deter mine the current rating, when this rating falls below the package limit. current derating* 0 3 6 9 12 15 0 25 50 75 100 125 150 package limited t c - case temperature (c) i d - drain current (a) power derating, junction-to-foot 0 1 2 3 4 5 0 25 50 75 100 125 150 t c - case temperature (c) power (w) power derating, junction-to-ambient 0.0 0.3 0.6 0.9 1.2 1.5 0 25 50 75 100 125 150 t a - ambient temperature (c) power (w)
vishay siliconix SI4276DY document number: 66599 s10-1289-rev. a, 31-may-10 www.vishay.com 7 channel-1 typical characteristics 25 c, unless otherwise noted normalized thermal transient impedance, junction-to-ambient s quare wave pul s e duration ( s ) normalized effective tran s ient thermal impedance 2 1 0.1 0.01 10 -3 10 -2 1 10 600 10 -1 10 -4 duty cycle = 0.5 0.2 0.1 0.05 0.02 s ingle pul s e 100 1. duty cycle, d = 2. per unit ba s e = r thja = 85 c/w 3. t jm - t a = p dm z thja (t) t 1 t 2 t 1 t 2 note s : 4. s urface mounted p dm normalized thermal transient impedance, junction-to-foot 10 -3 10 -2 110 10 -1 10 -4 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single pulse duty cycle = 0.5 square wave pulse duration (s) normalized effective transient thermal impedance
www.vishay.com 8 document number: 66599 s10-1289-rev. a, 31-may-10 vishay siliconix SI4276DY channel-2 typical characteristics 25 c, unless otherwise noted output characteristics on-resistance vs. drain current gate charge 0 6 12 18 24 30 0.0 0.5 1.0 1.5 2.0 v gs = 10 v thru 4 v v gs =3v v ds - drain-to-source voltage (v) - drain current (a) i d 0.000 0.015 0.030 0.045 0.060 0 5 10 15 20 25 30 v gs =10v v gs =4.5v - on-resistance ( ) r ds(on) i d - drain current (a) 0 2 4 6 8 10 02468 i d =6.8a v ds =7.5v v ds =24v v ds =15v - gate-to-source voltage (v) q g - total gate charge (nc) v gs transfer characteristics capacitance on-resistance vs. junction temperature 0 1 2 3 4 5 0.0 0.6 1.2 1.8 2.4 3.0 t c = 25 c t c = 125 c t c = - 55 c v gs - gate-to-source voltage (v) - drain current (a) i d 0 100 200 300 400 500 0 6 12 18 24 30 c iss c oss c rss v ds - drain-to-source voltage (v) c - capacitance (pf) 0.7 0.9 1.1 1.3 1.5 1.7 - 50 - 25 0 25 50 75 100 125 150 v gs =4.5v i d =6.1a v gs =10v;i d =6.8a t j - junction temperature (c) (normalized) - on-resistance r ds(on)
vishay siliconix SI4276DY document number: 66599 s10-1289-rev. a, 31-may-10 www.vishay.com 9 channel-2 typical characteristics 25 c, unless otherwise noted source-drain diode forward voltage threshold voltage 0.1 1 10 100 0.0 0.3 0.6 0.9 1.2 t j = 25 c t j = 150 c v sd - source-to-drain voltage (v) - source current (a) i s 1.1 1.3 1.5 1.7 1.9 2.1 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a (v) v gs(th) t j - temperature (c) on-resistance vs. gate-to-source voltage single pulse power, junction-to-ambient 0 0.015 0.030 0.045 0.060 0246810 t j = 25 c i d =6.8a t j = 125 c - on-resistance ( ) r ds(on) v gs - gate-to-source voltage (v) 0 10 20 30 40 50 power (w) time (s) 10 1000 0.1 0.01 0.001 100 1 safe operating area, junction-to-ambient 100 1 0.1 1 10 100 0.01 10 0.1 t a = 25 c single pulse 1s 10 s limited by r ds(on) * bvdss limited 1ms 100 s 10 ms dc 100 ms v ds - drain-to-source voltage (v) *v gs > minimum v gs at which r ds(on) is specied - drain current (a) i d
www.vishay.com 10 document number: 66599 s10-1289-rev. a, 31-may-10 vishay siliconix SI4276DY channel-2 typical characteristics 25 c, unless otherwise noted * the power dissipation p d is based on t j(max) = 150 c, using junction-to-case thermal resistanc e, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. it is used to deter mine the current rating, when this rating falls below the package limit. current derating* 0 2 4 6 8 10 0 255075100125150 package limited t c - case temperature (c) i d - drain current (a) power derating, junction-to-foot 0 1 2 3 4 0 25 50 75 100 125 150 t c - case temperature (c) power (w) power derating, junction-to-ambient 0.0 0.3 0.6 0.9 1.2 1.5 0 25 50 75 100 125 150 t a - ambient temperature (c) power (w)
vishay siliconix SI4276DY document number: 66599 s10-1289-rev. a, 31-may-10 www.vishay.com 11 channel-2 typical characteristics 25 c, unless otherwise noted vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?66599 . normalized thermal transient impedance, junction-to-ambient 10 -3 10 -2 1 10 1000 10 -1 10 -4 100 0.2 0.1 0.05 0.02 s q uare wave pulse duration (s) normalized ef fective transient thermal impedance 1 0.1 0.01 single pulse t 1 t 2 notes: p dm 1. duty cycle, d = 2. per unit base = r thja = 90 c/w 3. t jm - t a = p dm z thja (t) t 1 t 2 4. surface mounted duty cycle = 0.5 normalized thermal transient impedance, junction-to-foot 10 -3 10 -2 0 1 1 10 -1 10 -4 0.2 0.1 0.05 duty cycle = 0.5 s q uare wave pulse duration (s) normalized effective transient thermal impedance 1 0.1 0.01 0.02 single pulse
vishay siliconix package information document number: 71192 11-sep-06 www.vishay.com 1 dim millimeters inches min max min max a 1.35 1.75 0.053 0.069 a 1 0.10 0.20 0.004 0.008 b 0.35 0.51 0.014 0.020 c 0.19 0.25 0.0075 0.010 d 4.80 5.00 0.189 0.196 e 3.80 4.00 0.150 0.157 e 1.27 bsc 0.050 bsc h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.50 0.93 0.020 0.037 q0808 s 0.44 0.64 0.018 0.026 ecn: c-06527-rev. i, 11-sep-06 dwg: 5498 4 3 1 2 5 6 8 7 h e h x 45 c all le a d s q 0.101 mm 0.004" l ba 1 a e d 0.25 mm (g a ge pl a ne) s oic (narrow): 8-lead jedec p a rt n u m b er: m s -012 s
vishay siliconix trenchfet ? power mosfets application note 808 mounting little foot ? , so-8 power mosfets application note document number: 70740 www.vishay.com revision: 18-jun-07 1 wharton mcdaniel surface-mounted little foot power mosfets use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. leadframe materials and design, molding compounds, and die attach materials have been changed, while the footpr int of the packages remains the same. see application note 826, recommended minimum pad patterns with outline drawin g access for vishay siliconix mosfets, ( http://www.vishay.com/ppg?72286 ), for the basis of the pad design for a little foot so-8 power mosfet. in converting this recommended minimum pad to the pad set for a power mosfet, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package. in the case of the so-8 p ackage, the thermal connections are very simple. pins 5, 6, 7, and 8 are the drain of the mosfet for a single mosfet package and are connected together. in a dual package, pi ns 5 and 6 are one drain, and pins 7 and 8 are the other drain. for a small-signal device or integrated circuit, typical co nnections would be made with traces that are 0.020 inches wi de. since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. the total cross section of the copp er may be adequate to carry the current required for the a pplication, but it presents a large thermal impedance. also , heat spreads in a circular fashion from the heat source. in this case the drain pins are the heat sources wh en looking at heat spread on the pc board. figure 1. single mosfet so-8 pad pattern with copper spreading figure 2. dual mosfet so-8 pad pattern with copper spreading the minimum recommended pad patterns for the single-mosfet so-8 with copp er spreading (figure 1) and dual-mosfet so-8 with copper spreading (figure 2) show the starting point for utilizing th e board area available for the heat-spreading copper. to creat e this pattern, a plane of copper overlies the drain pins . the copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat fr om the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. these patterns use all the available area underneath the body for this purpose. since surface-mounted packag es are small, and reflow soldering is the most comm on way in which these are affixed to the pc board, ?t hermal? connections from the planar copper to the pads have not been used. even if additional planar copper area is used, there should be no problems in the soldering process. the actual solder connections are defined by the solder mask openings. by combining the basic footprint wi th the copper plane on the drain pins, the solder mask ge neration occurs automatically. a final item to keep in mind is the width of the power traces. the absolute minimum pow er trace width must be determined by the amount of current it has to carry. for thermal reasons, this minimum width should be at least 0.020 inches. the use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device. 0.027 0.69 0.07 8 1.9 8 0.2 5.07 0.196 5.0 0.2 88 7.3 0.050 1.27 0.027 0.69 0.07 8 1.9 8 0.2 5.07 0.0 88 2.25 0.2 88 7.3 0.050 1.27 0.0 88 2.25
application note 826 vishay siliconix www.vishay.com document number: 72606 22 revision: 21-jan-08 application note recommended minimum pads for so-8 0.246 (6.248) recommended mi nimum pads dimensions in inches/(mm) 0.172 (4.369) 0.152 (3.861) 0.047 (1.194) 0.028 (0.711) 0.050 (1.270) 0.022 (0.559) return to index return to index
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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