v ishay siliconix spice device model SI6866BDQ dual n-channel 2.5-v (g-s) mosfet characteristics ? n-channel vertical dmos ? macro model (subcircuit model) ? level 3 mos ? apply for both linear and sw itching application ? accurate over the ? 55 to 125 c temperature range ? model the gate charge, transient, and diode reverse recovery characteristics description the attached spice model descri bes the ty pical electrical characteristics of the n-channel ve rtical dmos. the subcircuit model is extracted and optimized over the ? 55 to 125 c temperature ranges under the puls ed 0-v to 5-v gate drive. the saturated output impedance is best fit at the gate bias near the threshold voltage. a novel gate-to-drain feedback capac itance netw o rk is used to model the gate charge characteristics w h ile avoiding convergence difficulties of the sw itched c gd model. all model parameter values are optimized to provide a best fit to the m easured electrical data and are not intended as an exact phy sical interpretation of the device. subcircuit model schematic this document is intended as a spice modeling guideline and does not constitute a commercial product data sheet. designers sho uld refer to the appropriate data sheet of the same number fo r guaranteed specific ation limits. 1 www. vi s h a y .com document number: 72703 s-60146 ? rev . b , 13-feb-06
v ishay siliconix spice device model SI6866BDQ specificat ions (t j = 2 5 c unless ot herwise not e d) pa ra me te r s y m b o l te s t c o n d i t i o n simulated data measu red data unit static gate threshold voltage v gs(t h ) v ds = v gs , i d = 250 a 1.1 v on-state drain current a i d(o n ) v ds = 5 v, v gs = 4.5 v 115 a v gs = 4.5 v, i d = 6 a 0.020 0.022 drain-source on-state resistance a r d s (on) v gs = 2.5 v, i d = 4.9 a 0.032 0.033 ? forw ard transconductance a g fs v ds = 10 v, i d = 6 a 21 25 forw ard voltage a v sd i s = 1.5 a, v gs = 0 v 0.80 0.75 v dy namic b total gate charge q g 7.2 7.5 gate-source charge q gs 1.4 1.4 gate-drain charge q gd v ds = 10 v, v gs = 4.5 v, i d = 6 a 2.2 2.2 nc turn-on delay time t d(on) 2 6 4 5 ris e time t r 3 8 5 3 turn-of f delay time t d(off) 3 0 3 0 fall time t f v dd = 10 v, r l = 10 ? i d ? 1 a, v gen = 4.5 v, r g = 6 ? 10 13 ns not e s a. pulse test; pulse w i dth 300 s, duty cy cle 2%. b. guaranteed by design, not s ubject to production testing. 2 www. vi s h a y .com document number: 72703 s-60146 ? rev . b, 13-feb-06
v ishay siliconix spice device model SI6866BDQ comparison of model wit h measured dat a (t j =2 5 c unless ot herwise not e d) 3 www. vi s h a y .com document number: 72703 s-60146 ? rev . b , 13-feb-06
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