document number: 66540 www.vishay.com s10-0749-rev. a, 05-apr-10 1 p-channel 20 v (d-s) mosfet spice device model SI2323CDS vishay siliconix description the attached spice model desc ribes the typical electrical characteristics of the p-channel vertical dmos. the subcircuit model is extracted and optimized over the - 55 c to + 125 c temperature ranges under the pulsed 0 v to 5 v gate drive. the sa turated output impedanc e is best fit at the gate bias near the threshold voltage. a novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched c gd model. all model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. characteristics ? p-channel vertical dmos ? macro model (subcircuit model) ?level 3 mos ? apply for both linear and switching application ? accurate over the - 55 c to + 125 c temperature range ? model the gate charge, transient, and diode reverse recovery characteristics subcircuit model schematic note this document is intended as a spice modeling guideline and do es not constitute a commercial product datasheet. designers shoul d refer to the appropriate datasheet of the same number for guaranteed specification limits. d s dbd c gs m 1 g 3 r 1 m 2 gx r g c gd gy etcv + C
www.vishay.com document number: 66540 2 s10-0749-rev. a, 05-apr-10 spice device model SI2323CDS vishay siliconix notes a. pulse test; pulse width ? 300 s, duty cycle ? 2 %. b. guaranteed by design, not su bject to production testing. specifications t j = 25 c, unless otherwise noted parameter symbol test conditions simulated data measured data unit static gate-source threshold voltage v gs(th) v ds = v gs , i d = - 250 a 0.75 - v drain-source on-state resistance a r ds(on) v gs = - 4.5 v, i d = - 4.6 a 0.032 0.032 ? v gs = - 2.5 v, i d = - 4.1 a 0.039 0.041 forward transconductance a g fs v ds = - 5 v, i d = - 4.6 a 18 20 s diode forward voltage v sd i s = - 3.7 a - 0.75 - 0.80 v dynamic b input capacitance c iss v ds = - 10 v, v gs = 0 v, f = 1 mhz 1080 1090 pf output capacitance c oss 157 155 reverse transfer capacitance c rss 136 135 total gate charge q g v ds = - 10 v, v gs = - 4.5 v, i d = - 4.6 a 12 16 nc v ds = - 10 v, v gs = - 2.5 v, i d = - 4.6 a 7.7 9 gate-source charge q gs 2.5 2.5 gate-drain charge q gd 3.2 3.2
document number: 66540 www.vishay.com s10-0749-rev. a, 05-apr-10 3 spice device model SI2323CDS vishay siliconix comparison of model with measured data t j = 25 c, unless otherwise noted note dots and squares represent measured data. i d - drain current (a) v d s - drain-to- s ource voltage (v) i d - drain current (a) c - capacitance (pf) v d s - drain-to- s ource voltage (v) q g - total g ate charge (nc) v gs - g ate-to- s ource voltage (v) i s - s ource current (a) v s d - s ource-to-drain voltage (v) r d s (on) - on-re s i s tance ( ) i d - drain current (a) v gs - g ate-to- s ource voltage (v) 0 5 10 15 20 0.0 0.5 1.0 1.5 2.0 v gs = 2 v v gs = 5 v, 4 v, 3.5 v, 3 v, 2.5 v 0 1 2 3 4 0.0 0.3 0.6 0.9 1.2 1.5 t j = 125 c t j = - 55 c t j = 25 c 0.00 0.02 0.04 0.06 0.08 0.10 0 5 10 15 20 v gs = 4.5 v v gs = 2.5 v 0 450 900 1350 1800 2250 0 5 10 15 20 c i ss c o ss c r ss 0 1 2 3 4 5 048121620 v d s = 10 v v d s = 24 v i d = 4.6 a 0.1 1 10 100 0 0.3 0.6 0.9 1.2 t j = 150 c t j = 25 c
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