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51309hkim 20070328-s00008,s00009 no.a0788-1/22 specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. LC72131K LC72131Km overview the LC72131K and LC72131Km are pll frequency synthesizers for use in tuners in radio/cassette players. they allow high-performance am/fm tuners to be implemented easily. features ? high speed programmable dividers ? fmin: 10 to 160mhz ?????? ??.. pulse swallower (built-in divide-by-two prescaler) ? amin: 2 to 40mhz ?????????. pulse swallower 0.5 to 10mhz ????????.. direct division ? if counter ? ifin: 0.4 to 12mhz ?????????. am/fm if counter ? reference frequencies ? twelve selectable frequencies (4.5 or 7.2mhz crystal) ? 100, 50, 25, 15, 12.5, 6.25, 3.125, 10, 9, 5, 3, 1khz ? phase comparator ? dead zone control ? unlock detection circuit ? deadlock clear circuit ? built-in mos transistor for forming an active low-pass filter ? i/o ports ? dedicated output ports: 4 ? input or output ports: 2 ? support clock time base output continued on next page. ordering number : ena0788 cmos ic pll frequency synthesizer ? ccb is a registered trademark of sanyo semiconductor co., ltd. ? ccb is sanyo semiconductor's original bus format. all bus addresses are managed by sanyo semiconductor for this format.
LC72131K, 72131km no.a0788-2/22 continued from preceding page. ? serial data i/o ? support ccb format communicatio n with the system controller. ? operating ranges ? supply voltage ........................4.5 to 5.5v ? operating temperature ............ -40 to +85 c ? packages ? dip22s/mfp20 specifications absolute maximum ratings at ta = 25 c, v ss = 0v parameter symbol pins conditions ratings unit supply voltage v dd max v dd -0.3 to +7.0 v v in 1 max ce, cl, di, ain -0.3 to +7.0 v v in 2 max xin, fmin, amin, ifin -0.3 to v dd +0.3 v maximum input voltage v in 3 max io1 , io2 -0.3 to +15 v v o 1 max do -0.3 to +7.0 v v o 2 max xout, pd -0.3 to v dd +0.3 v maximum output voltage v o 3 max bo1 to bo4 , io1 , io2 , aout -0.3 to +15 v i o 1 max bo1 0 to 3.0 ma i o 2 max do, aout 0 to 6.0 ma maximum output current i o 3 max bo2 to bo4 , io1 , io2 0 to 10 ma ta 85 c [LC72131K] 350 mw allowable power dissipation pd max ta 85 c [LC72131Km] 180 mw operating temperature topr -40 to +85 c storage temperature tstg -55 to +125 c note 1: power pins v dd and v ss : insert a capacitor with a capacitance of 2,000pf or higher between these pins when using the ic. LC72131K, 72131km no.a0788-3/22 allowable operating ranges at ta = -40 c to +85 c, v ss = 0v ratings parameter symbol pins conditions min typ max unit supply voltage v dd v dd 4.5 5.5 v v ih 1 ce, cl, di 0.7v dd 6.5 v input high-level voltage v ih 2 io1 , io2 0.7v dd 13 v input low-level voltage v il ce, cl, di, io1 , io2 0 0.3v dd v v o 1 do 0 6.5 v output voltage v o 2 bo1 to bo4 , io1 , io2 , aout 0 13 v fin1 xin v in 1 1.0 8.0 mhz fin2 fmin v in 2 10 160 mhz fin3 amin v in 3 2.0 40 mhz fin4 amin v in 4 0.5 10 mhz input frequency fin5 ifin v in 5 0.4 12 mhz supported crystals x'tal xin, xout note 1 4.0 8.0 mhz v in 1 xin fin1 400 1500 mvrms v in 2-1 fmin f=10 to 130mhz 40 1500 mvrms v in 2-2 fmin f=130 to 160mhz 70 1500 mvrms v in 3 amin fin3 40 1500 mvrms v in 4 amin fin4 40 1500 mvrms v in 5 ifin fin5 (ifs=1) 40 1500 mvrms input amplitude high-level clock pulse width t h cl [figure 1][figure 2] 160 ns low-level clock pulse width v in 6 ifin fin5 (ifs=0) 70 1500 mvrms data setup time tsu di, cl note 2 0.75 s data hold time thd di, cl note 2 0.75 s clock low-level time tcl cl note 2 0.75 s clock high-level time tch cl note 2 0.75 s ce wait time tel ce, cl note 2 0.75 s ce setup time tes ce, cl note 2 0.75 s ce hold time teh ce, cl note 2 0.75 s data latch change time tlc note 2 0.75 s tdc do, cl data output time tdh do, ce differs depending on the value of the pull-up resistor. note 2 0.35 s note 1: recommended crystal oscillator ci values: ci 120 (for a 4.5mhz crystal) ci 70 (for a 7.2mhz crystal) the characteristics of the oscillation circuit depends on the printed circuit board, circuit constants, and other factors. therefore we recommend cons ulting with the anufacturer of the crystal for evaluation and reliability. note 2: refer to "serial data timing". LC72131K, 72131km no.a0788-4/22 electrical characteristics in the allowable operating ranges ratings parameter symbol pins conditions min typ max unit rf1 xin 1.0 m rf2 fmin 500 k rf3 amin 500 k built-in feedback resistance rf4 ifin 250 k rpd1 fmin 200 k built-in pull-down resistor rpd2 amin 200 k hysteresis vhys ce, cl, di, io1 , io2 0.1v dd v output high-level voltage v oh pd i o =1ma v dd -0.1 v v ol 1 pd i o =1ma 1.0 v i o =0.5ma 0.5 v v ol 2 bo1 i o =1ma 1.0 v i o =1ma 0.2 v v ol 3 do i o =5ma 1.0 v i o =1ma 0.2 v i o =5ma 1.0 v v ol 4 bo2 to bo4 , io1 , io2 i o =8ma 1.6 v output low-level voltage v ol 5 aout i o =1ma ain=1.3v 0.5 v i ih 1 ce, cl, di v i =6.5v 5.0 a i ih 2 io1 , io2 v i =13v 5.0 a i ih 3 xin v i =v dd 2.0 11 a i ih 4 fmin, amin v i =v dd 4.0 22 a i ih 5 ifin v i =v dd 8.0 44 a input high-level current i ih 6 ain v i =6.5v 200 na i il 1 ce, cl, di v i =0v 5.0 a i il 2 io1 , io2 v i =0v 5.0 a i il 3 xin v i =0v 2.0 11 a i il 4 fmin, amin v i =0v 4.0 22 a i il 5 ifin v i =0v 8.0 44 a input low-level current i il 6 ain v i =0v 200 na ioff1 bo1 to bo4 , aout, io1 , io2 v o =13v 5.0 a output off leakage current ioff2 do v o =6.5v 5.0 a high-level three-state off leakage current ioffh pd v o =v dd 0.01 200 na low-level three-state off leakage current ioffl pd v o =0v 0.01 200 na input capacitance cin fmin 6 pf i dd 1 v dd x'tal=7.2mhz f in 2=130mhz v in 2=40mvrms 5 10 ma i dd 2 v dd pll block stopped (pll inhibit) x'tal oscillator operating (x'tal=7.2mhz) 0.5 ma current drain i dd 3 v dd pll block stopped x'tal oscillator operating 10 a LC72131K, 72131km no.a0788-5/22 serial data timing package dimensions package dimensions unit : mm (typ) unit : mm (typ) 3059a [LC72131K] 3036c [LC72131Km] tcl teh tes thd tsu old new tlc tdh tdc tel tch when stopped with cl high v il v il v ih v ih v ih v ih v ih v ih v il v il v il do internal data latch cl di ce tcl teh tes thd tsu old new tlc tdh tdc tdc tel tch when stopped with cl low v il v il v il v ih v ih v ih v ih v ih v ih v il v il v il do internal data latch cl di ce sanyo : dip22s(300mil) 21.0 6.4 0.95 0.48 111 22 12 (0.8) 1.78 (3.25) 3.3 3.9 max 0.51min 7.62 0.25 sanyo : mfp20(300mil) 1 20 10 11 12.5 0.15 1.27 0.35 (0.4) 1.7max (1.5) 0.1 5.4 0.63 7.6 LC72131K, 72131km no.a0788-6/22 pin assignments block diagram io2 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 xout ifin nc amin fmin v dd pd ain aout v ss ce nc xin do cl di bo3 bo2 bo1 io1 bo4 LC72131K top view pd ifin amin ce di cl do v ss v dd fmin xout xin universal counter unlock detector phase detector charge pump reference divider data shift register latch 12bits programmable divider swallow counter 1/16,1/17 4bits power on reset ccb i/f 1/2 ain aout bo1 bo2 bo3 bo4 io1 io2 io2 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 xout ifin amin fmin v dd pd ain aout v ss ce xin do cl di bo3 bo2 bo1 io1 bo4 LC72131Km top view LC72131K, 72131km no.a0788-7/22 pin functions pin no. symbol LC72131K LC72131Km type functions circuit configuration xin xout 1 22 1 20 x'tal osc crystal resonator connection (4.5mhz/7.2mhz) fmin 16 14 local oscillator signal input fmin is selected when the serial data input dvs bit is set to 1. the input frequency range is from 10 to 160mhz. the input signal passes through the internal divide-by-two prescaler and is input to the swallow counter. the divisor can be in the range 272 to 65535. however, since the signal has passed through the divide-by-two prescaler, the actual divisor is twice the set value. amin 15 13 local oscillator signal input amin is selected when the serial da ta input dvs bit is set to 0. when the serial data input sns bit is set to 1: ? the input frequency range is 2 to 40mhz. ? the signal is directly i nput to the swallow counter. ? the divisor can be in the range 272 to 65535, and the divisor used will be the value set. when the serial data input sns bit is set to 0: ? the input frequency range is 0.5 to 10mhz. ? the signal is directly input to a 12-bit programmable divider. ? the divisor can be in the range 4 to 4095, and the divisor used will be the value set. ce 3 2 chip enable set this pin high when inputting (di) or outputting (do) serial data. di 4 3 input data inputs serial data tr ansferred from the cont roller to the lc72131. cl 5 4 clock used as the synchronization clock when inputting (di) or outputting (do) serial data. do 6 5 output data outputs serial data transferred from the lc72131 to the controller. the content of the output data is determined by the serial data doc0 to doc2. v dd 17 15 power supply the lc72131 power supply pin (v dd =4.5 to 5.5v) the power on reset circuit operates when power is first applied. - v ss 21 19 ground the lc72131 ground - bo1 bo2 bo3 bo4 7 8 9 10 6 7 8 9 output port dedicated output pins the output states are determined by bo1 to bo4 bits in the serial data. data: 0=open, 1=low a time base signal (8hz) can be output from the bo1 pin. (when the serial data tbc bit is set to 1.) care is required when using the bo1 pin, since it has a higher on impedance that the other output ports (pins bo2 to bo4 ). io1 io2 11 13 10 12 i/o port i/o dual-use pins the direction (input or output) is determined by bits ioc1 and ioc2 in the serial data. data: 0=input port, 1=output port when specified for use as input ports: the state of the input pin is tr ansmitted to the controller over the do pin. input state: low=0 data value high=1 data value when specified for use as output ports: the output states are determined by the io1 and io2 bits in the serial data. data: 0=open, 1=low these pins function as input pins following a power on reset. continued on next page. s s s s LC72131K, 72131km no.a0788-8/22 continued from preceding page. pin no. symbol LC72131K LC72131Km type functions circuit configuration pd 18 16 charge pump output pll charge pump output when the frequency generated by dividing the local oscillator frequency by n is higher than the reference frequency, a high level is output from the pd pin. similarly, when that frequency is lower, a low level is output. the pd pin goes to the high impedance state when the frequencies match. ain aout 19 20 17 18 lpf amplifier transistors the n-channel mos transistor used for the pll active low-pass filter. ifin 12 11 if counter accepts an input in the frequency range 0.4 to 12mhz. the input signal is directly tr ansmitted to the if counter. the result is output starting the msb of the if counter using the do pin. four measurement periods are supported: 4, 8, 32, and 64ms. di control data (seria l data input) structure [1] in1 mode [2] in2 mode r2 r1 r0 (3) if-ctr xs cte dvs sns p15 p14 p13 p12 p11 p10 (1) p-ctr (2) r-ctr p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 r3 address 0 0 1 0 1 0 0 di 0 first data in1 test1 test0 ifs (12) test (11) ifs (10) pd-c (5) o-port (13) don?t care (6) do-c (9) time dlc tbc gt1 gt0 dz1 dz0 ul1 ul0 doc2 doc1 (7) unlock (4) io-c (8) dz-c (3) if-ctr doc0 dnc bo4 bo3 bo2 bo1 io2 io1 ioc2 ioc1 test2 address 0 0 1 0 1 0 0 di 1 first data in2 LC72131K, 72131km no.a0788-9/22 control data functions no. control block/data functions related data (1) programmable divider data p0 to p15 dvs, sns data that sets the divisor of the programmable divider. a binary value in which p15 is the msb. the lsb changes depending on dvs and sns. (*: don?t care) note: p0 to p3 are ignored when p4 is the lsb. selects the signal input pin (amin or fmin) for the programmable divider, switches the input frequency range. (*: don?t care) note: see the ?programmable divider structure? item for more information. (2) reference divider data r0 to r3 xs reference frequency (fref) selection data. note *: pll inhibit the programmable divider block and the if counter block are stopped, the fmin, amin, and ifin pins are set to the pull-down state (ground), and the charge pump goes to the high impedance state. crystal resonator selection xs=0: 4.5mhz xs=1: 7.2mhz the 7.2mhz frequency is selected after the power-on reset. (3) if counter control data cte gt0, gt1 if counter measurement start data cte=1: counter start =0: counter reset determines the if counter measurement period. note: see the ?if counter structure? item for more information. ifs continued on next page. twice the value of the setting the value of the setting the value of the setting 272 to 65535 272 to 65535 4 to 4095 actual divisor divisor setting (n) lsb sns p0 p0 p4 * 1 0 1 0 0 dvs 10 to 160mhz 2 to 40mhz 0.5 to 10mhz fmin amin amin input frequency range input pin sns * 1 0 1 0 0 dvs 1 * pll inhibit * pll inhibit + x'tal osc stop 1 0 1 1 1 1 1 0 1 0 0 1 1 1 1 3 15 10 9 5 1 0 1 0 1 0 0 1 1 0 0 0 0 1 1 1 1 100khz 50 25 25 12.5 6.25 3.125 3.125 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 reference frequency r0 r1 r2 r3 wait time (ms) measurement time (ms) gt0 gt1 3 to 4 3 to 4 7 to 8 7 to 8 4 8 32 64 0 1 0 1 0 0 1 1 LC72131K, 72131km no.a0788-10/22 continued from preceding page. no. control block/data functions related data (4) i/o port specification data ioc1, ioc2 specifies the i/o direction for the bidirectional pins io1 and io2 . data: 0=input mode, 1=output mode (5) output port data bo1 to bo4 io1, io2 data that determines the output from the bo1 to bo4 , io1 and io2 output ports data: 0=open, 1=low the data=0 (open) state is sele cted after the power-on reset. ioc1 ioc2 (6) do pin control data doc0 doc1 doc2 data that determines the do pin output the open state is selected after the power-on reset. note: 1. end-uc: check for if counter measurement completion (1) when end-uc is set and the if counter is started (i.e., when cte is changed from zero to one), the do pin automatically goes to the open state. (2) when the if counter meas urement completes, the do pin goes low to indicate the measurement completion state. (3) depending on serial data i/o (ce: high) the do pin goes to the open state. note: 2. goes to the open state if the i/ o pin is specified to be an output port. caution: the state of the do pin during a data input period (an in1 or in2 mode period with ce high) will be open, regardless of the state of the do control data (doc0 to doc2). also, the do pin during a data output period (an out mode period with ce high) will output the contents of the internal do serial data in synchronization with the cl pin signal, regardless of the state of the do control data (doc0 to doc2). ul0, ul1 cte ioc1 ioc2 (7) unlock detection data ul0, ul1 selects the phase error ( e) detection width for checking pll lock. a phase error in excess of the specified detection width is seen as an unlocked state. note: in the unlocked state the do pin goes low and the ul bit in the serial data becomes zero. doc0 doc1 doc2 continued on next page. open the io1 pin state *2 the io2 pin state *2 open open low when the unlock state is detected end-uc *1 open do pin state doc0 doc1 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 1 1 1 1 0 0 0 0 doc2 (1) count start (3)ce: high (2) count end do pin open e is output directry e is extended by 1 to 2ms stopped 0 0.55 s 1.11 detector output e detection width ul0 0 1 0 1 0 0 1 1 ul1 LC72131K, 72131km no.a0788-11/22 continued from preceding page. no. control block/data functions related data (8) phase comparator control data dz0, dz1 ? controls the phase comparator dead zone. dead zone width: dza |