View PCA8576DU_8080048.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1. general description the pca8576d is a peripheral device which interfaces to almost any liquid crystal display (lcd) with low multiplex rates. it gene rates the drive signals for any static or multiplexed lcd containing up to four backplanes and up to 40 segments. it can be easily cascaded for larger lcd applications. the pca8576d is compatible with most microcontrollers and communicates via the two-line bidirectional i 2 c-bus. communication overheads are minimized by a display ram with auto-incremented addressing, by hardware subaddressing and by display me mory switching (static and duplex drive modes). 2. features and benefits ? aec-q100 compliant for automotive applications ? single chip lcd controller and driver ? selectable backplane drive configuration: static or 2, 3, 4 backplane multiplexing ? selectable display bias configuration: static, 1 2 or 1 3 ? internal lcd bias generation with voltage-follower buffers ? 40 segment drives: ? up to 20 7-segment numeric characters ? up to 10 14-segment alphanumeric characters ? any graphics of up to 160 elements ? 40 ? 4-bit ram for display data storage ? auto-incremented display data loading across device subaddress boundaries ? display memory bank switching in static and duplex drive modes ? versatile blinking modes ? independent supplies possible for lcd and logic voltages ? wide power supply range: from 1.8 v to 5.5 v ? wide logic lcd supply range: ? from 2.5 v for low-threshold lcds ? up to 6.5 v for high-threshold twisted nematic lcds ? low power consumption ? 400 khz i 2 c-bus interface ? may be cascaded for large lcd applications (up to 2560 elements possible) ? no external components required ? compatible with chip-on-gla ss and chip-on-board technology ? manufactured in silicon gate cmos process pca8576d automotive 40 x 4 lcd segment dr iver for low multiplex rates up to 1:4 rev. 2 ? 6 june 2013 product data sheet
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 2 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates 3. ordering information 3.1 ordering options 4. marking 5. block diagram table 1. ordering information type number package name description version PCA8576DU bare die 59 bumps PCA8576DU/2da table 2. ordering options product type number sales item (12nc) orderable part number ic revision delivery form PCA8576DU/2da/q2 935294883026 PCA8576DU/2da/q2,0 1 chips with bumps in tray table 3. marking codes product type number marking code PCA8576DU/2da/q2 pc8576d-2 fig 1. block diagram of pca8576d 40 013aaa467 lcd bias generator lcd voltage selector pca8576d backplane outputs display controller command decoder write data control display ram 40 4-bit output bank select and blink control display register display segment outputs data pointer and auto increment subaddress counter clock select and timing oscillator input filters blinker timebase power-on reset i 2 c-bus controller bp0 bp2 bp1 bp3 a2 a1 a0 sa0 sda scl v dd osc sync clk v ss v lcd s0 to s39
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 3 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates 6. pinning information 6.1 pinning viewed from active side. c1 and c2 are a lignment marks. for mechanical details, see figure 23 . fig 2. pinning diagram for PCA8576DU (bare die) s25 s26 s27 s28 s29 s30 s31 s32 s33 c2 s4 s6 s5 s7 s9 s10 s8 s11 s12 s13 s15 s14 s16 s17 osc a0 sync scl clk sda sda sda scl s39 s38 s36 s37 s35 s34 a2 a1 c1 sa0 v ss bp2 bp0 v lcd bp1 bp3 s0 s2 s1 s3 PCA8576DU v dd 013aaa468 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 52 53 54 55 56 57 58 59 1 2 3 4 5 6 7 8 43 44 45 46 47 48 49 s18 s19 s20 s21 s22 s23 s24 36 37 38 39 40 41 42 50 51
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 4 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates 6.2 pin description [1] the substrate (rear side of the die) is connected to v ss and should be electrically isolated. table 4. pin description symbol pin description PCA8576DU sda 1, 58, 59 i 2 c-bus serial data input and output scl 2, 3 i 2 c-bus serial clock input clk 5 external clock input or output v dd 6 supply voltage sync 4 cascade synchronization input or output osc 7 internal oscillator enable input a0 to a2 8 to 10 subaddress inputs sa0 11 i 2 c-bus address input; bit 0 v ss 12 [1] ground supply voltage v lcd 13 lcd supply voltage bp0, bp2, bp1, bp3 14 to 17 lcd backplane outputs s0 to s39 18 to 57 lcd segment outputs
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 5 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates 7. functional description the pca8576d is a versatile peripheral device designed to interface any microcontroller with a wide variety of lcds. it can directly dr ive any static or multiplexed lcd containing up to four backplanes and up to 40 segments. the possible display configurations of the pca8576d depend on the number of active backplane outputs required. a selection of display configurations is shown in ta b l e 5 . all of these configurations can be implem ented in the typical system shown in figure 3 . the host microprocessor or microcontroller maintains the 2-line i 2 c-bus communication channel with the pca8576d. the internal oscillator is enabled by connecting pin osc to pin v ss . the appropriate biasing voltages for the multiplexed lcd waveforms are generated internally. the only other connec tions required to complete the system are to the power supplies (v dd , v ss and v lcd ) and the lcd panel chosen for the application. table 5. selection of possi ble display configurations number of backplanes icons digits/characters dot matrix/ elements 7-segment 14-segment 4 160 20 10 160 (4 ? 40) 3 120 15 7 120 (3 ? 40) 28010580 (2 ? 40) 1405240 (1 ? 40) the resistance of the power lines must be kept to a minimum. for chip-on-glass applications, due to the indium tin oxide (ito) track resistance, each supply line must be routed separately between the chip and the connector. fig 3. typical system configuration host micro- processor/ micro- controller t r 2c b sda scl osc 40 segment drives 4 backplanes lcd panel (up to 160 elements) pca8576d a0 a1 a2 sa0 v dd v ss v ss v dd v lcd 013aaa469 r
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 6 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates 7.1 power-on reset at power-on the pca8576d resets to the following starting conditions: ? all backplane and segment outputs are set to v lcd ? the selected drive mode is: 1:4 multiplex with 1 3 bias ? blinking is switched off ? input and output bank selectors are reset ? the i 2 c-bus interface is initialized ? the data pointer and the subaddress counter are cleared (set to logic 0) ? the display is disabled (bit e = 0, see ta b l e 11 ) data transfers on the i 2 c-bus must be avoided for 1 ms following power-on to allow the reset action to complete. 7.2 lcd bias generator fractional lcd biasing voltages are obtained from an internal voltage divider consisting of three impedances connected in series between v lcd and v ss . the middle resistor can be bypassed to provide a 1 2 bias voltage level for the 1:2 multiplex configuration. the lcd voltage can be temperature compensated externally using the supply to pin v lcd . 7.3 lcd voltage selector the lcd voltage selector coordinates the mult iplexing of the lcd in accordance with the selected lcd drive configuration. the operation of the voltage selector is controlled by the mode-set command (see ta b l e 11 ) from the command decoder. the biasing configurations that apply to the preferred modes of opera tion, together with the biasing characteristics as functions of v lcd and the resulting discrimination ratios (d), are given in ta b l e 6 . a practical value for v lcd is determined by equating v off(rms) with a defined lcd threshold voltage (v th ), typically when the lcd exhibits approximately 10 % contrast. in the static drive mode a suitable choice is v lcd >3v th . multiplex drive modes of 1:3 and 1:4 with 1 2 bias are possible but the discrimination and hence the contrast ratios are smaller. bias is calculated by , where the values for a are a = 1 for 1 2 bias table 6. discrimination ratios lcd drive mode number of: lcd bias configuration backplanes levels static 1 2 static 0 1 ? 1:2 multiplex 2 3 1 2 0.354 0.791 2.236 1:2 multiplex 2 4 1 3 0.333 0.745 2.236 1:3 multiplex 3 4 1 3 0.333 0.638 1.915 1:4 multiplex 4 4 1 3 0.333 0.577 1.732 v off rms ?? v lcd ------------------------ - v on rms ?? v lcd ----------------------- - d v on rms ?? v off rms ?? ------------------------ - = 1 1a + ------------ -
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 7 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates a = 2 for 1 3 bias the rms on-state voltage (v on(rms) ) for the lcd is calculated with equation 1 (1) where the values for n are n = 1 for static mode n = 2 for 1:2 multiplex n = 3 for 1:3 multiplex n = 4 for 1:4 multiplex the rms off-state voltage (v off(rms) ) for the lcd is calculated with equation 2 : (2) discrimination is the ratio of v on(rms) to v off(rms) and is determined from equation 3 : (3) using equation 3 , the discrimination for an lcd drive mode of 1:3 multiplex with 1 2 bias is and the discrimination for an lc d drive mode of 1:4 multiplex with 1 2 bias is . the advantage of these lcd drive modes is a reduction of the lcd full scale voltage v lcd as follows: ? 1:3 multiplex ( 1 2 bias): ? 1:4 multiplex ( 1 2 bias): these compare with when 1 3 bias is used. it should be noted that v lcd is sometimes referred as the lcd operating voltage. 7.3.1 electro-optical performance suitable values for v on(rms) and v off(rms) are dependent on the lcd liquid used. the rms voltage, at which a pixel will be switched on or off, determine the transmissibility of the pixel. v on rms ?? a 2 2a n ++ n 1a + ?? ? ----------------------------- - v lcd = v off rms ?? a 2 2a ? n + n 1a + ?? ? ----------------------------- - v lcd = d v on rms ?? off rms ?? ---------------------- - a1 + ?? n 1 ? ?? + a1 ? ?? n 1 ? ?? + ------------------------------------------- - == 3 1.732 = 21 3 ---------- 1.528 = v lcd 6v off rms ?? ? off rms ?? == v lcd 43 ? ?? --------------------- - 2.309v off rms ?? == v lcd 3v off rms ?? =
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 8 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates for any given liquid, there are two threshold values defined. one point is at 10 % relative transmission (at v low ) and the other at 90 % relative transmission (at v high ), see figure 4 . for a good contrast performance, the following rules should be followed: (4) (5) v on(rms) and v off(rms) are properties of the display driver and are affected by the selection of a, n (see equation 1 to equation 3 ) and the v lcd voltage. v th(off) and v th(on) are properties of the lcd liquid and can be provided by the module manufacturer. v th(off) is sometimes just named v th . v th(on) is sometimes named saturation voltage v sat . it is important to match the module properties to those of the driver in order to achieve optimum performance. fig 4. electro-optical characteristic: relative transmission curve of the liquid v on rms ?? v high ? v off rms ?? v low ? v rms [v] 100 % 90 % 10 % off segment grey segment on segment v low v high relative transmission 001aam358
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 9 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates 7.4 lcd drive mode waveforms 7.4.1 static drive mode the static lcd drive mode is used when a single backplane is provided in the lcd. the backplane (bpn) and segment drive (sn) waveforms for this mode are shown in figure 5 . (1) v state1 (t) = v sn (t) ? v bp0 (t). (2) v on(rms) = v lcd . (3) v state2 (t) = v sn+1 (t) ? v bp0 (t). (4) v off(rms) = 0 v. fig 5. static driv e mode waveforms mgl745 v ss v lcd v ss v lcd v ss v lcd v lcd ?v lcd ?v lcd v lcd state 1 0 v bp0 sn sn+1 state 2 0 v (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 1 (on) state 2 (off) t fr
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 10 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates 7.4.2 1:2 multiplex drive mode the 1:2 multiplex drive mode is used when tw o backplanes are provided in the lcd. this mode allows fractional lcd bias voltages of 1 2 bias or 1 3 bias as shown in figure 6 and figure 7 . (1) v state1 (t) = v sn (t) ? v bp0 (t). (2) v on(rms) = 0.791v lcd . (3) v state2 (t) = v sn+1 (t) ? v bp1 (t). (4) v off(rms) = 0.354v lcd . fig 6. waveforms for the 1:2 multiplex drive mode with 1 2 bias mgl746 state 1 bp0 (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 2 state 1 v ss v lcd v lcd / 2 v ss v ss v lcd v lcd v ss v lcd v lcd v lcd 0 v 0 v v lcd / 2 v lcd / 2 v lcd / 2 ?v lcd ?v lcd ?v lcd / 2 ?v lcd / 2 s n sn+1 t fr
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 11 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates (1) v state1 (t) = v sn (t) ? v bp0 (t). (2) v on(rms) = 0.745v lcd . (3) v state2 (t) = v sn+1 (t) ? v bp1 (t). (4) v off(rms) = 0.333v lcd . fig 7. waveforms for the 1:2 multiplex drive mode with 1 3 bias mgl747 state 1 bp0 (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 state 2 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 0 v v lcd 2v lcd / 3 ?2v lcd / 3 v lcd / 3 ?v lcd / 3 ?v lcd ?v lcd 0 v v lcd 2v lcd / 3 ?2v lcd / 3 v lcd / 3 ?v lcd / 3 s n s n+1 t fr v ss v lcd 2v lcd / 3 v lcd / 3
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 12 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates 7.4.3 1:3 multiplex drive mode when three backplanes are provided in the lcd, the 1:3 multiplex drive mode applies (see figure 8 ). (1) v state1 (t) = v sn (t) ? v bp0 (t). (2) v on(rms) = 0.638v lcd . (3) v state2 (t) = v sn+1 (t) ? v bp1 (t). (4) v off(rms) = 0.333v lcd . fig 8. waveforms for the 1:3 multiplex drive mode with 1 3 bias mgl748 state 1 bp0 (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 state 2 (a) waveforms at driver. bp2 s n s n+1 s n+2 t fr v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 0 v v lcd 2v lcd / 3 ?2v lcd / 3 v lcd / 3 ?v lcd / 3 ?v lcd 0 v v lcd 2v lcd / 3 ?2v lcd / 3 v lcd / 3 ?v lcd / 3 ?v lcd v ss v lcd 2v lcd / 3 v lcd / 3
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 13 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates 7.4.4 1:4 multiplex drive mode when four backplanes are provided in the lcd, the 1:4 multiplex drive mode applies (see figure 9 ). (1) v state1 (t) = v sn (t) ? v bp0 (t). (2) v on(rms) = 0.577v lcd . (3) v state2 (t) = v sn+1 (t) ? v bp1 (t). (4) v off(rms) = 0.333v lcd . fig 9. waveforms for the 1:4 multiplex drive mode with 1 3 bias mgl749 state 1 bp0 (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 state 2 bp2 (a) waveforms at driver. bp3 sn sn+1 sn+2 sn+3 t fr v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 0 v v lcd 2v lcd / 3 ?2v lcd / 3 v lcd / 3 ?v lcd / 3 ?v lcd 0 v v lcd 2v lcd / 3 ?2v lcd / 3 v lcd / 3 ?v lcd / 3 ?v lcd v ss v lcd 2v lcd / 3 v lcd / 3
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 14 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates 7.5 oscillator 7.5.1 internal clock the internal logic of the pca8576d and its lcd drive signals are timed either by its internal oscillator or by an external clock. the internal osc illator is enabled by connecting pin osc to pin v ss . if the internal oscillator is used, the output from pin clk can be used as the clock signal for several pca8576d in the system that are connected in cascade. 7.5.2 external clock pin clk is enabled as an external clock input by connecting pin osc to v dd . the lcd frame signal frequency is determined by the clock frequency (f clk ). remark: a clock signal must always be supplied to the device; removing the clock may freeze the lcd in a dc state, which is not suitable for the liquid crystal. 7.6 timing the pca8576d timing controls the internal da ta flow of the device. this includes the transfer of display data from the display ram to the display segment outputs. in cascaded applications, the correct timing relationship between each pca8576d in the system is maintained by the synchronization signal at pin sync . the timing also generates the lcd frame signal whose frequency is derived from the clock frequency. the frame signal frequency is a fixed division of the clock frequency from either the internal or an external clock: . 7.7 display register the display register holds the display data while the corresponding multiplex signals are generated. there is a one-to-one relationship be tween the data in the display register, the lcd segment outputs, and one column of the display ram. 7.8 segment outputs the lcd drive section includes 40 segment outputs s0 to s39 which should be connected directly to the lcd. the segment output signals are generated in accordance with the multiplexed backplane signals and with data residing in the display register. when less than 40 segment outputs are required, the unused segment outputs should be left open-circuit. 7.9 backplane outputs the lcd drive section includes four backplane outputs bp0 to bp3 which must be connected directly to the lcd. the backplane output signals are generated in accordance with the selected lcd drive mode. if less than four backplane outputs are required, the unused outputs can be left open-circuit. in the 1:3 multiplex drive mode, bp3 carries the same signal as bp1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. f fr f clk 24 ------- =
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 15 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates in the 1:2 multiplex drive mode, bp0 and bp2, bp1 and bp3 all carry the same signals and may also be paired to in crease the drive capabilities. in the static drive mode the same signal is ca rried by all four backplane outputs and they can be connected in parallel for very high drive requirements. 7.10 display ram the display ram is a static 40 ? 4-bit ram which stores lcd data. a logic 1 in the ram bit-map indicates the on-state of the corresponding lcd element; similarly, a logic 0 indicates the off-state. there is a one -to-one correspondence between the ram addresses and the segment outputs, and between the individual bits of a ram word and the backplane outputs. the display ram bit map figure 10 shows the rows 0 to 3 which correspond with the backplane outputs bp0 to bp3, and the columns 0 to 39 which correspond with the segment outputs s0 to s39. in multiplexed lcd applications the segment data of the first, second, third and fourth row of the display ram are time-multiplexed with bp0, bp1 , bp2 and bp3 respectively. when display data is transmitted to the pca8 576d, the display bytes received are stored in the display ram in accordance with the se lected lcd drive mode. the data is stored as it arrives and does not wait for an ackno wledge cycle as with the commands. depending on the current multiplex drive mode, data is stored singularly, in pairs, triplets or quadruplets. to illustrate th e filling order, an example of a 7-segment numeric display showing all drive modes is given in figure 11 ; the ram filling organization depicted applies equally to other lcd types. display ram bit map showing direct relation ship between ram addresses and segment outputs; also between bits in a ram word and the backplane outputs. fig 10. display ram bit map 0 0 1 2 3 1 2 3 4 35 36 37 38 39 display ram addresses (columns)/segment outputs (s) display ram bits (rows)/ backplane outputs (bp) mbe525
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 16 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates x = data bit unchanged. fig 11. relationship between lcd layout, drive mode, display ram filling order and display data transmitted over the i 2 c-bus 001aaj646 acbdpf egd msb lsb bdpcadgfe msb lsb abfgecddp msb lsb cba f geddp msb lsb drive mode static 1:2 multiplex 1:3 multiplex 1:4 multiplex lcd segments lcd backplanes display ram filling order transmitted display byte bp0 bp0 bp1 bp0 bp1 bp2 bp1 bp2 bp3 bp0 n c x x x 0 1 2 3 b x x x a x x x f x x x g x x x e x x x d x x x dp x x x n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 rows display ram rows/backplane outputs (bp) byte1 columns display ram address/segment outputs (s) n a b x x 0 1 2 3 f g x x e c x x d dp x x n + 1 n + 2 n + 3 byte1 byte2 rows display ram rows/backplane outputs (bp) columns display ram address/segment outputs (s) n b dp c x 0 1 2 3 a d g x f e x x n + 1 n + 2 byte1 byte2 byte3 rows display ram rows/backplane outputs (bp) columns display ram address/segment outputs (s) n + 1 n a c b dp 0 1 2 3 f e g d byte1 byte2 byte3 byte4 byte5 rows display ram rows/backplane outputs (bp) columns display ram address/segment outputs (s) s n+2 s n+3 s n+1 s n dp a f b g e c d s n+2 s n+1 s n+7 s n s n+3 s n+5 s n+6 s n+4 dp a f b g e c d s n s n+1 s n+2 dp a f b g e c d s n+1 s n dp a f b g e c d
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 17 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates the following applies to figure 11 : ? in static drive mode the eight transmitted data bits are placed in row 0 as one byte. ? in 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into row 0 and 1 as two successive 4-bit ram words. ? in 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as three successive 3-bit ram words, with bit 3 of the third address left unchanged. it is not recommended to use this bit in a displa y because of the difficult addressing. this last bit may, if necessary, be controlled by an additional transfer to this address but care should be taken to avoid overwriting adjacent data because always full bytes are transmitted. ? in 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples into row 0, 1, 2, and 3 as two successive 4-bit ram words. 7.11 data pointer the addressing mechanism for the display ram is realized using the data pointer. this allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display ram. the se quence commences with the initialization of the data pointer by the load-data-pointer command (see section 7.17 ). following this command, an arriving data byte is stored at the display ram address indicated by the data pointer. the filling orde r is shown in figure 11 . after each byte is stored, the content of the da ta pointer is automatically incremented by a value dependent on the selected lcd drive mode: after each byte is stored, the contents of the data pointer is automatically incremented by a value dependent on the selected lcd drive mode: ? in static drive mode by eight ? in 1:2 multiplex drive mode by four ? in 1:3 multiplex drive mode by three ? in 1:4 multiplex drive mode by two if an i 2 c-bus data access is terminated early then the state of the data pointer is unknown. the data pointer should be re-written prior to further ram accesses. 7.12 subaddress counter the storage of display data is determined by the contents of the subaddress counter. storage is allowed to take place only when the contents of the subaddress counter match with the hardware subaddress applied to a0, a1 and a2. the subaddress counter value is defined by the device-select command (see section 7.17 ). if the contents of the subaddress counter and the hardware subaddress do not match then data storage is inhibited but the data pointer is incremente d as if data storage had taken place. the subaddress counter is also incremented when the data pointer overflows. the storage arrangements described lead to ex tremely efficient data loading in cascaded applications. when a series of display byte s are sent to the display ram, automatic wrap-over to the next pca 8576d occurs when the last ram address is exceeded.
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 18 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a tr ansmitted character (such as during the 14 th display data byte transmit ted in 1:3 multiplex mode). the hardware subaddress must not be changed while the device is being accessed on the i 2 c-bus interface. 7.13 output bank selector the output bank selector (see ta b l e 1 4 ) selects one of the four rows per display ram address for transfer to the display register. the actual row selected depends on the particular lcd drive mode in operation and on the instant in the multiplex sequence. ? in 1:4 multiplex mode, all ram addresses of row 0 are selected, these are followed by the contents of row 1, 2, and then 3 ? in 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially ? in 1:2 multiplex mode, rows 0 and 1 are selected ? in static mode, row 0 is selected the sync signal resets these sequences to the following starting points: row 3 for 1:4 multiplex, row 2 for 1:3 mult iplex, row 1 for 1: 2 multiplex and row 0 for static mode. the pca8576d includes a ram bank switching feature in the static and 1:2 multiplex drive modes. in the static drive mode, the bank-select command may request the contents of row 2 to be selected for display instead of the contents of row 0 . in the 1:2 mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. this gives the provision for preparing display information in an alternative bank and to be able to switch to it, once it is assembled. 7.14 input bank selector the input bank selector loads display data into the display ram in accordance with the selected lcd drive configuration. display data can be loaded in row 2 in static drive mode or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command. the input bank selector functions independe ntly to the output bank selector. 7.15 blinking the pca8576d has a very versatile display b linking capability. the whole display can blink at a frequency selected by the blink-select command (see ta b l e 1 5 ). each blink frequency is a fraction of the clock frequen cy; the ratio between the clock frequency and blink frequency depends on the blink mode selected (see ta b l e 7 ). an additional feature allows an arbitrary sele ction of lcd segments to blink in the static and 1:2 drive modes. this is implemented without any communication overheads by the output bank selector which alternates the displayed data between the data in the display ram bank and the data in an alternative ram bank at the blink frequency. this mode can also be implemented by the blink-select command (see ta b l e 1 5 ). in the 1:3 and 1:4 drive modes, where no al ternative ram bank is available, groups of lcd segments can blink selectively by changing the display ram data at fixed time intervals.
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 19 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates the entire display can blink at a frequency other than the nominal blink frequency by sequentially resetting and setting the display enable bit e at the required rate using the mode-set command (see ta b l e 11 ). [1] blink modes 1, 2 and 3 and the nominal blink frequencies 0.5 hz, 1 hz and 2 hz correspond to an oscillator frequency (f clk ) of 1536 hz (see section 11 ). 7.16 characteristics of the i 2 c-bus the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 7.16.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see figure 12 ). table 7. blinking frequencies [1] blink mode normal operating mode ratio nominal blink frequency off - blinking off 12 hz 21 hz 3 0.5 hz f clk 768 --------- - f clk 1536 ------------ - f clk 3072 ------------ - fig 12. bit transfer mba607 data line stable; data valid change of data allowed sda scl
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 20 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates 7.16.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line while the clock is high is defined as the start condition - s. a low-to-high transition of the data line while the clock is high is defined as the stop condition - p (see figure 13 ). 7.16.3 system configuration a device generating a message is a transmitter, a device receiving a message is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves (see figure 14 ). 7.16.4 acknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlim ited. each byte of eight bits is followed by an acknowledge cycle. ? a slave receiver which is addressed must generate an acknowledge after the reception of each byte. ? also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. ? the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is st able low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). fig 13. definition of start and stop conditions mbc622 sda scl p stop condition sda scl s start condition fig 14. system configuration mga807 sda scl master transmitter/ receiver master transmitter slave transmitter/ receiver slave receiver master transmitter/ receiver
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 21 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates ? a master receiver must signal an end of da ta to the transmitter by not generating an acknowledge on the last byte that has been cl ocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition. acknowledgement on the i 2 c-bus is shown in figure 15 . 7.16.5 i 2 c-bus controller the pca8576d acts as an i 2 c-bus slave receiver. it does not initiate i 2 c-bus transfers or transmit data to an i 2 c-bus master receiver. the only data output from the pca8576d are the acknowledge signals of the selected devices. device selection depends on the i 2 c-bus slave address, on the transferre d command data and on the hardware subaddress. in single device applications, the hardware subaddress inputs a0, a1 and a2 are normally tied to v ss which defines the hardware subaddress 0. in multiple device applications a0, a1 and a2 are tied to v ss or v dd in accordance with a binary coding scheme such that no two devices with a common i 2 c-bus slave address have the same hardware subaddress. 7.16.6 input filters to enhance noise immunity in electrically ad verse environments, rc low-pass filters are provided on the sda and scl lines. 7.16.7 i 2 c-bus protocol two i 2 c-bus slave addresses (0111 000 and 0111 001) are reserved for the pca8576d. the pca8576d slave addr ess is illustrated in ta b l e 8 . fig 15. acknowledgement of the i 2 c-bus mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master table 8. i 2 c slave address byte slave address bit 7 6 5 4 3 2 1 0 msb lsb 011100sa0r/w
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 22 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates the least significant bit of the slave addre ss that a pca8576d will respond to is defined by the level tied to its sa0 input. the pc a8576d is a write-only device and will not respond to a read access. having two reserved slave addresses allows the following on the same i 2 c-bus: ? up to 16 pca8576d for very large lcd applications ? the use of two types of lcd multiplex drive modes. the i 2 c-bus protocol is shown in figure 16 . the sequence is initiated with a start condition (s) from the i 2 c-bus master which is followed by one of two possible pca8576d slave addresses available. all pca8576d whos e sa0 inputs correspond to bit 0 of the slave address respond by asserting an acknowledge in parallel. this i 2 c-bus transfer is ignored by all pca8576d whose sa0 inputs are set to the alternative level. after an acknowledgement, one or more command bytes follow, that define the status of each addressed pca8576d. the last command byte sent is identified by resetting its most signif icant bit, continuation bit c, (see figure 17 ). the command bytes are also acknowledged by all addressed pca8576d on the bus. after the last command byte, one or more display data bytes may follow. display data bytes are stored in the display ram at the address specified by the data pointer and the subaddress counter. both data pointer and subaddress counter are automatically updated and the data directed to the intended pca8576d device. an acknowledgement after each byte is asserted only by the pca8576d that are addressed via address lines a0, a1 and a2. after the last display byte, the i 2 c-bus master asserts a stop condition (p). alternately a start may be asserted to restart an i 2 c-bus access. fig 16. i 2 c-bus protocol fig 17. format of command byte 013aaa470 s a 0 s 011100 0ac command a p a display data slave address r/w acknowledge by all addressed pca8576d acknowledge by a0, a1 and a2 selected pca8576d only 1 byte update data pointers and if necessary, subaddress counter n 1 byte(s) n 0 byte(s) msa833 rest of opcode c msb lsb
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 23 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates 7.17 command decoder the command decoder identifies command bytes that arrive on the i 2 c-bus. the commands available to the pca8576d are defined in ta b l e 9 . [1] not used. all available commands carry a continuation bit c in their most significant bit position as shown in figure 17 . when this bit is set, it indicates that the next byte of the transfer to arrive will also represent a command. if this bit is reset, it indicates that the command byte is the last in the transfe r. further bytes will be re garded as display data (see ta b l e 1 0 ). [1] the possibility to disable the display allows implementation of blinking under external control. [2] default value. [3] the display is disabled by setting all backplane and segment outputs to v lcd . table 9. definition of pca8576d commands command operation code reference bit 7 6 5 4 3 2 1 0 mode-set c 1 0 [1] e b m[1:0] ta b l e 11 load-data-pointer c 0 p[5:0] ta b l e 1 2 device-select c1100a[2:0] ta b l e 1 3 bank-select c 1 1 1 1 0 i o ta b l e 1 4 blink-select c 1 1 1 0 ab bf[1:0] ta b l e 1 5 table 10. c bit description bit symbol value description 7c continue bit 0 last control byte in the transfer; next byte will be regarded as display data 1 control bytes continue; next byte will be a command too table 11. mode-set command bit description bit symbol value description 7c0, 1see ta b l e 1 0 6 to 5 - 10 fixed value 4 - - unused 3e display status [1] 0 [2] disabled (blank) [3] 1 enabled 2b lcd bias configuration [4] 0 [2] 1 3 bias 1 1 2 bias 1 to 0 m[1:0] lcd drive mode selection 01 static; bp0 10 1:2 multiplex; bp0, bp1 11 1:3 multiplex; bp0, bp1, bp2 00 [2] 1:4 multiplex; bp0, bp1, bp2, bp3
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 24 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates [4] not applicable for static drive mode. [1] default value. [1] default value. [1] the bank-select command has no effect in 1:3 and 1:4 multiplex drive modes. [2] default value. table 12. load-data-pointer command bit description bit symbol value description 7c0, 1see ta b l e 1 0 6 - 0 fixed value 5 to 0 p[5:0] 000000 [1] to 100111 6 bit binary value, 0 to 39; transferred to the data pointer to define one of forty display ram addresses table 13. device-select command bit description bit symbol value description 7c0, 1see ta b l e 1 0 6 to 3 - 1100 fixed value 2 to 0 a[2:0] 000 [1] to 111 3 bit binary value, 0 to 7; transferred to the subaddress counter to define one of eight hardware subaddresses table 14. bank-select command bit description bit symbol value description static 1:2 multiplex [1] 7 c 0, 1 see table 10 6 to 2 - 11110 fixed value 1i input bank selection ; storage of arriving display data 0 [2] ram bit 0 ram bits 0 and 1 1 ram bit 2 ram bits 2 and 3 0o output bank selection ; retrieval of lcd display data 0 [2] ram bit 0 ram bits 0 and 1 1 ram bit 2 ram bits 2 and 3
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 25 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates [1] default value. [2] normal blinking is assumed when the lcd multiplex drive modes 1:3 or 1:4 are selected. [3] alternate ram bank blinking does not apply in 1:3 and 1:4 multiplex drive modes. 7.18 display controller the display controller executes the commands identified by the command decoder. it contains the device?s status registers and co ordinates their effects. the display controller is also responsible for loadi ng display data into t he display ram in the correct filling order. table 15. blink-select command bit description bit symbol value description 7c0, 1see ta b l e 1 0 6 to 3 - 1110 fixed value 2ab blink mode selection 0 [1] normal blinking [2] 1 alternate ram bank blinking [3] 1 to 0 bf[1:0] blink frequency selection 00 [1] off 01 1 10 2 11 3
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 26 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates 8. internal circuitry fig 18. device protection circuits sa0 v dd v dd v ss v ss v lcd v ss sda mdb076 v ss scl v ss clk v dd v ss osc v dd v ss sync v dd v ss a0, a1 a2 v dd v ss bp0, bp1, bp2, bp3 v lcd v ss s0 to s39 v lcd v ss
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 27 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates 9. limiting values [1] pass level; human body model (hbm) according to ref. 6 ? jesd22-a114 ? . [2] pass level; machine model (mm), according to ref. 7 ? jesd22-a115 ? . [3] pass level; latch-up testing according to ref. 8 ? jesd78 ? at maximum ambient temperature (t amb(max) ). [4] according to the store and transport requirements (see ref. 11 ? um10569 ? ) the devices have to be stored at a temperature of +8 ? c to +45 ? c and a humidity of 25 % to 75 %. caution static voltages across the liquid crystal display can build up when the lcd supply voltage (v lcd ) is on while the ic supply voltage (v dd ) is off, or vice versa. this may cause unwanted display artifacts. to av oid such artifacts, v lcd and v dd must be applied or removed together. table 16. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.5 +6.5 v v lcd lcd supply voltage ? 0.5 +7.5 v v i input voltage on each of the pins clk, sda, scl, sync , sa0, osc, a0 to a2 ? 0.5 +6.5 v v o output voltage on each of the pins s0 to s39, bp0 to bp3 ? 0.5 +7.5 v i i input current ? 10 +10 ma i o output current ? 10 +10 ma i dd supply current ? 50 +50 ma i dd(lcd) lcd supply current ? 50 +50 ma i ss ground supply current ? 50 +50 ma p tot total power dissipation - 400 mw p o output power - 100 mw v esd electrostatic discharge voltage hbm [1] - ? 5000 v mm [2] - ? 200 v i lu latch-up current [3] - 100 ma t stg storage temperature [4] ? 65 +150 ? c t amb ambient temperature operating device ? 40 +85 ? c
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 28 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates 10. static characteristics [1] v lcd > 3 v for 1 3 bias. [2] lcd outputs are open-circuit; inputs at v ss or v dd ; external clock with 50 % duty factor; i 2 c-bus inactive. [3] the i 2 c-bus interface of pca8576d is 5 v tolerant. [4] when tested, i 2 c pins scl and sda have no diode to v dd and may be driven to the v i limiting values given in table 16 . [5] propagation delay of driver between clock (clk) and lcd driving signals. [6] periodically sampled, not 100 % tested. [7] outputs measured one at a time. table 17. static characteristics v dd = 1.8 v to 5.5 v; v ss = 0 v; v lcd = 2.5 v to 6.5 v; t amb = ? 40 ? c to +85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit supplies v dd supply voltage 1.8 - 5.5 v v lcd lcd supply voltage [1] 2.5 - 6.5 v i dd supply current f clk(ext) = 1536 hz [2] -3.57 ? a v dd =3.0v; t amb =25 ?c -2.7- ? a i dd(lcd) lcd supply current f clk(ext) = 1536 hz [2] -1825 ? a v lcd =3.0v; t amb =25 ?c -13- ? a logic [3] v p(por) power-on reset supply voltage 1.0 1.3 1.6 v v il low-level input voltage on pins clk, sync , osc, a0 to a2, sa0, scl, sda v ss -0.3v dd v v ih high-level input voltage on pins clk, sync , osc, a0 to a2, sa0, scl, sda [4] [5] 0.7v dd -v dd v i ol low-level output current output sink current; v ol = 0.4 v; v dd =5v on pins clk and sync 1- - ma on pin sda 3 - - ma i oh(clk) high-level output current on pi n clk output source current; v oh =4.6v; v dd =5v 1- - ma i l leakage current v i =v dd or v ss ; on pins clk, scl, sda, a0 to a2 and sa0 ? 1- +1 ? a i l(osc) leakage current on pin osc v i =v dd ? 1- +1 ? a c i input capacitance [6] --7pf lcd outputs ? v o output voltage variation on pins bp0 to bp3 and s0 to s39 ? 100 - +100 mv r o output resistance v lcd = 5 v [7] on pins bp0 to bp3 - 1.5 - k ? on pins s0 to s39 - 6.0 - k ?
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 29 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates 11. dynamic characteristics [1] typical output duty factor: 50 % measured at the clk output pin. [2] not tested in production. [3] all timing values are valid within the operating supply voltage and ambient temperature range and are referenced to v il and v ih with an input voltage swing of v ss to v dd . table 18. dynamic characteristics v dd = 1.8 v to 5.5 v; v ss = 0 v; v lcd = 2.5 v to 6.5 v; t amb = ? 40 ? c to +85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit clock f clk(int) internal clock frequency [1] 1440 1850 2640 hz f clk(ext) external clock frequency 960 - 2640 hz t clk(h) high-level clock time 60 - - ? s t clk(l) low-level clock time 60 - - ? s synchronization t pd(sync_n) sync propagation delay - 30 - ns t sync_nl sync low time 1 - - ? s t pd(drv) driver propagation delay v lcd = 5 v [2] --3 0 ? s i 2 c-bus [3] pin scl f scl scl clock frequency - - 400 khz t low low period of the scl clock 1.3 - - ? s t high high period of the scl clock 0.6 - - ? s pin sda t su;dat data set-up time 100 - - ns t hd;dat data hold time 0 - - ns pins scl and sda t buf bus free time between a stop and start condition 1.3 - - ? s t su;sto set-up time for stop condition 0.6 - - ? s t hd;sta hold time (repeated) start condition 0.6 - - ? s t su;sta set-up time for a repeated start condition 0.6 - - ? s t r rise time of both sda and scl signals f scl = 400 khz - - 0.3 ? s f scl < 125 khz - - 1.0 ? s t f fall time of both sda and scl signals - - 0.3 ? s c b capacitive load for each bus line - - 400 pf t w(spike) spike pulse width on the i 2 c - b u s--5 0n s
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 30 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates fig 19. driver timing waveforms fig 20. i 2 c-bus timing waveforms 001aai163 t pd(drv) t sync_nl t pd(sync_n) clk sync bp0 to bp3, and s0 to s39 t clk(h) t clk(l) 1 / f clk 0.7 v dd 0.3 v dd 0.7 v dd 0.3 v dd 0.5 v (v dd = 5 v) 0.5 v sda mga728 sda scl t su;sta t su;sto t hd;sta t buf t low t hd;dat t high t r t f t su;dat
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 31 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates 12. application information 12.1 cascaded operation in large display configurations, up to 16 pca8576d can be differentiated on the same i 2 c-bus by using the 3-bit hardware subaddresses (a0, a1 and a2) and the programmable i 2 c-bus slave address (sa0). the pca8576d connected in cascade are synchronized to allow the backplane signals from only one device in the cascade to be shared. this arrangement is cost-effective in large lcd applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. the other cascaded pca8576d contribute additional segment outputs but their backplane outputs are left open-circuit (see figure 21 ). all pca8576d connected in cascade are correctly synchronized by the sync signal. this synchronization is guaranteed after the power-on reset. the only time that sync is likely to be needed is if synchroniza tion is lost accidentally, for example, by noise in adverse electrical environments, or if the lcd multip lex drive mode is changed in an application using several cascaded pca8576d, as the drive mode cannot be changed on all of the cascaded devices simultaneously. sync can be either an input or an output signal; a sync output is implemented as an open-drain driver with an internal pull-up resistor. the pca8576d asserts sync at the start of its last active backplane signal and monitors the sync line at all other times. if cascade synchroniza tion is lost, it is restored by the first pca8576d to assert sync . the timing relationship between the backplane waveforms and the sync signal for each lcd drive mode is shown in figure 22 . table 19. addressing cascaded pca8576d cluster bit sa0 pin a2 pin a1 pin a0 device 100000 0011 0102 0113 1004 1015 1106 1117 210008 0019 01010 01111 10012 10113 11014 11115
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 32 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates the contact resistance between the sync on each cascaded devi ce must be controlled. if the resistance is too high, the device is no t able to synchronize properly; this is particularly applicable to chip-on-glass applications. the maximum sync contact resistance allowed for the number of devices in cascade is given in ta b l e 2 0 . the pca8576d can be cascaded with the pca8 534a. this allows optimal drive selection for a given number of pixels to display. figure 19 and figure 20 show the timing of the synchronization signals. table 20. sync contact resistance number of devices maximum contact resistance 26 k ? 3 to 5 2.2 k ? 6 to 10 1.2 k ? 10 to 16 700 ? fig 21. cascaded pca8576d configuration host micro- processor/ micro- controller sda scl clk osc sync 40 segment drives 4 backplanes 40 segment drives lcd panel (up to 2560 elements) pca8576d a0 a1 a2 sa0 v dd v lcd v dd v lcd 013aaa471 sda scl sync clk osc bp0 to bp3 (open-circuit) a0 a1 a2 sa0 v ss v ss v ss v dd v lcd pca8576d bp0 to bp3 r t r 2c b
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 33 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates 12.2 ram writing in 1:3 multiplex drive mode in 1:3 multiplex drive mode, t he ram is written as shown in ta b l e 2 1 (see figure 11 as well). if the bit at position bp2/s2 would be writ ten by a second byte tr ansmitted, then the mapping of the segment bits would cha nge as illustrated in ta b l e 2 2 . fig 22. synchronization of the cascade for the various pca8576d drive modes t fr = f fr 1 bp0 sync bp0 (1/2 bias) sync bp0 (1/3 bias) (a) static drive mode. (b) 1:2 multiplex drive mode. (c) 1:3 multiplex drive mode. (d) 1:4 multiplex drive mode. bp0 (1/3 bias) sync sync bp0 (1/3 bias) mgl755 table 21. standard ram filling in 1:3 multiplex drive mode assumption: bp2/s2, bp2/s5, bp2/s8 etc. are no t connected to any elements on the display. display ram bits (rows)/ backplane outputs (bpn) display ram addresses (columns)/segment outputs (sn) 0 1 2 3 4 5 6 7 8 9 : 0 a7 a4 a1 b7 b4 b1 c7 c4 c1 d7 : 1 a6 a3 a0 b6 b3 b0 c6 c3 c0 d6 : 2 a5 a2 - b5 b2 - c5 c2 - d5 : 3 ----------:
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 34 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates in the case described in ta b l e 2 2 the ram has to be written entirely and bp2/s2, bp2/s5, bp2/s8 etc. have to be connected to elements on the display. this can be achieved by a combination of writing and re writing the ram like follows: ? in the first write to the ram, bits a7 to a0 are written. ? in the second write, bits b7 to b0 are writt en, overwriting bits a1 and a0 with bits b7 and b6. ? in the third write, bits c7 to c0 are writte n, overwriting bits b1 and b0 with bits c7 and c6. depending on the method of writing to t he ram (standard or co ntinuous filling by rewriting), some elements remain unused or c an be used, but it has to be considered in the module layout process as well as in the driver software design. 13. test information 13.1 quality information this product has been qualified in accordance with the automotive electronics council (aec) standard q100 - failure mechanism based stress test qualification for integrated circuits , and is suitable for use in automotive applications. table 22. continuos ram filling by rewriting in 1:3 multiplex drive mode assumption: bp2/s2, bp2/s5, bp2/s8 etc. ar e connected to elements on the display. display ram bits (rows)/ backplane outputs (bpn) display ram addresses (columns)/segment outputs (sn) 0 1 2 3 4 5 6 7 8 9 : 0 a7 a4 a1/b7 b4 b1/c7 c4 c1/d7 d4 d1/e7 e4 : 1 a6 a3 a0/b6 b3 b0/c6 c3 c0/d6 d3 d0/e6 e3 : 2 a5 a2 b5 b2 c5 c2 d5 d2 e5 e2 : 3 ----------:
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 35 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates 14. bare die outline fig 23. bare die outline PCA8576DU/2da/2 (for dimensions see table 23 ) references outline version european projection issue date iec jedec jeita PCA8576DU/2da PCA8576DU_2da_do 11-03-07 11-03-10 bare die; 59 bumps PCA8576DU/2da e x (1) 0 0 y x d e c2 59 1 52 8 c1 22 35 36 51 9 21 detail x b l notes 1. marking code: pc8576d-2 0 0.5 1 mm scale y detail y a 1 a 2 a
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 36 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates [1] dimension not drawn to scale. table 23. dimensions of PCA8576DU original dimensions are in mm. unit (mm) a a 1 a 2 b d e e [1] l max-------- nom 0.40 0.015 0.381 0.052 2.2 2.0 - 0.077 min------0.072- table 24. bump location for PCA8576DU all x/y coordinates represent the position of the ce nter of each bump with respect to the center (x/y = 0) of the chip (see figure 2 and figure 23 ). symbol bump x ( ? m) y ( ? m) description sda 1 ? 34.38 ? 876.6 i 2 c-bus serial data input/output scl 2 109.53 ? 876.6 i 2 c-bus serial clock input scl 3 181.53 ? 876.6 sync 4 365.58 ? 876.6 cascade synchronization input/output clk 5 469.08 ? 876.6 external clock input/output v dd 6 577.08 ? 876.6 supply voltage osc 7 740.88 ? 876.6 internal oscillator enable input a0 8 835.83 ? 876.6 subaddress inputs a1 9 1005.48 ? 630.9 a2 10 1005.48 ? 513.9 sa0 11 1005.48 ? 396.9 i 2 c-bus address input; bit 0 v ss 12 1005.48 ? 221.4 ground supply voltage v lcd 13 1005.48 10.71 lcd supply voltage bp0 14 1005.48 156.51 lcd backplane outputs bp2 15 1005.48 232.74 bp1 16 1005.48 308.97 bp3 17 1005.48 385.2 s0 18 1005.48 493.2 lcd segment outputs s1 19 1005.48 565.2 s2 20 1005.48 637.2 s3 21 1005.48 709.2 s4 22 347.22 876.6 lcd segment outputs s5 23 263.97 876.6 s6 24 180.72 876.6 s7 25 97.47 876.6 s8 26 14.22 876.6 s9 27 ? 69.03 876.6 s10 28 ? 152.28 876.6 s11 29 ? 235.53 876.6 s12 30 ? 318.78 876.6
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 37 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates s13 31 ? 402.03 876.6 s14 32 ? 485.28 876.6 s15 33 ? 568.53 876.6 s16 34 ? 651.78 876.6 s17 35 ? 735.03 876.6 s18 36 ? 1005.5 625.59 s19 37 ? 1005.5 541.62 s20 38 ? 1005.5 458.19 s21 39 ? 1005.5 374.76 s22 40 ? 1005.5 291.33 s23 41 ? 1005.5 207.9 s24 42 ? 1005.5 124.47 s25 43 ? 1005.5 41.04 s26 44 ? 1005.5 ? 42.39 s27 45 ? 1005.5 ? 125.8 s28 46 ? 1005.5 ? 209.3 s29 47 ? 1005.5 ? 292.7 s30 48 ? 1005.5 ? 376.1 s31 49 ? 1005.5 ? 459.5 s32 50 ? 1005.5 ? 543 s33 51 ? 1005.5 ? 625.6 s34 52 ? 735.03 ? 876.6 s35 53 ? 663.03 ? 876.6 s36 54 ? 591.03 ? 876.6 s37 55 ? 519.03 ? 876.6 s38 56 ? 447.03 ? 876 .6 s39 5 7 ? 375.03 ? 876.6 lcd segment outputs sda 58 ? 196.38 ? 876.6 i 2 c-bus serial data input/output sda 59 ? 106.38 ? 876.6 table 25. alignment marks all x/y coordinates represent the position of the ce nter of each alignment mark with respect to the center (x/y = 0) of the chip (see figure 2 and figure 23 ). symbol x ( ? m) y ( ? m) c1 930.42 ? 870.3 c2 ? 829.98 ? 870.3 table 24. bump location for PCA8576DU ?continued all x/y coordinates represent the position of the ce nter of each bump with respect to the center (x/y = 0) of the chip (see figure 2 and figure 23 ). symbol bump x ( ? m) y ( ? m) description
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 38 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates 15. handling information all input and output pins are protected ag ainst electrostatic discharge (esd) under normal handling. when handling metal-oxide semiconductor (mos) devices ensure that all normal precautions are taken as described in jesd625-a , iec 61340-5 or equivalent standards. 16. packing information 16.1 tray information fig 24. tray details ghwdlo; ; \ [ 0 1 / - . + 6(&7,21$$ $ & $ 'lphqvlrqvlqpp ddd [ \ % ' ( ) () * $ &
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 39 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates 17. abbreviations table 26. description of tray details tray details are shown in figure 24 . tray details dimensions abcdefghj kl mnunit 3.6 3.6 2.36 2.11 50.8 45.72 39.6 5.6 5.6 39.6 3.96 2.18 2.49 mm number of pockets x direction y direction 12 12 fig 25. tray alignment ddd pdunlqjfrgh table 27. abbreviations acronym description cmos complementary metal-oxide semiconductor hbm human body model ito indium tin oxide lcd liquid crystal display lsb least significant bit mm machine model msb most significant bit pcb printed circuit board ram random access memory rms root mean square scl serial clock line sda serial data line
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 40 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates 18. references [1] an10170 ? design guidelines for cog modules with nxp monochrome lcd drivers [2] an10706 ? handling bare die [3] iec 60134 ? rating systems for electronic tu bes and valves and analogous semiconductor devices [4] iec 61340-5 ? protection of electronic devices from electrostatic phenomena [5] ipc/jedec j-std-020d ? moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices [6] jesd22-a114 ? electrostatic discharge (esd) sensitivity testing human body model (hbm) [7] jesd22-a115 ? electrostatic discharge (esd) se nsitivity testing machine model (mm) [8] jesd78 ? ic latch-up test [9] jesd625-a ? requirements for handling elec trostatic-discharge-sensitive (esds) devices [10] um10204 ? i 2 c-bus specification and user manual [11] um10569 ? store and transport requirements 19. revision history table 28. revision history document id release date data sheet status change notice supersedes pca8576d v.2 20130606 product data sheet - pca8576d v.1 modifications: ? added improved i dd and i dd(lcd) values ( ta b l e 1 7 ) ? improved description of bit e ? changed tray information ( section 16.1 ) pca8576d v.1 20110404 product data sheet - -
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 41 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates 20. legal information 20.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 20.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 20.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use in automotive applications ? this nxp semiconductors product has been qualified for use in automotive applications. unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 42 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any licens e under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. bare die ? all die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the nxp semiconductors storage and transportation conditions. if there are da ta sheet limits not guaranteed, these will be separately indicated in the data sheet. there are no post-packing tests performed on individual die or wafers. nxp semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. accordingly, nxp semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. it is the responsibility of the customer to test and qualify their application in which the die is used. all die sales are conditioned upon and subject to the customer entering into a written die sale agreement with nxp semiconductors through its legal department. 20.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 21. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 43 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates 22. tables table 1. ordering information . . . . . . . . . . . . . . . . . . . . .2 table 2. ordering options . . . . . . . . . . . . . . . . . . . . . . . . .2 table 3. marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 4. pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4 table 5. selection of possible display configurations . . . .5 table 6. discrimination ratios . . . . . . . . . . . . . . . . . . . . . .6 table 7. blinking frequencies [1] . . . . . . . . . . . . . . . . . . .19 table 8. i 2 c slave address byte . . . . . . . . . . . . . . . . . . .21 table 9. definition of pca8576d commands . . . . . . . .23 table 10. c bit description . . . . . . . . . . . . . . . . . . . . . . . .23 table 11. mode-set command bit description . . . . . . . . .23 table 12. load-data-pointer command bit description . . .24 table 13. device-select command bit description . . . . . .24 table 14. bank-select command bit description . . . . . . .24 table 15. blink-select command bit description . . . . . . .25 table 16. limiting values . . . . . . . . . . . . . . . . . . . . . . . . .27 table 17. static characteristics . . . . . . . . . . . . . . . . . . . .28 table 18. dynamic characteristics . . . . . . . . . . . . . . . . . .29 table 19. addressing cascaded pca8576d . . . . . . . . . .31 table 20. sync contact resistance . . . . . . . . . . . . . . . . .32 table 21. standard ram filling in 1:3 multiplex drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 22. continuos ram fi lling by rewriting in 1:3 multiplex drive mode. . . . . . . . . . . . . . . . . . . . .34 table 23. dimensions of PCA8576DU . . . . . . . . . . . . . . .36 table 24. bump location for PCA8576DU . . . . . . . . . . . .36 table 25. alignment marks . . . . . . . . . . . . . . . . . . . . . . . .37 table 26. description of tray details . . . . . . . . . . . . . . . . .39 table 27. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 28. revision history . . . . . . . . . . . . . . . . . . . . . . . .40
pca8576d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 june 2013 44 of 45 nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates 23. figures fig 1. block diagram of pca8576d . . . . . . . . . . . . . . . . .2 fig 2. pinning diagram for PCA8576DU (bare die) . . . . .3 fig 3. typical system configuration . . . . . . . . . . . . . . . . .5 fig 4. electro-optical characteristic: relative transmission curve of the liquid . . . . . . . . . . . . . . .8 fig 5. static drive mode waveforms . . . . . . . . . . . . . . . . .9 fig 6. waveforms for the 1:2 multiplex drive mode with 1 2 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 fig 7. waveforms for the 1:2 multiplex drive mode with 1 3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 fig 8. waveforms for the 1:3 multiplex drive mode with 1 3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 fig 9. waveforms for the 1:4 multiplex drive mode with 1 3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 fig 10. display ram bit map . . . . . . . . . . . . . . . . . . . . . .15 fig 11. relationship between lcd layout, drive mode, display ram filling order and display data transmitted over the i 2 c-bus . . . . . . . . . . . . . . . .16 fig 12. bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 fig 13. definition of start and stop conditions. . . . . .20 fig 14. system configuration . . . . . . . . . . . . . . . . . . . . . .20 fig 15. acknowledgement of the i 2 c-bus . . . . . . . . . . . .21 fig 16. i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . .22 fig 17. format of command byte . . . . . . . . . . . . . . . . . . .22 fig 18. device protection circuits . . . . . . . . . . . . . . . . . . .26 fig 19. driver timing waveforms . . . . . . . . . . . . . . . . . . .30 fig 20. i 2 c-bus timing waveforms . . . . . . . . . . . . . . . . . .30 fig 21. cascaded pca8576d configuration . . . . . . . . . .32 fig 22. synchronization of the cascade for the various pca8576d drive modes . . . . . . . . . . . . . . . . . . .33 fig 23. bare die outline PCA8576DU/2da/2 (for dimensions see ta b l e 2 3 ) . . . . . . . . . . . . . . . . . .35 fig 24. tray details . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 fig 25. tray alignment . . . . . . . . . . . . . . . . . . . . . . . . . . .39
nxp semiconductors pca8576d automotive 40 x 4 lcd segment driver for low multiplex rates ? nxp b.v. 2013. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 6 june 2013 document identifier: pca8576d please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 24. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 5 7.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.2 lcd bias generator . . . . . . . . . . . . . . . . . . . . . 6 7.3 lcd voltage selector . . . . . . . . . . . . . . . . . . . . 6 7.3.1 electro-optical performance . . . . . . . . . . . . . . . 7 7.4 lcd drive mode waveforms . . . . . . . . . . . . . . . 9 7.4.1 static drive mode . . . . . . . . . . . . . . . . . . . . . . . 9 7.4.2 1:2 multiplex drive mode. . . . . . . . . . . . . . . . . 10 7.4.3 1:3 multiplex drive mode. . . . . . . . . . . . . . . . . 12 7.4.4 1:4 multiplex drive mode. . . . . . . . . . . . . . . . . 13 7.5 oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.5.1 internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.5.2 external clock . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.6 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.7 display register . . . . . . . . . . . . . . . . . . . . . . . . 14 7.8 segment outputs. . . . . . . . . . . . . . . . . . . . . . . 14 7.9 backplane outputs . . . . . . . . . . . . . . . . . . . . . 14 7.10 display ram . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.11 data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.12 subaddress counter . . . . . . . . . . . . . . . . . . . . 17 7.13 output bank selector . . . . . . . . . . . . . . . . . . . 18 7.14 input bank selector . . . . . . . . . . . . . . . . . . . . . 18 7.15 blinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.16 characteristics of the i 2 c-bus. . . . . . . . . . . . . 19 7.16.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.16.2 start and stop conditions . . . . . . . . . . . . . 20 7.16.3 system configuration . . . . . . . . . . . . . . . . . . . 20 7.16.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.16.5 i 2 c-bus controller . . . . . . . . . . . . . . . . . . . . . . 21 7.16.6 input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.16.7 i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 21 7.17 command decoder . . . . . . . . . . . . . . . . . . . . . 23 7.18 display controller . . . . . . . . . . . . . . . . . . . . . . 25 8 internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 26 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 27 10 static characteristics. . . . . . . . . . . . . . . . . . . . 28 11 dynamic characteristics . . . . . . . . . . . . . . . . . 29 12 application information . . . . . . . . . . . . . . . . . 31 12.1 cascaded operation. . . . . . . . . . . . . . . . . . . . 31 12.2 ram writing in 1:3 multiplex drive mode . . . . 33 13 test information . . . . . . . . . . . . . . . . . . . . . . . 34 13.1 quality information . . . . . . . . . . . . . . . . . . . . . 34 14 bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 35 15 handling information . . . . . . . . . . . . . . . . . . . 38 16 packing information . . . . . . . . . . . . . . . . . . . . 38 16.1 tray information . . . . . . . . . . . . . . . . . . . . . . . 38 17 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 39 18 references. . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 19 revision history . . . . . . . . . . . . . . . . . . . . . . . 40 20 legal information . . . . . . . . . . . . . . . . . . . . . . 41 20.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 41 20.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 20.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 41 20.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 42 21 contact information . . . . . . . . . . . . . . . . . . . . 42 22 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 23 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 24 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

▲Up To Search▲

Price & Availability of PCA8576DU

	To Download PCA8576DU Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .