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| N79E825A/824a/823a/822a data sheet 8-bit microcontroller pub lica tio n relea s e da te: aug 5 , 20 10 - 1 - revision a02 table of contents- 1 general des cription ......................................................................................................... 4 2 features ....................................................................................................................... .......... 5 3 parts inform ation list ..................................................................................................... 6 3.1 lead f r ee (rohs) parts informati on li st ......................................................................... 6 4 pin config uration .............................................................................................................. . 7 5 pin descri ption ................................................................................................................ ..... 8 6 functiona l d escription.................................................................................................... 9 6.1 on-chip fl ash eprom .................................................................................................. 9 6.2 i/o ports ...................................................................................................................... .... 9 6.3 serial i/o ..................................................................................................................... .... 9 6.4 timers ......................................................................................................................... .... 9 6.5 interrupts ..................................................................................................................... .... 9 6.6 data po inters .................................................................................................................. 9 6.7 arc h itec ture ................................................................................................................... 10 6.7.1 alu ............................................................................................................................ .... 10 6.7.2 accumula tor ................................................................................................................... 10 6.7.3 b regi ster ..................................................................................................................... .. 10 6.7.4 program stat us word: .................................................................................................... 10 6.7.5 scratch-pa d ram ........................................................................................................... 10 6.7.6 stack po inter .................................................................................................................. 11 6.8 power m anagem ent ...................................................................................................... 11 7 memory orga nization...................................................................................................... 12 7.1 program memory (o n-c h ip flas h) ................................................................................. 12 7.2 data me mory ................................................................................................................ 12 7.3 regis ter map ................................................................................................................. 13 7.4 work ing re gis ters......................................................................................................... 15 7.5 bit addressabl e locations ............................................................................................. 15 7.6 stac k .......................................................................................................................... ... 15 8 special functi o n registers ......................................................................................... 16 9 instruction set ................................................................................................................ .. 47 9.1 ins truc tion timing.......................................................................................................... 56 10 power ma na gement .......................................................................................................... 59 10.1 idle mode ...................................................................................................................... 59 10.2 power down mode ....................................................................................................... 59 11 reset cond itions ............................................................................................................... 61 11.1 sourc e s of res e t ............................................................................................................ 61 11.1.1 ex ternal reset .............................................................................................................. 61 http://
N79E825A/824a/823a/822a data sheet - 2 - 11.1.2 po w e r-on rese t (por) ................................................................................................ 61 11.1.3 watchdog t i me r reset ................................................................................................. 61 11.2 res e t state ................................................................................................................... 61 12 interrupts ..................................................................................................................... ...... 66 12.1 interrupt sourc e s .......................................................................................................... 66 12.2 priority level struc ture ................................................................................................. 68 12.3 res p onse time ............................................................................................................. 69 12.4 interrupt inputs .............................................................................................................. 70 13 programmable time rs/counte r s ............................................................................... 72 13.1 timer/counter s 0 & 1 .................................................................................................... 72 13.1.1 t i me-base se lection .................................................................................................... 72 13.1.2 mode 0 ......................................................................................................................... 72 13.1.3 mode 1 ......................................................................................................................... 73 13.1.4 mode 2 ......................................................................................................................... 74 13.1.5 mode 3 ......................................................................................................................... 74 14 nvm memory ..................................................................................................................... .... 76 15 watchdog timer ................................................................................................................. 77 15.1 watchdog control .............................................................................................. 78 15.2 clock control of wat c hdog .................................................................................. 79 16 serial port (ua r t) ............................................................................................................. 80 16.1 mode 0 ........................................................................................................................ 80 16.2 mode 1 ........................................................................................................................ 81 16.3 mode 2 ........................................................................................................................ 83 16.4 mode 3 ........................................................................................................................ 84 16.5 framing error detec tion ............................................................................................... 85 16.6 multiproc e ssor communications ................................................................................... 85 17 time access pr octe ction .............................................................................................. 87 18 keyboard interrupt (kbi) ............................................................................................... 90 19 analog com parators ...................................................................................................... 91 20 i/o port configuration ................................................................................................... 92 20.1 quasi-bidi rectional ou tput config uration ..................................................................... 92 20.2 open drai n output configuration ................................................................................. 93 20.3 pus h -pull output configuration .................................................................................... 94 20.4 input only co nfiguration ............................................................................................... 94 21 oscillator ..................................................................................................................... ...... 95 21.1 on-chip rc osc illator op t i on ....................................................................................... 95 21.2 external clock input option .......................................................................................... 96 21.3 cpu clock rate s e lec t ................................................................................................. 96 22 power monitoring function ........................................................................................ 97 22.1 power on detec t........................................................................................................... 97 22.2 brownout detect ........................................................................................................... 97 23 pulse-width-modula t ed (pwm) ou tp uts ................................................................... 98 N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 3 - revision a02 24 analog-to-digita l converte r .................................................................................... 102 24.1 adc resoluti on and anal og supply: .......................................................................... 103 25 i2c serial control .......................................................................................................... 105 25.1 sio port ...................................................................................................................... 105 25.2 the i2c cont ro l regis ters : ......................................................................................... 106 25.2.1 t he address regi sters, i2addr ................................................................................ 106 25.2.2 t he data regi ster, i2da t .......................................................................................... 106 25.2.3 t he control regi ster, i2con ..................................................................................... 107 25.2.4 t he status regi ster, i2 st a tus ................................................................................. 107 25.2.5 t he i2c clock baud ra te bits , i2clk ........................................................................ 107 25.3 modes of operation .................................................................................................... 108 25.3.1 master t rans m i tter mode ........................................................................................... 108 25.3.2 master rece iver mode ............................................................................................... 108 25.3.3 slave receiv er mode ................................................................................................. 108 25.3.4 slave t r ansmi tter m ode ............................................................................................. 109 25.4 data trans f er flow in five oper ating modes ............................................................. 109 26 icp(in-ci r cuit progra m) flash program ................................................................ 115 27 config bits .................................................................................................................... ..... 116 27.1 config1 .................................................................................................................... 116 27.2 config2 .................................................................................................................... 117 28 electri c a l cha racteristics ....................................................................................... 119 28.1 abs o lute maxi mum ratings ........................................................................................ 119 28.2 dc ele c tri c al ch ara c teristics .................................................................... 120 28.3 the adc converter dc e lec trical cha ra cte r istics ................................... 122 28.4 the comparator electr i c al characte r istics ........................................ 122 28.5 ac electrical ch ara c teristics .................................................................... 122 28.6 external clock ch a r acte ristics ................................................................ 123 28.7 ac specific ation .................................................................................................. 123 28.8 internal rc osc spec ific at ion ................................................................................... 123 28.9 typical applicat ion cir cuits .......................................................................... 123 29 package dime nsio ns ....................................................................................................... 124 29.1 20-pin ssop ............................................................................................................... 124 29.2 20-pin sop ................................................................................................................. 125 29.3 20-pin dip ................................................................................................................... 126 30 revision hi stor y .............................................................................................................. 127 N79E825A/824a/823a/822a data sheet - 4 - 1 general descrip t ion the n79e 82 5 serie s are an 8-bit turb o 51 micro c o ntrolle r whi c h has an in-system prog ra mmabl e flash epro m whi c h fla s h eprom ca n program by icp (in circuit prog ram ) or by h a rd w a re wr iter . the in stru ctio n set of the n79e8 25 seri es a r e fully compatible wit h the stan da rd 8052. t he n79e8 25 seri es contai n a 16k/8k/4k/2k byte s o f main flash eprom; a 25 6 bytes of ram; 256 by tes nvm data fl ash e p rom; two 8 - bit bi-directio nal, one 2- bit bi-di r e c tional and bit-ad dressabl e i/o p o rts; two 16-bit time r/counters; 4 - ch annel m u ltipl e xed 10 -bit a/d conve r t; 4-chan nel 1 0 -bit pwm; two seri al ports th at incl ude a i2c a n d an enh an ced full duplex serial p ort. t hese peri phe rals a r e sup p orted by 13 source s fo ur-l evel interrupt ca pability. to facilitate prog ram m ing and verifi cati on, the fla s h eprom insid e the n79e825 serie s allow the prog ram me mory to be prog ram m ed and read electro nically. once the co d e is co nfirme d, the use r ca n prote c t the cod e for se cu rity. N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 5 - revision a02 2 feat ure s ? fully static de sign 8 - bit turbo 51 cm os microcontroll er up to 20m hz whe n v dd = 4 .5v to 5.5v, 12mhz when v dd = 2 .7v to 5.5v ? 16k/8k/4k/2k bytes of ap flash epro m, with icp and external writer prog ram mable mo de. ? 256 bytes of on-chip ram. ? 256 bytes nvm data fla s h eprom for cu stome r dat a stora ge u s e d and 10k wri t er cycl es; da ta flash p r o gra m/era s e v dd =3.0v to 5.5v ? ins t ruc t ion-set c o mpatible with mcs-51. ? built-in intern al rc o s cillat or (a bout 6m hz) ? two 8 - bit bi-d irectio nal an d one 2-bit bi -d irectio nal po rt s. ? two 16 -bit timer/counte r s. ? 13 interrupt s sou r ce with four levels of priority. ? one en han ce d full duplex serial po rt with framing erro r detection a n d automatic a ddre s s recognitio n . ? the 4 output s mode and t tl/schmitt trigger sele ctab le port. ? programma bl e watchdo g timer. ? four-chan nel 10-bit pwm (pulse width modulato r). ? four-chan nel multiplexed with 10-bits a / d conve r t. ? one i2c com m unication p o rt (ma s ter / slave). ? eight keypad interrupt input s. ? two an alog compa r ators. ? config ura b le on-chip o s cill ator. ? led drive capability (20m a) on all port pins. ? brownout voltage dete c t interrupt and re set. ? develo pment tools: - jt ag ice ( in circ uit emulation) tool - icp(in ci rcu i t programmi ng) writer ? p a ck age s: N79E825Adg ---- pdip20 N79E825Asg ---- sop20 N79E825Arg ---- ss op20 n79e824adg ---- pdip20 n79e824asg ---- sop20 n79e824arg ---- ss op20 n79e823adg ---- pdip20 n79e823asg ---- sop20 n79e823arg ---- ss op20 n79e822adg ---- pdip20 N79E825A/824a/823a/822a data sheet - 6 - n79e822asg ---- sop20 n79e822arg ---- ss op20 3 part s information list 3.1 lead free (rohs) parts information list part no. ep rom f l ash siz e ram nvm dat a flas h ep rom pac kag e rema rk n79e8 25a dg 16kb 256b 256b dip-20 pin n79e8 25as g 16kb 256b 256b sop-20 pin n79e8 25a rg 16kb 256b 256b ssop-20 pin n79e8 24a dg 8kb 256b 256b dip-20 pin n79e8 24as g 8kb 256b 256b sop-20 pin n79e8 24a rg 8kb 256b 256b ssop-20 pin n79e8 23a dg 4kb 256b 256b dip-20 pin n79e8 23as g 4kb 256b 256b sop-20 pin n79e8 23a rg 4kb 256b 256b ssop-20 pin n79e8 22a dg 2kb 256b 256b dip-20 pin n79e8 22as g 2kb 256b 256b sop-20 pin n79e8 22a rg 2kb 256b 256b ssop-20 pin table 3-1: lead free (rohs) parts information list N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 7 - revision a02 4 pin configuration 1 2 20 19 18 17 16 15 14 13 12 11 3 4 5 6 7 8 9 10 pwm3/cmp2/p0.0 pwm2/p1.7 pw m1 /p1.6 rst/p1.5 vss xtal1/p2.1 xtal2/cl ko ut/p2.0 int 1/p1.4 sda / i n t0/p1.3 scl/t0/p1.2 p0.1/c in2b/pwm0 p0.2/c in2a/brake p0.3/c in1b/ad0 p0.4/c in1a/ad1 p0.5/c mpref/ad2 vdd p0.6/c mp1/ad3 p0.7/t 1 p1.0/t xd p1.1/r xd 20 p i n di p 1 2 20 19 18 17 16 15 14 13 12 11 3 4 5 6 7 8 9 10 pwm3/cmp2/p0.0 pwm2/p1.7 pw m1 /p1.6 rst/p1.5 vss xtal1/p2.1 xtal2/cl ko ut/p2.0 int 1/p1.4 sda / i n t0/p1.3 scl/t0/p1.2 p0.1/c in2b/pwm0 p0.2/c in2a/brake p0.3/c in1b/ad0 p0.4/c in1a/ad1 p0.5/c mpref/ad2 vdd p0.6/c mp1/ad3 p0.7/t 1 p1.0/t xd p1.1/r xd 20 pin so p/ ssop figure 4-1: pin configuration N79E825A/824a/823a/822a data sheet - 8 - 5 pin des c ription symbol type descriptions st r (p1.5) i reset: a low on this pin for two machine cycles while the oscillator is running resets the device. xtal1(p2.1) i/o crystal1: this is the crystal oscilla tor input. this pin may be driven by an external clock or configurable i/o pin. xtal2(p2.0) i/o crystal2: this is the crystal osc illator output. it is the inversion of xtal1 or configurable i/o pin. vss p ground: ground potential vdd p power: supply: s upply voltage for operation. p0.0 ? p0.7 i/o port 0: port 0 is four mode output pin and two mode input. the p0.3~p0.6 are 4-channel input por ts (adc0-adc3) for adc used. p1.0 ? p1.7 i/o port 1: port 1 is four mode output pin and two mode input. the p1.2 (scl) and p1.3 (sda) is only open drain circuit, and p1.5 only input pin. * type: p: power, i: input, o: output, i/o: bi-directional, h: pull-high, l: pull-low, d: open-drain . table 5-1: pin description N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 9 - revision a02 6 functional de scription the n7 9e82 5 seri es a r chi t ecture con s i s t of a 4t 80 51 co re controller surrou nd ed by variou s registe r s, 16k/8k/4k/2k bytes flash eprom, 256 bytes of ram, 256 bytes nvm dat a flash eprom, three gene ral p u rp ose i/o po rts, two timer/co unters, one serial p o rt, on e i2c seri al i/o, 4 cha nnel pwm with 10-bit cou n te r, 4-cha nnel multiplexed with 10-bit a d c an alog i n p u t, flash ep rom pro g ra m by write r and icp. 6.1 on-chip flash epro m the n79e8 2 5 se rie s in clu de on e 16 k/8 k /4k/2 k byte s of mai n fla s h eprom f o r ap plication prog ram. a writer or icp prog ram m ing boa rd is req uire d to program the flash epro m or nvm data flash eprom. this icp (in-circuit prog ramming ) feature ma ke s t he job easy a nd efficient whe n the ap plicatio n?s firmwa re nee ds to be upd ated freque nt ly. in some appli c ation s , the in-ci r cuit prog ram m ing feature make s it possible for the en d-u s e r to easi l y update t he system firm ware with out o penin g the ch assis. 6.2 i/o ports the n79e 82 5 serie s hav e two 8-bit and one 2-bit port, up to 18 i/o pins using on-chip o scill ator & /rst is input only by rese t options. all ports ca n be use d as fou r outputs m o d e whe n it may set by pxm1.y and pxm2.y sfr?s regi ste r s, it has st rong pull-u ps a nd pull-d owns, a nd doe s not need any external pull - ups. othe rwi s e it can be use d as ge ne ral i/o port a s ope n drai n circuit. all ports can b e use d bi-di r ect i onal and the s e are a s i/o ports. thes e ports are not true i/o, but rathe r are pseudo -i/o ports. thi s is becau se the s e ports have stron g pull - do wn s and wea k pull-up s. 6.3 serial i/o the n79e82 5 se rie s hav e one seri al port that is fu ncti on ally sim ilar to the se rial port of the original 8032 fa mily. ho wever the seri al p o rt o n the n7 9e82 5 se rie s can o perate in diffe rent mo de s in ord er to obtain timing similarity as well. the serial por t ha s the enhan ced features of automatic addre ss recognitio n a nd fra m e error dete c tion. 6.4 timers the n7 9e82 5 seri es h ave two 16-bit timers that ar e functionally and simil a r to the timers of the 8052 family. when used a s timers, the u s er has a ch oice of 12 or 4 clo c ks pe r co unt that emulates the timing of the origin al 805 2. 6.5 interrupts the interrupt stru cture in t he n79e82 5 seri es i s slig h t ly different from that of the stan dard 8 052. due to the presen ce of additional feature s and peri phe rals, the number of interru pt source s and vectors has b een in creased. 6.6 data pointers the data poi nters of n7 9 e 825 se rie s are same as 8052 that has dual 16-bit data pointers (dptr) by setting dps b it at auxr1.0. the figure o f dual dptr i s as b e lo w di agra m . N79E825A/824a/823a/822a data sheet - 10 - dptr dptr1 dps auxr1.0 dps=0 dps=1 figure 6 - 1: dual dptr 6.7 archit ectu r e the n79e 82 5 serie s are based on the standard 80 52 devic e. it is built aroun d an 8-bit alu that uses internal regi sters fo r temp ora r y storage and cont rol of the peri p heral devices. it can execute the stand ard 8 05 2 instru ction set. 6.7.1 alu the alu i s th e hea rt of the n79e8 25 se ries. it is resp onsi ble for th e arithmeti c a nd logi cal fun c tion s. it is also u s ed in deci s io n makin g, in case of jum p instru ction s , a nd is al so u s ed in cal c ul a t ing jump addresse s. t he user can not dire ct ly use the alu, but the instru ction decod er re ad s the op-code, decode s it, a nd sequ en ce s the d ata th roug h the al u an d its a s so ciated regi sters to g ene rate the requi re d re su lt. the alu mainly u s es the acc whi c h is a spe c ial function re gi ster (sfr) o n the chip. another sfr, namely b r egiste r is also used in mu ltiply and divide instructio n s . the alu g enerate s several statu s sig nal s whi c h are sto r ed in the progra m status wo rd regi ster (ps w). 6.7.2 accumulato r the accumul ator (acc) is the primary registe r use d in arithmetic, logical and da ta transfer op eration s in the n7 9e8 25 serie s . since th e accu mulator i s di r ect ly ac ce s s i ble by t he cpu, most of the high spe ed in stru ctions ma ke u s e of the acc as o ne arg u ment. 6.7.3 b register this is a n 8-bit registe r th at is use d as the se con d a r gum ent in the mul an d div instructio n s . for all other in stru cti ons it ca n be use d simply a s a gen eral p urpo s e regi st er. 6.7.4 program st atus word: this is an 8-bit sfr that is used to store the status bit s of the alu. it holds the carry flag, the auxiliary carry flag, general pu rpo s e flags, the registe r ban k select, the o v erflow flag, and the parit y flag. 6.7.5 scratch-pad ram the n79e825 series have a 256 bytes on-chip scratch-pad ram. thes e can be used by the user for temporary storage during program execution. a certai n section of this ram is bit addressable, and can be directly addressed for this purpose. N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 11 - revision a02 6.7.6 stack pointer the n7 9e82 5 seri es hav e an 8-bit stack pointer whi c h point s to the top of the stack. this sta c k resi de s in the scratch pad ram in the n79e8 25 se ri es. hen c e the size of t he stack is limited by the s i ze of this ram. 6.8 po w e r man a gement powe r mana gement like the stand ard 8052, the n7 9e825 serie s also have th e idle and powe r do wn m ode s of ope ration . in the idle mode, the cl o ck to the cp u is stopp ed while the tim ers, seri al ports and int e rrupt lock co ntinue to ope rate. in the powe r do wn mode, all clocks a r e sto pped a nd the chip o peration is compl e tely stoppe d . th is is the l owe st po wer con s um ption state. N79E825A/824a/823a/822a data sheet - 12 - 7 memory organization the n79e82 5 se rie s se pa rate the mem ory into two separate secti ons, the pro g r am mem o ry and the data memo ry. the progra m memory is use d to stor e the instru ctio n op-code s, while the dat a memory is used to sto r e data o r for memory ma p ped devi c e s . 7.1 program memory (on-chip flash) the prog ram memory on the n79e8 25 seri es can be up to 16k/8k/4k/2 k bytes long. all instruction s are fetched f o r exe c ution f r om this m e m o ry are a . th e movc inst ru ction can al so acce ss thi s memory regio n . 7.2 dat a me mo ry the nvm da ta memory of flash epro m on the n79e825 serie s can be up to 256 bytes long. th e n79e8 25 se ries read th e content of dat a memo ry by usin g ?m ovc a, @a+dpt r?. to write d a ta is b y nvmad dr, nvmdat a n d nvmc on sfr?s regi ste r s. o n - c h i p c ode m em or y s p ace 00 00 h 16k/8k/4k/2k bytes on-chip code memory u nus ed c ode m em or y unused code memory config 1 3 f ffh / 1 fffh 4 0 00h / 2 00 0h ffffh page 0 64 bytes p age 1 64 b y t es p age 2 64 b y t es p age 3 64 b y t es fc 0 0 h fc 3 fh fc 4 0 h fc 7 fh fc 8 0 h fc bfh fc c 0 h fc ffh n v m d a t a me mo r y a r e a fc00h config 2 fc ffh 256 b y t es nv m d a t a me mo r y fb ffh figure 7-1: n79e825/824/823/822 memory map N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 13 - revision a02 7.3 regist er m a p as mentio ne d befo r e the n79e8 25 se ries h ave sep arate p r og ra m and data memory are a s. the on- chip 25 6 byte s scratch p a d ram is in ad dition to the in ternal m e m o ry. there are also seve ra l special functio n re g i sters (sf r s) which ca n b e acce ssed b y software. t he sfrs ca n be acce ssed only by dire ct add re ssing, while th e on-chip ra m can be a cce ssed by eith er direct or in dire ct add re ssing. indirect ram addressing direct & indirect ram addressing sfr direct addressing only 00 h 7f h 80 h ff h r a m and s f r d at a m em or y s pac e figure 7 - 2: n79e 825/824/823/ 822 ram and sf r memor y map since the scratch-pad ra m is only 256 bytes it can be used only whe n data co ntents a r e sm all. there are several other spe c ial p u rpo s e a r e a s within t he scratch-pad ra m. these a r e describ ed a s follows. N79E825A/824a/823a/822a data sheet - 14 - bank 0 bank 1 bank 2 bank 3 03 02 01 00 04 05 06 07 0b 0a 09 08 0c 0d 0e 0f 13 12 11 10 14 15 16 17 1b 1a 19 18 1c 1d 1e 1f 23 22 21 20 24 25 26 27 2b 2a 29 28 2c 2d 2e 2f 33 32 31 30 34 35 36 37 3b 3a 39 38 3c 3d 3e 3f 43 42 41 40 44 45 46 47 4b 4a 49 48 4c 4d 4e 4f 53 52 51 50 54 55 56 57 5b 5a 59 58 5c 5d 5e 5f 63 62 61 60 64 65 66 67 6b 6a 69 68 6c 6d 6e 6f 73 72 71 70 74 75 76 77 7b 7a 79 78 7c 7d 7e 7f direct ram indirect ra m 00h 07 h 28 h 08 h 0f h 10 h 17 h 18 h 1f h 20 h 21 h 22 h 23 h 24 h 25 h 26 h 27 h 29 h 2a h 2b h 2c h 2d h 2e h 2fh 30 h 7f h 80 h ffh figure 7-3: scratch pad ram N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 15 - revision a02 7.4 working registers there are fou r sets of working r egi sters, each con s isti ng of eight 8- bit registe r s. these are termed as banks 0, 1, 2, and 3. individual regi st ers within th ese b an ks can be directl y acce ssed b y separate instru ction s . these individ ual regi sters are nam ed as r0, r1, r2, r3, r4, r5, r6 and r7. howeve r, at one time the n79e8 25 series can work with only one particular b a nk. the b an k sele ction is done by setting rs1 - rs0 bits in th e psw. the r0 an d r1 re gisters a r e u s ed to store th e address for indire ct ac ce ssi ng. 7.5 bit addressable locations the scrat c h - pad ram are a from location 20h to 2fh is byte as well as bit addre s sable. this mean s that a bit in this area ca n be individu ally addre s se d. in additio n som e of the sfrs are also bit addressa ble. the in stru ctio n decode r is able to distin guish a bit acce ss from a b y te acce ss by the type of the in stru ction itself. in the sfr are a , any ex isti ng sfr who s e a dd r e ss e nds i n a 0 o r 8 is bit addressa ble. 7.6 stac k the scratch - pad ram ca n be used fo r the sta ck. this a r ea i s sele cted by the stack pointer (sp), whi c h sto r e s the add re ss of the t op of the stack. wheneve r a ju mp, call or i n terru pt is invoke d the return address is placed o n the sta ck. there is no restri ction as to where the stack ca n be gin in the ram. by default ho wever, the stack p o inter contai n s 07 h at re se t. the use r can then ch an ge this to any value desired. the sp will point to the last us ed value. therefore, the sp will be incremented and then ad dre s s saved onto th e sta ck. conv ersely, while poppi ng fro m the sta c k the conte nts will be read first, and then the sp is decre ased. N79E825A/824a/823a/822a data sheet - 16 - 8 spe cial function registers the n79e82 5 se rie s uses special fu n c tion regi ste r s (sf r s) to control and monitor p erip heral s an d their mo de s. the sf rs re side i n t he re gister lo catio ns 8 0-f fh a n d ar e a c cessed by di re ct a ddre s sing only. some o f the sfrs are bit add re ssable. thi s is very useful i n ca se s wher e use r s wi sh t o modify a particula r bit without cha nging the others. the sfrs that are bit addressable are tho s e wh ose addresse s e nd in 0 or 8. the n79e8 25 seri es co ntain all the sfrs presen t in the standard 80 52. ho wever so me additio nal sfrs are ad ded. in some ca se s the u n use d bits i n the ori ginal 80 52, have been give n n e w fun c tion s. the list of the sfrs is a s follows. f8 ip1 f0 b p0id ip1h e8 eie e0 acc adccon adch d8 wdcon pwmpl pwm0l pwm1l pwmcon1 pwm2l pwm3l pwmcon2 d0 psw pwmph pwm0h pwm1h pwm2h pwm3h pwmcon3 c8 nvmcon nvmdat c0 i2con i2addr nvmaddr t a b8 ip0 saden i2dat i2st a t us i2clk i2timer b0 p0m1 p0m2 p1m1 p1m2 p2m1 p2m2 ip0h a8 ie saddr cmp1 cmp2 a0 p2 kbi auxr1 98 scon sbuf 90 p1 divm 88 tc o n tm o d tl 0 tl 1 th 0 th 1 c k c o n 80 p0 sp dpl dph pcon table 8 - 1: special fu nctio n regi ster l o c ation ta ble note : 1. t he sf rs in the column w i th da rk bord er s are bit-add ressable 2. the table is condensed w i th eight loca tions per ro w. empt y locations indicate that these ar e no registers at t hese addresses. when a bit or re gister is not implemented, it w ill read hi gh. N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 17 - revi si on a0 2 symbol definit ion a ddr ess msb bit_ a d dre ss, symbol lsb reset ip1 interrupt priority 1 f 8 h (ff) - (fe) - (fd) pp w m (fc) pw di (fb) pc2 (fa) pc1 (f9) pkb (f8) pi2 xx000000b ip1h interrupt high priority 1 f7h - - ppwmh pwdih pc2h pc 1h pkbh pi2h xx000000b p0ids port 0 digi tal in put disable f6h 00000000b b b register f0h (f7) (f6) (f5) (f4) (f3) (f2) (f1) (f0) 00000000b eie interrupt enable 1 e8h (ef) - (ee) - (ed) ep w m (ec) ew di (eb) ec2 (ea) ec1 (e9) ekb (e8) ei2c xx000000b adch adc converter result e2h adc.9 adc.8 adc.7 adc.6 adc.5 adc.4 adc.3 adc.2 xxxxxxxxb adccon adc control regi ster e1h adc.1 adc.0 adcex adci adcs rcclk aadr1 aadr0 xx000x00b acc accumulator e0h (e7) (e6) (e5) (e4) (e3) (e2) (e1) (e0) 00000000b pwmcon2 pwm control register 2 dfh bkch bkps bpen bken pwm3b pwm2b pwm1b pwm0b 00000000b pwm3l pwm 3 low bits register deh pwm3.7 pwm3.6 pwm3.5 pwm3.4 pwm3.3 pwm3.2 pwm3.1 pwm3.0 00000000b pwm2l pwm 2 low bits register ddh pwm2.7 pwm2.6 pwm2.5 pwm2.4 pwm2.3 pwm2.2 pwm2.1 pwm2.0 00000000b pwmcon1 pwm control register 1 dch pwmrun load cf c lrpwm pwm3i pwm2i pwm1i pwm0i 00000000b pwm1l pwm 1 low bits register dbh pwm1.7 pwm1.6 pwm1.5 pwm1.4 pwm1.3 pwm1.2 pwm1.1 pwm1.0 00000000b pwm0l pwm 0 low bits register dah pwm0.7 pwm0.6 pwm0.5 pwm0.4 pwm0.3 pwm0.2 pwm0.1 pwm0.0 00000000b pw mp l pw m c o un t e r l o w register d9h pwmp0.7 pwmp0. 6 pwmp0. 5 p wmp0.4 pwmp0. 3 pwmp0. 2 pwmp0.1 pwmp0. 0 00000000b wdcon watch-dog control d8h (df) w drun (de) - (dd) wd 1 (dc) wd 0 (db) wd if (da) wt r f (d9) ew rs t (d8) w dclr 0x 000000b pwmcon3 pwm control register 3 d7h - - - - - - - bkf xxxxxxx0b pwm3h pwm 3 high bits register d6h - - - - - - pwm3.9 pwm3.8 xxxxxx00b pwm2h pwm 2 high bits register d5h - - - - - - pwm2.9 pwm2.8 xxxxxx00b pwm1h pwm 1 high bits register d3h - - - - - - pwm1.9 pwm1.8 xxxxxx00b pwm0h pwm 0 high bits register d2h - - - - - - pwm0.9 pwm0.8 xxxxxx00b pw mp h p w m cou nter high register d1h - - - - - - pw mp 0. 9 pw mp 0. 8 xxxx xx00b psw program statu s w ord d0h (d7) cy (d6) ac (d5) f0 (d4) rs1 (d3) rs0 (d2) ov (d1) f1 (d0) p 00000000b nvmdata nvm data cfh 00000000b nvmcon nvm control ceh eer ewr - - - - - - 00000000b ta t i m ed ac ce ss prote c ti on c7h ta.7 ta.6 ta.5 ta.4 ta.3 ta.2 ta.1 ta.0 11111111b nvmaddr nvm addre s s c6h 00000000b i2addr i2c address1 c1h addr.7 addr.6 addr.5 addr.4 addr.3 addr.2 addr.1 gc xxxxxxx0b i 2 con i 2 c cont rol regis t er c0h (c7) - (c6) ens1 (c5) sta (c4) sto (c3) si (c2) aa (c1) - (c0) - x 00000 xx b i2t i m e r i2c timer counter register bfh - - - - - enti div4 tif 00000000b i2clk i2c clock rate beh i2clk.7 i2clk.6 i2c lk.5 i2clk.4 i2clk.3 i2clk.2 i2clk.1 i2clk.0 00000000b i2status bdh 1111000b i2dat bch i2dat.7 i2dat.6 i2dat.5 i2dat.4 i2dat.3 i2dat.2 i2dat.1 i2dat.0 xxxxxxxxb saden slav e address ma sk b9h 00000000b ip0 interrupt priority b8h (bf) - (be) padc (bd) pbo (bc) ps (bb) pt1 (ba) px 1 (b9) pt0 (b8) px 0 x 0000000b ip0h interrupt high priority b7h - pa dch pboh psh pt1h px1h pt0h px0h x0000000b p2m2 port 2 output mode 2 b6h - - - - - - p2m2.1 p2m2.0 xxxxxx00b p2m1 port 2 output mode 1 b5h p2s p1s p0s enclk t1oe t0oe p2m1.1 p2m1.0 00000000b p1m2 port 1 output mode 2 b4h p1m2.7 p1m2.6 - p1m2.4 p1m2.3 p1m2.2 p1m2.1 p1m2.0 00000000b p1m1 port 1 output mode 1 b3h p1m1.7 p1m1.6 - p1m1.4 p1m1.3 p1m1.2 p1m1.1 p1m1.0 00000000b p0m2 port 0 output mode 2 b2h p0m2.7 p0m2.6 p0m2.5 p0m2.4 p0m2.3 p0m2.2 p0m2.1 p0m2.0 00000000b p0m1 port 0 output mode 1 b1h p0m1.7 p0m1.6 p0m1.5 p0m1.4 p0m1.3 p0m1.2 p0m1.1 p0m1.0 00000000b N79E825A/824a/823a/822a data sheet - 18 - continued symbol definit ion a ddr ess msb bit_ a d dre ss, symbol lsb reset cmp2 comparator 2 con t r o l register adh - - ce2 cp2 cn2 oe2 co2 cmf2 00000000b cmp1 comparator 1 con t r o l register ach - - ce1 cp1 cn1 oe1 co1 cmf1 00000000b saddr slav e address a9h 00000000b ie interrupt enable a8h (af) ea (ae) eadc (ad) ebo (ac) es (ab) et1 (aa) ex 1 (a9) et0 (a8) ex 0 00000000b auxr1 aux function register a2h kbf bod boi lpbov srst adcen 0 dps 000x0000b kbi key board interrup t a1h 00000000b p2 port 2 a0h (a7) - (a6) - (a5) - (a4) - (a3) - (a2) - (a1) x t al1 (a0) x t al2 clkout xxxx xx11b sbuf serial buff er 99h xxxx xxx x b scon serial control 98h (9f) sm0/fe (9e) sm1 (9d) sm2 (9c) ren (9b) tb8 (9a) rb8 (99) ti (98) ri 00000000b divm uc clo c k div ide regi ste r 95h 00000000b p1 port 1 90h (97) pw m2 (96) pw m1 (95) /r st (94) /in t 1 (93) /in t 0 sdl (92) t0 scl (91) rx d (90) tx d 11111111b ckcon clock control 8eh - - - t1m t0m - - - xxx00xxxb th1 timer high 1 8dh 00000000b th0 timer high 0 8ch 00000000b tl1 timer low 1 8bh 00000000b tl0 timer low 0 8ah 00000000b tmod timer mode 89h gate c/t m1 m0 gate c/t m1 m0 00000000b tcon timer control 88h (8f) tf1 (8e) tr1 (8d) tf0 (8c) tr0 (8b) ie1 (8a) it 1 (89) ie0 (88) it 0 00000000b pcon power control 87h smod smod0 bof por gf1 gf0 pd idl 00xx0000b dph data poi nter high 83h 00000000b dpl data poi nter low 82h 00000000b sp sta c k poin t er 81h 00000111b p0 port 0 80h (87) t1 (86) ad3 cmp1 (85) ad2 cmpref (84) ad1 ci n1a (83) ad0 ci n1b (82) brake ci n2a (81) pw m0 ci n2b (80) pw m3 cmp2 11111111b table 8 - 2: special fu nctio n regi sters N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 19 - revi si on a0 2 port 0 bit: 7 6 5 4 3 2 1 0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 mnemo n ic: p0 addre ss: 80 h p0.7-0: ge ne ral pu rpo s e i nput/output port. mo st in stru ction s will read th e po rt pins in ca se of a port read a c ce ss, however in case of r ead -modify-write instru ction s , the por t lat c h i s re ad. the s e alternate function s are descri bed b el ow: bit name function 7 p0.7 timer 1 pin or kbi.7 pin of keypad input. 6 p0.6 cmp1 pin of analog comparator or kbi.6 pin of keypad input. 5 p0.5 cmpref pin of analog comparator or kbi.5 pin of keypad input. 4 p0.4 cin1a pin of analog comparator or kbi.4 pin of keypad input. 3 p0.3 cin1b pin of analog comparator or kbi.3 pin of keypad input. 2 p0.2 brake pin of pwm or cin2a pin of anal og comparator or kbi.2 pin of keypad input. 1 p0.1 pwm0 pin or cin2b pin of analog comparator or kbi.1 pin of keypad input. 0 p0.0 pwm3 pin or cmp2 pin of analog comparator or kbi.0 pin of keypad input. note: the initial value of the port is set by confi g 1.prhi bi t. t h e default setting for confi g 1.pr hi =1 w h ich the alternative function output i s turned o n upo n reset. if con f ig1.p rhi is se t to 0, th e user has to w r ite a 1 to port sfr to turn on the alternative function output. stac k poi n ter bit: 7 6 5 4 3 2 1 0 sp.7 sp.6 sp.5 sp.4 sp.3 sp.2 sp.1 sp.0 mnemo n ic: sp addre s s: 81h bit name function 7-0 sp.[7:0] the stack pointer stores the scratch-pa d ram address where the stack begins. in other words it always points to the top of the stack. dat a poin t e r low bit: 7 6 5 4 3 2 1 0 dpl.7 dpl.6 dpl.5 dpl.4 dpl.3 dpl.2 dpl.1 dpl.0 mnemo n ic: dpl addre s s: 82h bit name function 7-0 dpl.[7:0] this is the low byte of the standard 8052 16-bit data pointer. dat a poin t e r hig h bit: 7 6 5 4 3 2 1 0 dph.7 dph.6 dph.5 dph.4 dph.3 dph.2 dph.1 dph.0 N79E825A/824a/823a/822a data sheet - 20 - mnemo n ic: dph addre s s: 83h bit name function 7-0 dph.[7:0] this is the high byte of the standard 8052 16-bit data pointer. this is the high byte of the dptr 16-bit data pointer. power c o ntr ol bit: 7 6 5 4 3 2 1 0 smod smod0 bof por gf1 gf0 pd idl mnemo n ic: pco n address: 87h bit name function 7 smod 1: this bit doubles the serial port baud rate in mode 1, 2, and 3. 6 smod0 0: framing erro r dete ction disable. sc on. 7 (sm0/fe) bit is use d as sm 0 (stan da r d 80 52 functio n). 1: framing e rro r dete ctio n enable. sco n .7 (sm0 /fe) bit is used to reflect as frame e rro r (fe) statu s flag. 5 bof 0: cleared by softwa r e. 1: set autom atically when a brownout reset o r inte rrupt ha s o c curred. also set at power on. 4 por 0: cleared by softwa r e. 1: set automatically wh en a power-on reset ha s o c curred. 3 gf1 general purpose user flags. 2 gf0 general purpose user flags. 1 pd 1: the cpu goe s into the power do wn mod e. in this mode, all the clocks a r e stopp ed an d prog ram exe c ution is fro z e n. 0 idl 1: the cpu goes into the idle mode. in this mode, the cl ocks cp u cl ock stopp ed, so p r og ram exe c ution is f r o z e n . but the clo ck to th e seri al, timer an d interrupt blo c ks i s not stop ped, and the s e blocks co ntinue op eratin g . timer co n t rol bit: 7 6 5 4 3 2 1 0 t f 1 t r1 t f 0 t r0 ie1 it 1 ie0 it 0 mnemo n ic: t c o n addre s s: 88h bit name function 7 tf1 timer 1 overflow flag. this bit is set when timer 1 overflows. it is cleared automatically when the program does a timer 1 interrupt service routine. software can also set or clear this bit. 6 tr1 timer 1 run control. this bit is set or cl eared by software to turn timer/counter on or off. N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 21 - revision a02 continued bit name function 5 tf0 timer 0 overflow flag. this bit is set when timer 0 overflows. it is cleared automatically when the program does a timer 0 interrupt service routine. software can also set or clear this bit. 4 tr0 timer 0 run control. this bit is set or cl eared by software to turn timer/counter on or off. 3 ie1 interrupt 1 edge detect flag: set by hardware when an edge/level is detected on int1 . this bit is cleared by hardware when the service routine is vectored to only if the interrupt was edge triggered. otherwise it follows the inverse of the pin. 2 it1 interru pt 1 ty pe control. s e t/cleared by softwa r e to spe c ify falling edge/ lo w le vel trigge red exte rnal inp u ts. 1 ie0 interrupt 0 edge detect flag. set by hardware when an edge/level is detected on int0 . this bit is cleared by hardware when the service routine is vectored to only if the interrupt was edge triggered. otherwise it follows the inverse of the pin. 0 it0 interru pt 0 ty pe control: s e t/cleared by softwa r e to spe c ify falling edge/ lo w le vel trigge red exte rnal inp u ts. timer mod e cont ro l bit: 7 6 5 4 3 2 1 0 gate t c / m1 m0 gate t c / m1 m0 timer1 timer0 mnemo n ic: t m od addre s s: 89h bit name function 7 gate gating control: when this bit is set, timer/counter 1 is enabled only while the int1 pin is high and the tr1 control bit is set. when cleared, the int1 pin has no effect, and timer 1 is enabled whenever tr1 control bit is set. 6 t c/ timer o r cou nter sele ct: whe n cl ear, timer 1 i s in cre m ente d b y the internal clo ck. whe n set, the timer co unt s falling ed ge s on the t1 pi n. 5 m1 timer 1 mode select bit 1. see table below. 4 m0 timer 1 mode select bit 0. see table below. 3 gate gating control: when this bit is set, timer/counter 0 is enabled only while the int0 pin is high and the tr0 control bit is set. when cleared, the int0 pin has no effect, and timer 0 is enabled whenever tr0 control bit is set. 2 t c/ timer o r cou nter sele ct: whe n cl ear, timer 0 i s in cre m ente d b y the internal clo ck. whe n set, the timer co unt s falling ed ge s on the t0 pi n. 1 m1 timer 0 mode select bit 1. see table below. 0 m0 timer 0 mode select bit 0. see table below. N79E825A/824a/823a/822a data sheet - 22 - m1, m0: mod e select bits: m1 m0 mode 0 0 mode 0: 8-bit timer/counter tlx serves as 5-bit pre-scale. 0 1 mode 1: 16-bit timer/counter, no pre-scale. 1 0 mode 2: 8-bit timer/counter with auto-reload from thx. 1 1 mode 3: (timer 0) tl0 is an 8-bit timer/ counter controlled by the standard timer0 control bits. th0 is an 8-bit timer only controlled by timer1 control bits. (timer 1) timer/counter 1 is stopped. timer 0 lsb bit: 7 6 5 4 3 2 1 0 t l0.7 t l0.6 t l0.5 t l0.4 t l0.3 t l0.2 t l0.1 t l0.0 mnemo n ic: t l 0 addre s s: 8ah bit name function 7-0 tl0.[7:0] timer 0 lsb. timer 1 lsb bit: 7 6 5 4 3 2 1 0 t l1.7 t l1.6 t l1.5 t l1.4 t l1.3 t l1.2 t l1.1 t l1.0 mnemo n ic: t l 1 addre s s: 8bh bit name function 7-0 tl1.[7:0] timer 1 lsb. timer 0 msb bit: 7 6 5 4 3 2 1 0 t h 0.7 t h 0.6 t h 0.5 t h 0.4 t h 0.3 t h 0.2 t h 0.1 t h 0.0 mnemo n ic: t h 0 addre s s: 8ch bit name function 7-0 th0.[7:0] timer 0 msb. timer 1 msb bit: 7 6 5 4 3 2 1 0 t h 1.7 t h 1.6 t h 1.5 t h 1.4 t h 1.3 t h 1.2 t h 1.1 t h 1.0 mnemo n ic: t h 1 addre s s: 8dh bit name function 7-0 th1.[7:0] timer 1 msb. N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 23 - revision a02 clo ck co n t rol bit: 7 6 5 4 3 2 1 0 - - - t 1 m t 0 m - - - mnemo n ic: ckcon addre ss: 8e h bit name function 7-5 - reserved. 4 t1m timer 1 cloc k sele ct : 0: timer 1 uses a divide by 12 clocks. 1: timer 1 uses a divide by 4 clocks. 3 t0m timer 0 cloc k sele ct : 0: timer 0 uses a divide by 12 clocks. 1: timer 0 uses a divide by 4 clocks. 2-0 - reserved. port 1 bit: 7 6 5 4 3 2 1 0 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 mnemo n ic: p1 addre ss: 90 h p1.7-0: ge ne ral pu rpo s e i nput/output port. mo st in stru ction s will read th e po rt pins in ca se of a port read a c ce ss, however in case of r ead -modify-write instru ction s , the por t lat c h i s re ad. the s e alternate function s are descri bed b el ow: bit name function 7 p1.7 pwm 2 pin. 6 p1.6 pwm 1 pin. 5 p1.5 /rst pin or input pin by alternative. 4 p1.4 /int1 interrupt. 3 p1.3 /int0 interrup t or sda of i2c. 2 p1.2 timer 0 or scl of i2c. 1 p1.1 rxd of serial port. 0 p1.0 txd of serial port. note: the initial value of the port is set by confi g 1.prhi bi t. t h e default setting for confi g 1.pr hi =1 w h ich the alternative function output i s turned o n upo n reset. if con f ig1.p rhi is se t to 0, th e user has to w r ite a 1 to port sfr to turn on the alternative function output. divider c l oc k bit: 7 6 5 4 3 2 1 0 divm.7 divm.6 divm.5 divm.4 divm.3 divm.2 divm.1 divm.0 mnemonic: divm address: 95h N79E825A/824a/823a/822a data sheet - 24 - bit name function 7-0 divm.[7:0] the divm register is clock divider of uc. refer oscillator chapter. serial port control bit: 7 6 5 4 3 2 1 0 sm0/f e sm1 sm2 ren t b 8 rb8 t i ri mnemo n ic: sco n addre s s: 98h bit name function 7 sm0/fe serial port mode select bit 0 or framing error flag: the smod0 bit in pcon sfr determines whether this bit acts as sm 0 or as fe. the operation of sm0 is described below. when used as fe, this bit will be set to indicate an invalid stop bit. this bit must be manually cleared in software to clear the fe condition. 6 sm1 serial port mode select bit 1. see table below. 5 sm2 multiple processors communication. setting this bit to 1 enables the multiprocessor communication feature in mode 2 and 3. in mode 2 or 3, if sm2 is set to 1, then ri will not be activated if the received 9th data bi t (rb8) is 0. in mode 1, if sm2 = 1, then ri will not be activated if a valid stop bit was not received. in mode 0, the sm2 bit controls the serial port clock. if set to 0, then the serial port runs at a divide by 12 clock of the oscillator. this gives co mpatibility with the standard 8052. when set to 1, the serial clock become divide by 4 of the oscillato r clock. this results in faster synchronous serial communication. 4 ren re ceive en ab le: 0: disa ble serial reception. 1: enable serial reception. 3 tb8 this is the 9th bit to be transmitted in modes 2 and 3. this bit is set and cleared by software as desired. 2 rb8 in modes 2 and 3 this is the received 9th dat a bit. in mode 1, if sm2 = 0, rb8 is the stop bit that was received. in mode 0 it has no function. 1 ti transmit interrupt flag: this flag is set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in all other modes during serial transmission. this bit must be cleared by software. 0 ri receive interrupt flag: this flag is set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bits time in the other modes during serial reception. however the restri ctions of sm2 apply to this bit. this bit can be cleared only by software. N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 25 - revision a02 sm0, sm1: mode select b i ts mode sm0 sm1 descri ptio n length baud rate 0 0 0 synchrono us 8 tclk divided by 4 or 12 1 0 1 asynch ro nou s 10 variable 2 1 0 asynch ro nou s 11 tclk divided by 32 or 64 3 1 1 asynch ro nou s 11 variable serial dat a buffe r bit: 7 6 5 4 3 2 1 0 sbuf.7 sbuf.6 sbuf.5 sbuf.4 sbuf.3 sbuf.2 sbuf.1 sbuf.0 mnemo n ic: sbuf addre s s: 99h bit name function 7-0 sbuf.[7:0] serial data on the serial port is read from or written to this location. it actually consists of two separate internal 8-bit re gisters. one is the receive resister, and the other is the transmit buffer. any re ad access gets data from the receive data buffer, while write access is to the transmit data buffer. port 2 bit: 7 6 5 4 3 2 1 0 - - - - - - p2.1 p2.0 mnemo n ic: p2 addre s s: a0h bit name function 7-2 - reserved 1 p2.1 xtal1 clock input pin. 0 p2.0 xtal2 or clkout pin by alternative. note: the initial value of the port is set by confi g 1.prhi bi t. t h e default setting for confi g 1.pr hi =1 w h ich the alternative function output i s turned o n upo n reset. if con f ig1.p rhi is se t to 0, th e user has to w r ite a 1 to port sfr to turn on the alternative function output. keybo a rd inter rupt bit: 7 6 5 4 3 2 1 0 kbi.7 kbi.6 kbi.5 kbi.4 kbi.3 kbi.2 kbi.1 kbi.0 mnemo n ic: kbi addre s s: a1h bit name function 7 kbi.7 1: enable p0.7 as a cause of a keyboard interrupt. 6 kbi.6 1: enable p0.6 as a cause of a keyboard interrupt. 5 kbi.5 1: enable p0.5 as a cause of a keyboard interrupt. 4 kbi.4 1: enable p0.4 as a cause of a keyboard interrupt. N79E825A/824a/823a/822a data sheet - 26 - continued . bit name function 3 kbi.3 1: enable p0.3 as a cause of a keyboard interrupt. 2 kbi.2 1: enable p0.2 as a cause of a keyboard interrupt. 1 kbi.1 1: enable p0.1 as a cause of a keyboard interrupt. 0 kbi.0 1: enable p0.0 as a cause of a keyboard interrupt. aux f u n c ti on re gister 1 bit: 7 6 5 4 3 2 1 0 kbf bod boi lpbov srst adcen 0 dps mnemo n ic: auxr1 address: a2h bit name function 7 kbf keyboard interrupt flag: 1: whe n any pin of po rt 0 that is en abl e d for the key board interru p t function g o e s low. must be clea red by so ftware. 6 bod brown out di sabl e: 0: enable bro w no ut dete ct function. 1: disa ble brown out dete ct function and save po wer. 5 boi brown out interrupt: 0: disable brown out dete ct interrupt function and it will cau s e chi p reset wh en bof is s e t. 1: this preve nts brownout detection from cau s ing a chip re set and allo ws th e brownout detect functio n to be used a s an interrupt. 4 lpbov low po we r brown out det ect co ntrol: 0: whe n bo d is ena ble, the bro w n out detect i s al ways turned on by norm a l ru n or power dow n mode. 1: when bo d is ena ble, the brown o u t detect circuit is turned on by power do wn m ode. this co ntrol can hel p save 15/16 of th e brownout circuit power. whe n uc i s in powe r do wn mo de, the bod will e nable inte rna l rc os c (2m h z~0.5m hz) 3 srst software reset: 1: reset the chip as if a hardwa r e reset occurred. 2 adce n 0: disa ble adc circuit. 1: enable adc circuit. 1 0 reserved. 0 dps dual data pointer selec t 0: to sele ct dptr of sta n dard 8 051. 1: to sele ct dp tr 1 interrupt enable N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 27 - revision a02 bit: 7 6 5 4 3 2 1 0 ea eadc ebo es et 1 ex1 et 0 ex0 mnemonic : ie addre s s: a8h bit name function 7 ea global enable. enable/disable all interrupts. 6 eadc enable adc interrupt. 5 ebo enable brown out interrupt. 4 es enable serial port interrupt. 3 et1 enable timer 1 interrupt. 2 ex1 enable external interrupt 1. 1 et0 enable timer 0 interrupt. 0 ex0 enable external interrupt 0. slave address bit: 7 6 5 4 3 2 1 0 saddr.7 saddr.6 saddr.5 saddr.4 saddr.3 saddr.2 saddr.1 saddr.0 mnemo n ic: saddr addre s s: a9h bit name function 7-0 saddr.[7:0] the saddr should be programmed to the given or broadcast address for serial port to which the slave processor is designated. comp ar at or 1 c on t rol register bit: 7 6 5 4 3 2 1 0 - - ce1 cp1 cn1 oe1 co1 cmf1 mnemo n ic: cmp1 addre s s: ach bit name function 7 - reserved. 6 - reserved. 5 ce1 comp arator e nable: 0: disa ble co mparator. 1: enabled comparator. comparator out put need wait stable 10 us after ce1 is first set. 4 cp1 comp arator p o sitive input select: 0: cin1a is selected as the positive comparator input. 1: cin1b is selected as the positive comparator input. N79E825A/824a/823a/822a data sheet - 28 - continued. bit name function 3 cn1 comp arator n egative input sele ct: 0: the com parato r refe rence pin cmpref is sele cted a s the negative comp arator in put. 1: the inte rn al compa r ato r referen c e v r ef is sele cted as the ne gati v e com parato r input. 2 oe1 output ena bl e: 1: the com p arato r output is conn ecte d to the cmp1 pin if the compa r ato r is enabl ed (ce1 = 1). this o u t put is asyn ch rono us to the cpu cl ock. 1 co1 comp arator o u tput: synchroni zed to the cpu clo ck to all ow readi ng by software. clea red whe n the comp arator is disabl ed (ce 1 = 0). 0 cmf1 comp arator i n terrupt flag: this bit is set by hardware wheneve r th e comp arato r output co1 cha nge s stat e. this bit will cau s e a ha rdwa re interru p t if enabled and of sufficient prio rity. clea red by software a nd whe n the co mparator is di sabl ed (ce1 = 0). comp ar at or 2 c on t rol register bit: 7 6 5 4 3 2 1 0 - - ce2 cp2 cn2 oe2 co2 cmf2 mnemon ic: cmp2 addre s s: adh bit name function 7 - re serv e d . 6 - re serv e d . 5 ce2 comp arator e nable: 0: disa ble co mparator. 1: enabled compa r ator. compa r ator ou t put need wai t stable 10 us after ce2 is firs t s e t. 4 cp2 comp arator p o sitive input select: 0: cin2a is selecte d as th e positive co mparator inp u t. 1: cin2b is selecte d as th e positive co mparator inp u t. 3 cn2 comp arator n egative input sele ct: 0: the com parato r refe rence pin cmpref is sele cted a s the negative comp arator in put. 1: the inte rn al co mpa r ato r refe ren c e v r ef is sele cted as the ne gati v e com parato r input. N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 29 - revision a02 continued . bit name function 2 oe2 output ena bl e: 1: the comparator output is connected to the cmp2 pin if the comparator is enabled (ce2 = 1). this output is asynchronous to the cpu clock. 1 co2 comp arator o u tput: synchronized to the cpu clock to allow reading by software. cleared when the comparator is disabled (ce2 = 0). 0 cmf2 comp arator i n terrupt flag: this bit is set by hardware whenever th e comparator output co2 changes state. this bit will cause a hardware interrupt if enabled and of sufficient priority. cleared by software and when the comparator is disabled (ce2 = 0). port 0 o u t p ut mo de 1 bit: 7 6 5 4 3 2 1 0 p0m1.7 p0m1.6 p0m1 .5 p0m1.4 p0m1.3 p0 m1.2 p0m1.1 p0m1.0 mnemo n ic: p0m1 addre s s: b1h bit name function 7-0 p0m1.[7:0] to control the output configuration of p0 bits [7:0] port 0 o u t p ut mo de 2 bit: 7 6 5 4 3 2 1 0 p0m2.7 p0m2.6 p0m2 .5 p0m2.4 p0m2.3 p0 m2.2 p0m2.1 p0m2.0 mnemo n ic: p0m2 addre s s: b2h bit name function 7-0 p0m2.[7:0] to control the output configuration of p0 bits [7:0] port 1 o u t p ut mo de 1 bit: 7 6 5 4 3 2 1 0 p1m1.7 p1m1.6 - p1m1.4 p1 m1.3 p1m1.2 p1m1.1 p1m1.0 mnemo n ic: p1m1 addre s s: b3h bit name function 7-0 p1m1.[7:0] to control the output configuration of p1 bits [7:0] port 1 o u t p ut mo de 2 bit: 7 6 5 4 3 2 1 0 p1m2.7 p1m2.6 - p1m2.4 p1 m2.3 p1m2.2 p1m2.1 p1m2.0 mnemonic: p1m2 address: b4h N79E825A/824a/823a/822a data sheet - 30 - bit name function 7-0 p1m2.[7:0] to control the output configuration of p1 bits [7:0] port 2 o u t p ut mo de 1 bit: 7 6 5 4 3 2 1 0 p2s p1s p0s enclk t 1 oe t 0 oe p2m1.1 p2m1.0 mnemo n ic: p2m1 addre s s: b5h bit name function 7 p2s 0: disa ble schmitt trigger i nputs o n port 2 and en able ttl input s on port 2. 1: enables schmitt trigger inputs on port 2. 6 p1s 0: disa ble schmitt trigger i nputs o n port 1 and en able ttl input s on port 1. 1: enables schmitt trigger inputs on port 1. 5 p0s 0: disa ble schmitt trigger i nputs o n port 0 and en able ttl input s on port 0 1: enables schmitt trigger inputs on port 0. 4 enclk 1: enabled clock out put to xtal2 pin (p2.0) 3 t1oe 1: the p0.7 pin is toggled whenever time r 1 overflows. the output frequency is therefore one half of the timer 1 overflow rate. 2 t0oe 1: the p1.2 pin is toggled whenever time r 0 overflows. the output frequency is therefore one half of the timer 0 overflow rate. 1 p2m1.1 to control the output configuration of p2.1. 0 p2m1.0 to control the output configuration of p2.0. port 2 o u t p ut mo de 2 bit: 7 6 5 4 3 2 1 0 - - - - - - p2m2.1 p2m2.0 mnemo n ic: p2m2 addre s s: b6h bit name function 7-2 - reserved. 1-0 p2m2.[1:0] to control the output configuration of p2 bits [1:0] N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 31 - revision a02 port output con f igura t ion settings : pxm1. y pxm2. y port in put / out p ut mo de 0 0 quasi-bidirectional 0 1 push-pull 1 0 input only (hi gh impeda nce) p2m1.pxs=0 , ttl input p2m1.pxs=1 , schmitt input 1 1 open drain interrupt high p r iority bit: 7 6 5 4 3 2 1 0 - padch pboh psh pt 1h px1h pt 0h px0h mnemo n ic: ip0h addre s s: b7h bit name function 7 - this bit is un-implemented and will read high. 6 padch 1: to set interrupt high priority of adc is highest priority level. 5 pboh 1: to set interrupt high priority of br own out detector is highest priority level. 4 psh 1: to set interrupt high priority of serial port 0 is highest priority level. 3 pt1h 1: to set interrupt high priority of timer 1 is highest priority level. 2 px1h 1: to set interrupt high priority of exte rnal interrupt 1 is highest priority level. 1 pt0h 1: to set interrupt high priority of timer 0 is highest priority level. 0 px0h 1: to set interrupt high priority of exte rnal interrupt 0 is highest priority level. interrupt priority 0 bit: 7 6 5 4 3 2 1 0 - padc pbo ps pt 1 px1 pt 0 px0 mnemonic : ip addre s s: b8h bit name function 7 - this bit is un-implemented and will read high. 6 padc 1: to set interrupt priority of adc is higher priority level. 5 pbo 1: to set interrupt priority of brow n out detector is hig her priority level. 4 ps 1: to set interrupt priority of se rial port 0 is higher priority level. 3 pt1 1: to set interrupt priority of timer 1 is higher priority level. 2 px1 1: to set interrupt priority of exter nal interrupt 1 is higher priority level. 1 pt0 1: to set interrupt priority of timer 0 is higher priority level. N79E825A/824a/823a/822a data sheet - 32 - 0 px0 1: to s e t interrupt priority of exter nal interru pt 0 is high er pri o rity level. slave address mask enable bit: 7 6 5 4 3 2 1 0 saden.7 saden.6 sad en.5 saden.4 saden.3 sad en.2 saden.1 saden.0 mnemo n ic: saden addre s s: b9h bit name function 7-0 saden [7:0] this register enables the automatic addr ess recognition feature of the serial port 0. when a bit in the saden is set to 1, the same bit location in saddr will be compared with the incoming serial data. when saden is 0, then the bit becomes a "don't care" in the comparison. this register enables the automatic address recognition feature of the serial port 0. when all the bits of saden are 0, interrupt will occur for any incoming address. i2c da ta register bit: 7 6 5 4 3 2 1 0 i2dat . 7 i2dat . 6 i2dat . 5 i2dat . 4 i2dat . 3 i2dat . 2 i2dat . 1 i2dat . 0 mnemo n ic: i2 dat addre s s: bch bit name function 7-0 i2dat.[7:0] the data register of i2c. i2c stat us register bit: 7 6 5 4 3 2 1 0 b7 b6 b5 b4 b3 b2 b1 b0 mnemo n ic: i2 status addre s s: bdh bit name function 7-0 i2status.[7:0] the statu s re gister of i2 c: the three least significant bits are always 0. the five most significant bits contain the status code. there are 23 possible status codes. when i2status contains f8h, no serial interrupt is requested. all other i2status values correspond to defined i2c states. when each of these states is entered, a status interrupt is requested (si = 1). a valid status code is present in i2status one machine cycle after si is set by hardware and is still present one machine cycle after si has been reset by software. in addition, states 00h stands for a bus error. a bus error occurs when a start or stop condition is present at an illegal position in the formation frame. example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit. i2c ba ud ra te c o n t rol r egister bit: 7 6 5 4 3 2 1 0 i2clk.7 i2clk.6 i2clk.5 i2clk.4 i2clk.3 i2clk.2 i2clk.1 i2clk.0 mnemonic: i2clk address: beh N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 33 - revi si on a0 2 bit name function 7-0 i2clk.[7:0] the i2c clock rate bits. i2c timer c ou n ter re gister bit: 7 6 5 4 3 2 1 0 - - - - - ent i div4 tif mnemo n ic: i2 timer addre s s: bfh bit name function 7~3 - reserved. 2 enti enable i2c 1 4-bits ti mer cou nter: 0: disa ble 14 -bits tim er counter cou nt. 1: enable 14-bits timer counter coun t. after enable enti and ensi, the 14-bit counter will be counted. when si flag of i2c is set, the counter will stop to count and 14-bits timer counter will be cleared. 1 div4 i2c time r co unter cl ock source divide f unctio n: 0: the 14-bits timer count er so urce clo ck i s fo sc clo ck. 1: the 14-bits timer counter so urce clock is divided by 4. 0 tif the i2c timer counter c o unt flag: 0: the 14-bits timer count er is not ove r flow. 1: the 14-bits timer counter is overfl ow. before enable i2c timer (both enti, ensi = [1,1]) the si must be cleared. if i2c interrupt is enabled. the i2c interrupt service routine will be execut ed. this bit is cleared by software. i2c co nt r ol registe r bit: 7 6 5 4 3 2 1 0 - ens1 sta sto si aa - - mnemo n ic: i2 co n addre s s: c0h bit name function 7 - reserved. 6 ens1 0: disa ble i2 c serial fu nction. the sda and scl o u tput are in a high impe dan ce state. sda and scl inp u t sign als a r e ig nore d , i2c is not in the add resse d slave mode o r it is not addressa ble, and sto bit in i2con is forced to ?0 ?. no othe r bits are affe cted. p1.2 (scl ) a nd p1.3 (sda ) may be use d as op en dra i n i/o ports. 1: enable i2c serial function. the p1.2 and p1.3 port latches must be to logic 1. N79E825A/824a/823a/822a data sheet - 34 - continued bit name function 5 sta the start fl ag. 0: the sta bit is reset, no start co ndi tion or re peat ed start co ndition will be gene rated. 1: the sta bit is set to enter a ma ster m ode. the i2 c hardware c hecks the sta t us of i2c bu s and gene rate s a start co ndi tion if t he bus is free. if bus is not free, then i2c wait s for a stop con d i tion and ge n e rate s a start condition after a delay. if sta is set wh ile i2c is alre ady in a mast er mod e and one or m o re bytes are transmitted or receive d , i2c tran smits a repeate d start co nditio n . sta may b e set any time. sta may also be set whe n i2c interfa c e is an ad dre s sed sl ave mode. 4 sto the bit sto bit is set whil e i2c is in a ma ste r mode. a stop condition is tran smitted to the i2c bus . when the stop c o nditi on is dete c te d on the bu s, the i2c hard w are clea rs the st o flag. in a slave mode, the sto flag may be set to recove r from a bus error conditio n . in this case, no stop condition i s tra n smitted to th e i2c bu s. ho wever, the i2c hard w a r e behave s a s if a stop condition ha s b een re ceive d and it swit che s to the not addressable sl ave re ceiv er m ode. the sto flag is automatically clea red by ha rdware. if the sta and sto bits are bot h set, then a stop con d ition is transmitted to the i2c bus i f i2c is in a master m ode (i n a slave mo de, i2c gen erates an intern al stop con d itio n whi c h is n o t transmitted ) . i2c then tran smits a start condition. 3 si 0: when the si flag is rese t, no serial int e rrupt is re qu ested, an d there is n o stretchin g on the se rial clo ck o n the scl line. 1: when a n e w sio state is pre s e n t in the i2status registe r , the si flag is se t by hard w a r e, an d, if the ea and ei2c(eie.0 ) bits a r e bot h set, an i2c interrupt is requ este d wh en si is set. only one stat e that does n o t cau s e si is set is i2status=f 8h, whi c h in d i cate s that no re levant stat e informatio n is available. whe n si is set, the low level cycle of the serial clo ck o n the scl lin e is stretch e d , and the serial transfe r is su spe nde d. the high level cy cle on the scl line is unaffecte d by the serial int e rrupt fl ag. si must be cl ea red by soft wa re. 2 aa the asse rt ackno w led ge flag 0: a not ackn owle dge (hig h level to sda) will be retu rned d u ri ng the ackn owl e d ge clo ck p u lse o n scl wh en: 1) a data ha s been re ceive d while sio is in the master receiver mo d e . 2) a data byte has bee n received whil e sio is in the addresse d slave re ceive r mode. 1: an acknowledge (l ow lev e l to sda) wi l l be returned durin g the ackno w le dge clock pulse on the scl line whe n : 1) the o w n slave add re ss ha s bee n re ceived. 2) a data byte has been re ceive d while sio is in the master receive r mod e . 3) a data byte has be e n received while sio is in the addresse d slave re ceiv er mod e. 4) t he gene ral call address ha s been receive d while the g eneral call bit (gc) in i2addr is s e t. 1 - reserved. 0 - reserved. N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 35 - revision a02 i2c addres s register bit: 7 6 5 4 3 2 1 0 i2addr.7 i2addr.6 i2addr.5 i 2a ddr.4 i 2addr.3 i 2addr.2 i 2addr.1 gc mnemo n ic: i2 addr addre s s: c1h bit name function 7~ 1 i2addr.[7:1] i2c address registe r : the 8051 uc can read from and write to this 8-bit, directly addressable sfr. the content of this register is i rrelevant when i2c is in master mode. in the slave mode, the seven most sign ificant bits must be loaded with the mcu?s own address. the i2c hardware will react if either of the address is matched. 0 gc gene ral call functio n . 0: disable general call function. 1: enable general call function. n v m ad dr ess bit: 7 6 5 4 3 2 1 0 n v m a ddr . 7 nvmaddr.6 nvmaddr. 5 nvmaddr.4 nvmaddr.3 nvmaddr.2nvmaddr.1 nvmaddr.0 mnemo n ic: nvmaddr addre s s: c6h bit name function 7~0 nvmad dr.[ 7 :0] the nvm ad dre ss: the register indicates nvm data memo ry of low byte address on on-chip code memory space. timed access bit: 7 6 5 4 3 2 1 0 ta . 7 ta . 6 ta . 5 ta . 4 ta . 3 ta . 2 ta . 1 ta . 0 mnemo n ic: t a addre s s: c7h bit name function 7-0 ta.[7:0] the timed a c cess registe r : the timed access register controls t he access to protected bits. to access protected bits, the user must first write aah to the ta. this must be immediately followed by a write of 55h to ta. now a window is opened in the protected bits for three machine cycles, during which the user can write to these bits. nvm co nt r ol bit: 7 6 5 4 3 2 1 0 eer ewr - - - - - - mnemonic: nvmcon address: ceh N79E825A/824a/823a/822a data sheet - 36 - bit name function 7 eer nvm pag e(n ) erase bit: 0: without erase nvm pag e(n ) . 1: set this bit to erase page(n) of nvm. the nvm has 4 pages and each page have 64 bytes data memory. before select page by nvmaddr register that will automatic enable page area, after set this bit, the page will be erased and program counter will halt at this instructi on. after finished, program counter will kept next instruction then executed . the nvm page?s address is defined in table below. 6 ewr nvm data wri t e bit: 0: without wri t e nvm data. 1: set this bit to write nvm bytes and prog ram counter will halt at this instruction. after write is finished, program counter will kept next instru ction then executed. 5-0 - reserved nvm d a ta bit: 7 6 5 4 3 2 1 0 nvmdat .7 nvmdat .6 nvmdat .5 nvmdat .4 nvmdat 3 n vmdat . 2 n vmdat . 1 nvmdat .0 mnemo n ic: nvmdata addre s s: cfh bit name function 7~0 nvmdat.[7:0] the nvm data write register. the read nvm data is by movc instruction. prog r a m stat us wo rd bit: 7 6 5 4 3 2 1 0 cy ac f0 rs1 rs0 ov f1 p mnemo n ic: psw addre s s: d0h bit name function 7 cy carry flag: set for an arithmetic operation which re sults in a carry being generated from the alu. it is also used as the accumulator for the bit operations. N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 37 - revision a02 continued bit name function 6 ac auxiliary carry: set when the previou s op eration re sulted in a carry fro m the high order nib b le. 5 f0 user flag 0: the ge neral purp o se flag that can b e se t or clea red b y the user. 4~3 rs1~rs0 register bank select bits. 2 ov overflow flag: set when a carry was gen erated from the se ve nth bi t but not from the 8th bit as a result of the previou s ope ration, or vice -versa. 1 f1 user fla g 1: the ge neral purp ose flag that can b e se t or clea red b y the user sof t ware. 0 p parity flag: set/cleared b y hardware to indicate o dd/ even numb e r of 1's in the a c cumulato r. rs.1-0 : re gister bank se lection bit s: rs1 rs0 register bank address 0 0 0 00-07h 0 1 1 08-0fh 1 0 2 10-17h 1 1 3 18-1fh pwmp co u n ter high bits register bit: 7 6 5 4 3 2 1 0 - - - - - - pwmp.9 pwmp.8 mnemo n ic: pwmph addre s s: d1h bit name function 7-2 - reserved. 1-0 pwmp.[9:8] the pwm counter register bits 9~8. pwm 0 hig h bits register bit: 7 6 5 4 3 2 1 0 - - - - - - pwm0.9 pwm0.8 mnemo n ic: pwm0 h addre s s: d2h bit name function 7~2 - reserved. 1~0 pwm0.[9:8] the pwm 0 high bits register bit 9~8. N79E825A/824a/823a/822a data sheet - 38 - pwm 1 hig h bits register bit: 7 6 5 4 3 2 1 0 - - - - - - pwm1.9 pwm1.8 mnemo n ic: pwm1 h addre s s: d3h bit name function 7~2 - reserved. 1~0 pwm1.[9:8] the pwm 1 high bits register bit 9~8. pwm 2 hig h bits register bit: 7 6 5 4 3 2 1 0 - - - - - - pwm2.9 pwm2.8 mnemo n ic: pwm2 h addre s s: d5h bit name function 7~2 - reserved. 1~0 pwm2.[9:8] the pwm 2 high bits register bit 9~8. pwm 3 hig h bits register bit: 7 6 5 4 3 2 1 0 - - - - - - pwm3.9 pwm3.8 mnemo n ic: pwm3 h addre s s: d6h bit name function 7~2 - reserved. 1~0 pwm3.[9:8] the pwm 3 high bits register bit 9~8. pwm co nt rol register 3 bit: 7 6 5 4 3 2 1 0 - - - - - - - bkf mnemonic: pwmcon3 address: d7h bit name function 7-6 - reserved. 0 bkf the extern al bra k e pin fl a g . 0: the pwm i s not brake. 1: the pwm is brake by external brake pin. it will be cleared by software. wa tc hd og con t r ol bit: 7 6 5 4 3 2 1 0 wdrun por wd1 wd0 wdif wt rf ewrst wdclr mnemonic: wdcon address: d8h N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 39 - revision a02 bit name function 7 wd r un 0: the wat c h dog is stopp e d. 1: the watchdog is running. 6 - reserved. 5 wd1 4 wd0 watchdo g timer time -out select bits. these bits det ermin e the time-o ut perio d of the watch d og timer. the reset time -ou t period is 5 1 2 clo c ks lon g er than the watchdo g time-out. wd1 w d0 interrupt time-out res e t time-out 0 0 2 17 2 17 + 512 0 1 2 20 2 20 + 512 1 0 2 23 2 23 + 512 1 1 2 26 2 26 + 512 3 wdif watchdo g timer interrupt flag 0: if the interrupt is not en abled, then t h is bit indi cat es that the time-o ut perio d has el ap sed. this bit mu st be cle a re d by softwa r e. 1: if the watchdog interrup t is enabled, hard w a r e will set this bit to indicate that the watchdo g interru pt has occurre d . 2 wt rf watchdo g timer reset flag 1: hardware will set this bi t when th e watchd og time r cau s e s a re set. software can rea d it b u t must cl ea r it manually. a powe r-fail reset will also clea r the bit. this bit h e lps soft ware in determi nin g the cause of a reset. if ewrst = 0, the watchdog timer will have no affect on this bit. 1 ewrst 0: disa ble watchd og time r re set. 1: enable watchdog timer reset. 0 wdclr re set wat c h dog time r this bit helps in putting th e watch dog timer into a kn ow state. it a l so help s in resetting the watchdog timer before a time-out occurs. failing to set the ewrst befo r e time-out wi ll cause an interru pt, if ewdi (eie.4) is set, and 512 clo c ks after that a watchd og timer rese t will be generated if ewrst is set. thi s bit is self-clea r ing by ha rd ware. the wdco n sfr is set to 0x00000 0b on a re set. wtrf (wdco n.2) is set to a 1 on a wat c hd og timer res e t, but to a 0 on power on/down resets . wt rf (wdco n . 2 ) is not alte red by an external reset. ewrs t (wdcon.1 ) is set to 0 on a powe r-o n reset, re set p i n reset, and watch do g ti mer reset. all the bits in this sfr have unrestricted r ead access. wdrun, wd0, wd1, ewrst, wdif and wdclr require timed access procedure to writ e. the remaining bits have unrestricted write accesses. please refer ta register description. N79E825A/824a/823a/822a data sheet - 40 - ta reg c7 h wd co n reg d8 h mov ta, #aah ; to access p r otecte d bits mov ta, #55h setb wdco n.0 ; reset watch dog timer orl wdco n, #00 1100 00b ; select 26 bits wat c hd og timer mov ta, #aah mov ta, #55h orl wdco n, #00 0000 10b ; enable watchdog pwmp co u n ter l o w bits register bit: 7 6 5 4 3 2 1 0 pwmp.7 pwmp.6 pwmp.5 pwp.4 pwmp.3 pwmp.2 pwmp.1 pwmp.1 mnemo n ic: pwmpl addre s s: d9h bit name function 7~0 pwmp.[7:0] pwm counter low bits register. pwm0 low bits register bit: 7 6 5 4 3 2 1 0 pwm0.7 pwm0.6 pwm0 .5 pwm0.4 pwm0.3 pw m0.2 pwm0.1 pwm0.1 mnemo n ic: pwm0l addre s s: dah bit name function 7~0 pwm0.[7:0] pwm 0 low bits register. pwm1 low bits register bit: 7 6 5 4 3 2 1 0 pwm1.7 pwm1.6 pwm1 .5 pwm1.4 pwm1.3 pw m1.2 pwm1.1 pwm1.0 mnemo n ic: pwm1l addre s s: dbh bit name function 7~0 pwm1.[7:0] pwm 1 low bits register. pwm co nt rol register 1 bit: 7 6 5 4 3 2 1 0 pwmrun loa d cf clrpwm pwm3i pwm2i pwm1i pwm0i mnemonic: pwmcon1 address: dch N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 41 - revi si on a0 2 bit name function 7 pw mrun 0: the pwm i s not ru nning. 1: the pwm counter is running. 6 load 0: the regi st ers valu e of pwmp and pwmn are n ever load ed to cou nter an d comp arator registe r s. 1: the p w m p and p w mn regi sters lo a d value to co unter and co mpare regist ers at the counte r unde rflow. this bit is auto cleare d by hardware at next clock cy cle. 5 cf 0: the 10-bit cou n ter do wn count is n o t unde rflow. 1: the 10-bit cou n ter do wn count is u n d e rflow. thi s b i t is software clea r. 4 cl rpwm 1: clear 10-bit pwm counter to 000 h. this bit is auto cleared by hardware. 3 pwm3i 0: pwm3 out is non -inve r te d. 1: pwm3 output is inverted. 2 pwm2i 0: pwm2 out is non -inve r te d. 1: pwm2 output is inverted. 1 pwm1i 0: pwm1 out is non -inve r te d. 1: pwm1 output is inverted. 0 pwm0i 0: pwm0 out is non -inve r te d. 1: pwm0 output is inverted. pwm2 low bits register bit: 7 6 5 4 3 2 1 0 pwm2.7 pwm2.6 pwm2 .5 pwm2.4 pwm2.3 pw m2.2 pwm2.1 pwm2.0 mnemo n ic: pwm2l addre s s: ddh bit name function 7~0 pwm2.[7:0] pwm 2 low bits register. pwm3 low bits register bit: 7 6 5 4 3 2 1 0 pwm3.7 pwm3.6 pwm3 .5 pwm3.4 pwm3.3 pw m3.2 pwm3.1 pwm3.0 mnemo n ic: pwm3l addre s s: deh bit name function 7~0 pwm3.[7:0] pwm 3 low bits register. pwm co nt rol register 2 bit: 7 6 5 4 3 2 1 0 bkch bkps bpen bken pwm3b pwm2b pwm1b pwm0b mnemonic: pwmcon2 address: dfh N79E825A/824a/823a/822a data sheet - 42 - bit name function 7 bkch see the below table, when bken is set. 6 bkps 0: brake i s asserte d if p0.2 is low. 1: brake i s asserte d if p0.2 is high 5 bpen see the below table, when bken is set. 4 bken 0: the bra k e is never a s se rted. 1: the bra k e is ena bled, a nd se e the be low table. 3 pwm3b 0: the pwm3 output is low, when brake is asse rted. 1: the pwm3 output is high, when brake is asserted. 2 pwm2b 0: the pwm2 output is low, when brake is asse rted. 1: the pwm2 output is high, when brake is asserted. 1 pwm1b 0: the pwm1 output is low, when brake is asse rted. 1: the pwm1 output is high, when brake is asserted. 0 pwm0b 0: the pwm0 output is low, when brake is asse rted. 1: the pwm0 output is high, when brake is asserted. brak e con dition table : bpen bkch brake condition 0 0 brake on (so ftware b r a k e and keepi ng bra k e ) . software brake condition. when acti ve (bpen=bkch=0, and bken=1), pwm output follows pwmnb setting. this br ake has no effect on pwmrun bit, therefore, internal pwm generator continue s to run. when the brake is released, the state of pwm output depends on the cu rrent state of pwm generator output during the release. 0 1 brake on, when pwm i s not runni ng (p wmrun=0), the pwm output con d itio n follows pwmnb s e tting. when the brak e is released (by dis abl ing bken = 0), the pwm output res u mes to the state when pwm generator stop running prior to enabling the brake. brake off, when pwm is running (pwmrun=1). 1 0 brake on, wh en bra k e pin asserte d . external pin brake condition. when active (by external pin), pwm output follows pwmnb setting, pwmrun will be cleared by hardware, and bkf flag will be set. when the brake is released (by de-asserting the external pin and disabling bken = 0), the pwm output resumes to the state of the pwm generator output prior to the brake. 1 1 no any active. accumulator bit: 7 6 5 4 3 2 1 0 acc.7 acc.6 acc.5 acc.4 acc.3 acc.2 acc.1 acc.0 mnemonic: acc address: e0h N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 43 - revi si on a0 2 bit name function 7-0 acc.[7:0] the a or acc register is the standard 8052 accumulator ad c c ont r ol registe r bit: 7 6 5 4 3 2 1 0 adc.1 adc.0 adce x adci adcs rcclk aadr1 aadr0 mnemo n ic: adcco n addre s s: e1h bit name function 7 adc.1 the adc conversion result. 6 adc.0 the adc conversion result. 5 adcex enable stadc-tri gge red conversion 0: conversio n can o n ly be started by software (i.e., by s e tting adcs). 1: conversion can be started by softwar e or by a rising edge on stadc (pin p1.4). 4 adci adc interrupt flag: this flag is set when the result of an a/d conversion is ready . this generates an adc interrupt, if it is enabled. the flag ma y be cleared by the isr. while this flag is 1, the adc cannot start a new conver sion. adci can not be set by software. 3 adcs adc start and status: set this bit to star t an a/d conversio n. it may also be set by stadc if adcex is 1. this sig nal re mains hig h while the adc is busy and is reset right after adci is s e t. note s: 1. it is recomm ende d to cle a r adci befo re adcs i s s e t. howev e r, if adci is clea red an d adcs is set at the same time, a new a/d conve r sion may start on the sam e cha nnel. 2. software clearing of adcs will abort conversion in progress. 3. adc cannot start a new conversion while adcs or adci is high. 2 rc clk 0: the cpu clock is u s ed a s adc clo ck. 1: the internal rc clock is used as adc clock. 1 aadr1 the adc input select. see table below. 0 aadr0 the adc input select. see table below. the adci an d adcs con t rol the adc conv ersion as belo w : adci adc s adc status 0 0 adc not busy; a conversion can be started. 0 1 adc busy; start of a new conversion is blocked. 1 0 conversion completed; start of a new conversion requires adci = 0. 1 1 this is an internal temporary state that user can ignore it. N79E825A/824a/823a/822a data sheet - 44 - aadr1, aadr0: adc analog i nput channel select bits: these bits can only be changed when adci and adcs are both zero. aadr1 aadr0 sel ected a nalog in pu t chann el 0 0 ad0 (p0.3) 0 1 ad1 (p0.4) 1 0 ad2 (p0.5) 1 1 ad3 (p0.6) ad c c onve r ter resu lt high re gister bit: 7 6 5 4 3 2 1 0 adc.9 adc.8 adc.7 adc.6 adc.5 adc.4 adc.3 adc.2 mnemonic: adch address: e2h bit name function 7-0 adc.[9:2] the adc conversion result. interrupt enable register 1 bit: 7 6 5 4 3 2 1 0 - - epwm ewdi ec2 ec1 ekb ei2c mnemo n ic: eie address: e8h bit name function 7 - reserved. 6 - reserved. 5 epwm 0: disa ble pwm interrupt whe n externa l brake pin was brake. 1: enable pwm interrupt when ex ternal brake pin was brake. 4 ewdi 0: disa ble watchd og time r interrupt. 1: enable watchdog timer interrupt. 3 ec2 0: disa ble co mparator 2 in terru pt. 1: enable comparator 2 interrupt. 2 ec1 0: disa ble co mparator 1 in terru pt. 1: enable comparator 1 interrupt. 1 ekb 0: disable keypad interrupt. 1: enable keypad interrupt. 0 ei2c 0: disa ble i2 c interrupt. 1: enable i2c interrupt. N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 45 - revision a02 b register bit: 7 6 5 4 3 2 1 0 b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 mnemo n ic: b ad d r ess : f 0 h bit name function 7-0 b.[7:0] the b register is the standard 8052 register that serves as a second accumulator. port 0 digi tal inp u t disable bit: 7 6 5 4 3 2 1 0 p0id.7 p0id.6 p0id .5 p0id.4 p0id.3 p0id.2 p0id.1 p0id.0 mnemo n ic: p0id addre s s: f6h bit name function 7~ 0 p0id.[7:0] enable/di sa b l e port 0 digital inputs. 0: enable port 0 digital inputs. 1: disable port 0 digital inputs. interrupt high p r iority 1 bit: 7 6 5 4 3 2 1 0 - - ppwmh pwdih pc2h pc1h pkbh pi2h mnemo n ic: ip1h addre s s: f7h bit name function 7 - reserved. 6 - reserved. 5 ppwmh 1: to set interrupt high priority of pwm?s brake is highest priority level. 4 pwdih 1: to set interrupt high priority of watchdog is highest priority level. 3 pc2h 1: to set interrupt high priority of comparator 2 is highest priority level. 2 pc1h 1: to set interrupt high priority of comparator 1 is highest priority level. 1 pkbh 1: to set interrupt high priority of keypad is highest priority level. 0 pi2h 1: to set interrupt high priority of i2c is highest priority level. N79E825A/824a/823a/822a data sheet - 46 - extended i n terrupt priority bit: 7 6 5 4 3 2 1 0 - - ppwm pwdi pc2 pc1 pkb pi2 mnemo n ic: ip1 addre s s: f8h bit name function 7 - reserved. 6 - reserved. 5 ppwm 1: to set interrupt priority of pwm? s external brake is higher priority level. 4 pwdi 1: to set interrupt priority of watchdog is higher priority level. 3 pc2 1: to set interrupt priority of comparator 2 is higher priority level. 2 pc1 1: to set interrupt priority of comparator 1 is higher priority level. 1 pkb 1: to set interrupt priority of keypad is higher priority level. 0 pi2 1: to set interrupt priority of i2c is higher priority level. N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 47 - revision a02 9 instruction set the n79e 82 5 serie s execute all the instruction s of the standa rd 8 052 family. t he operation s of these instru ction s , as well a s their effect s on flag and statu s bits, a r e ex actly the sam e . however, the timing of these in struction s is different in two ways. firstly, the machine cycl e i s four clo ck p eri od s, while the stand ard - 8 05 1/52 ma chine cycle is twel ve clock pe ri ods. se condl y, it can fe tch only once p e r machine cycle (i.e., four clo c ks p e r fetch), while the stand ard 8051/5 2 can fetch twice p e r ma chin e cycle (i.e., s i x c l oc ks per fetc h). the timing differences create an advantage for the n79e82 5 seri es. the r e is only one fetch per machi ne cycl e, so the number of machine cycl es i s usu ally equ al to the number of opera nds in the instru ction. (jumps a nd cal l s do re quire an addition al cycle to cal c u l ate the new address.) as a result, the n7 9e82 5 se rie s red uce s the nu mber of du mmy fetche s and wa sted cycle s , a n d therefo r e improve s ove r all efficien cy, compa r e d to the stand ard 8051/5 2 . op-cod e hex cod e bytes n79e825 se rie s machin e cycl e n79e825 se rie s clock cycl es 8032 clock cycl es n79e825 s e ries vs . 8032 speed ratio nop 00 1 1 4 12 3 add a, r0 28 1 1 4 12 3 add a, r1 29 1 1 4 12 3 add a, r2 2a 1 1 4 12 3 add a, r3 2b 1 1 4 12 3 add a, r4 2c 1 1 4 12 3 add a, r5 2d 1 1 4 12 3 add a, r6 2e 1 1 4 12 3 add a, r7 2f 1 1 4 12 3 add a, @r0 26 1 1 4 12 3 add a, @r1 27 1 1 4 12 3 add a, direct 25 2 2 8 12 1.5 add a, #data 24 2 2 8 12 1.5 addc a, r0 38 1 1 4 12 3 addc a, r1 39 1 1 4 12 3 addc a, r2 3a 1 1 4 12 3 addc a, r3 3b 1 1 4 12 3 addc a, r4 3c 1 1 4 12 3 addc a, r5 3d 1 1 4 12 3 addc a, r6 3e 1 1 4 12 3 addc a, r7 3f 1 1 4 12 3 addc a, @r0 36 1 1 4 12 3 N79E825A/824a/823a/822a data sheet - 48 - addc a, @r1 37 1 1 4 12 3 N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 49 - revision a02 continued op-cod e hex cod e bytes n79e825 se rie s machin e cycl e n79e825 se rie s clock cycl es 8032 clock cycl es n79e825 s e ries vs . 8032 speed ratio addc a, direct 35 2 2 8 12 1.5 addc a, #dat a 34 2 2 8 12 1.5 subb a, r0 98 1 1 4 12 3 subb a, r1 99 1 1 4 12 3 subb a, r2 9a 1 1 4 12 3 subb a, r3 9b 1 1 4 12 3 subb a, r4 9c 1 1 4 12 3 subb a, r5 9d 1 1 4 12 3 subb a, r6 9e 1 1 4 12 3 subb a, r7 9f 1 1 4 12 3 subb a, @r0 96 1 1 4 12 3 subb a, @r1 97 1 1 4 12 3 subb a, direct 95 2 2 8 12 1.5 subb a, #data 94 2 2 8 12 1.5 inc a 04 1 1 4 12 3 inc r0 08 1 1 4 12 3 inc r1 09 1 1 4 12 3 inc r2 0a 1 1 4 12 3 inc r3 0b 1 1 4 12 3 inc r4 0c 1 1 4 12 3 inc r5 0d 1 1 4 12 3 inc r6 0e 1 1 4 12 3 inc r7 0f 1 1 4 12 3 inc @r0 06 1 1 4 12 3 inc @r1 07 1 1 4 12 3 inc direct 05 2 2 8 12 1.5 inc dpt r a3 1 2 8 24 3 dec a 14 1 1 4 12 3 dec r0 18 1 1 4 12 3 dec r1 19 1 1 4 12 3 dec r2 1a 1 1 4 12 3 dec r3 1b 1 1 4 12 3 N79E825A/824a/823a/822a data sheet - 50 - continued op-cod e hex cod e bytes n79e825 se rie s machin e cycl e n79e825 se rie s clock cycl es 8032 clock cycl es n79e825 s e ries vs . 8032 speed ratio dec r4 1c 1 1 4 12 3 dec r5 1d 1 1 4 12 3 dec r6 1e 1 1 4 12 3 dec r7 1f 1 1 4 12 3 dec @r0 16 1 1 4 12 3 dec @r1 17 1 1 4 12 3 dec direct 15 2 2 8 12 1.5 mul ab a4 1 5 20 48 2.4 div ab 84 1 5 20 48 2.4 da a d4 1 1 4 12 3 anl a, r0 58 1 1 4 12 3 anl a, r1 59 1 1 4 12 3 anl a, r2 5a 1 1 4 12 3 anl a, r3 5b 1 1 4 12 3 anl a, r4 5c 1 1 4 12 3 anl a, r5 5d 1 1 4 12 3 anl a, r6 5e 1 1 4 12 3 anl a, r7 5f 1 1 4 12 3 anl a, @r0 56 1 1 4 12 3 anl a, @r1 57 1 1 4 12 3 anl a, direct 55 2 2 8 12 1.5 anl a, #data 54 2 2 8 12 1.5 anl dir e ct, a 52 2 2 8 12 1.5 anl dir e ct, #data 53 3 3 12 24 2 orl a, r0 48 1 1 4 12 3 orl a, r1 49 1 1 4 12 3 orl a, r2 4a 1 1 4 12 3 orl a, r3 4b 1 1 4 12 3 orl a, r4 4c 1 1 4 12 3 orl a, r5 4d 1 1 4 12 3 orl a, r6 4e 1 1 4 12 3 orl a, r7 4f 1 1 4 12 3 N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 51 - revision a02 continued op-cod e hex cod e bytes n79e825 se rie s machin e cycl e n79e825 se rie s clock cycl es 8032 clock cycl es n79e825 s e ries vs . 8032 speed ratio orl a, @r0 46 1 1 4 12 3 orl a, @r1 47 1 1 4 12 3 orl a, direct 45 2 2 8 12 1.5 orl a, #data 44 2 2 8 12 1.5 orl direct, a 42 2 2 8 12 1.5 orl direct, #d ata 43 3 3 12 24 2 xr l a, r0 68 1 1 4 12 3 xr l a, r1 69 1 1 4 12 3 xr l a, r2 6a 1 1 4 12 3 xr l a, r3 6b 1 1 4 12 3 xr l a, r4 6c 1 1 4 12 3 xr l a, r5 6d 1 1 4 12 3 xr l a, r6 6e 1 1 4 12 3 xr l a, r7 6f 1 1 4 12 3 xr l a, @r0 66 1 1 4 12 3 xr l a, @r1 67 1 1 4 12 3 xr l a, direct 65 2 2 8 12 1.5 xr l a, #data 64 2 2 8 12 1.5 xr l dir e ct, a 62 2 2 8 12 1.5 xr l dir e ct, #data 63 3 3 12 24 2 clr a e4 1 1 4 12 3 cpl a f 4 1 1 4 12 3 rl a 23 1 1 4 12 3 rlc a 33 1 1 4 12 3 rr a 03 1 1 4 12 3 rrc a 13 1 1 4 12 3 sw ap a c4 1 1 4 12 3 mov a, r0 e8 1 1 4 12 3 mov a, r1 e9 1 1 4 12 3 mov a, r2 ea 1 1 4 12 3 mov a, r3 eb 1 1 4 12 3 mov a, r4 ec 1 1 4 12 3 N79E825A/824a/823a/822a data sheet - 52 - continued op-cod e hex cod e bytes n79e825 se rie s machin e cycl e n79e825 se rie s clock cycl es 8032 clock cycl es n79e825 s e ries vs . 8032 speed ratio mov a, r5 ed 1 1 4 12 3 mov a, r6 ee 1 1 4 12 3 mov a, r7 ef 1 1 4 12 3 mov a, @r0 e6 1 1 4 12 3 mov a, @r1 e7 1 1 4 12 3 mov a, direct e5 2 2 8 12 1.5 mov a, #data 74 2 2 8 12 1.5 mov r0, a f 8 1 1 4 12 3 mov r1, a f 9 1 1 4 12 3 mov r2, a f a 1 1 4 12 3 mov r3, a f b 1 1 4 12 3 mov r4, a f c 1 1 4 12 3 mov r5, a f d 1 1 4 12 3 mov r6, a f e 1 1 4 12 3 mov r7, a f f 1 1 4 12 3 mov r0, direc t a8 2 2 8 12 1.5 mov r1, direc t a9 2 2 8 12 1.5 mov r2, direc t aa 2 2 8 12 1.5 mov r3, direc t ab 2 2 8 12 1.5 mov r4, direc t ac 2 2 8 12 1.5 mov r5, direc t ad 2 2 8 12 1.5 mov r6, direc t ae 2 2 8 12 1.5 mov r7, direc t af 2 2 8 12 1.5 mov r0, #data 78 2 2 8 12 1.5 mov r1, #data 79 2 2 8 12 1.5 mov r2, #data 7a 2 2 8 12 1.5 mov r3, #data 7b 2 2 8 12 1.5 mov r4, #data 7c 2 2 8 12 1.5 mov r5, #data 7d 2 2 8 12 1.5 mov r6, #data 7e 2 2 8 12 1.5 mov r7, #data 7f 2 2 8 12 1.5 mov @r0, a f 6 1 1 4 12 3 N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 53 - revision a02 continued op-cod e hex cod e bytes n79e825 se rie s machin e cycl e n79e825 se rie s clock cycl es 8032 clock cycl es n79e825 s e ries vs . 8032 speed ratio mov @r1, a f 7 1 1 4 12 3 mov @r0, direct a6 2 2 8 12 1.5 mov @r1, direct a7 2 2 8 12 1.5 mov @r0, #d ata 76 2 2 8 12 1.5 mov @r1, #d ata 77 2 2 8 12 1.5 mov direct, a f 5 2 2 8 12 1.5 mov direct, r0 88 2 2 8 12 1.5 mov direct, r1 89 2 2 8 12 1.5 mov direct, r2 8a 2 2 8 12 1.5 mov direct, r3 8b 2 2 8 12 1.5 mov direct, r4 8c 2 2 8 12 1.5 mov direct, r5 8d 2 2 8 12 1.5 mov direct, r6 8e 2 2 8 12 1.5 mov direct, r7 8f 2 2 8 12 1.5 mov direct, @r0 86 2 2 8 12 1.5 mov direct, @r1 87 2 2 8 12 1.5 mov direct, direct 85 3 3 12 24 2 mov direct, #data 75 3 3 12 24 2 mov dpt r , # data 16 90 3 3 12 24 2 movc a, @a+dpt r 93 1 2 8 24 3 movc a, @a+pc 83 1 2 8 24 3 movx a, @r0 e2 1 2 - 9 8 - 36 24 3 - 0.66 movx a, @r1 e3 1 2 - 9 8 - 36 24 3 - 0.66 movx a, @dpt r e0 1 2 - 9 8 - 36 24 3 - 0.66 movx @r0, a f 2 1 2 - 9 8 - 36 24 3 - 0.66 movx @r1, a f 3 1 2 - 9 8 - 36 24 3 - 0.66 movx @dpt r, a f 0 1 2 - 9 8 - 36 24 3 - 0.66 push dir e ct c0 2 2 8 24 3 pop direct d0 2 2 8 24 3 xc h a, r0 c8 1 1 4 12 3 xc h a, r1 c9 1 1 4 12 3 N79E825A/824a/823a/822a data sheet - 54 - continued op-cod e hex cod e bytes n79e825 se rie s machin e cycl e n79e825 se rie s clock cycl es 8032 clock cycl es n79e825 s e ries vs . 8032 speed ratio xc h a, r2 ca 1 1 4 12 3 xc h a, r3 cb 1 1 4 12 3 xc h a, r4 cc 1 1 4 12 3 xc h a, r5 cd 1 1 4 12 3 xc h a, r6 ce 1 1 4 12 3 xc h a, r7 cf 1 1 4 12 3 xc h a, @r0 c6 1 1 4 12 3 xc h a, @r1 c7 1 1 4 12 3 xc hd a, @r0 d6 1 1 4 12 3 xc hd a, @r1 d7 1 1 4 12 3 xc h a, direct c5 2 2 8 12 1.5 clr c c3 1 1 4 12 3 clr bit c2 2 2 8 12 1.5 set b c d3 1 1 4 12 3 set b bit d2 2 2 8 12 1.5 cpl c b3 1 1 4 12 3 cpl bit b2 2 2 8 12 1.5 anl c, bit 82 2 2 8 24 3 anl c, /bit b0 2 2 6 24 3 orl c, bit 72 2 2 8 24 3 orl c, /bit a0 2 2 6 24 3 mov c, bit a2 2 2 8 12 1.5 mov bit, c 92 2 2 8 24 3 acall a ddr 11 71, 91, b1, 11, 31, 51, d1, f1 2 3 12 24 2 lcal l ad dr16 12 3 4 16 24 1.5 ret 22 1 2 8 24 3 ret i 32 1 2 8 24 3 ajmp addr1 1 01, 21, 41, 61, 81, a1, c1, e1 2 3 12 24 2 ljmp addr 16 02 3 4 16 24 1.5 jmp @a+ dpt r 73 1 2 6 24 3 N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 55 - revision a02 continued op-cod e hex cod e bytes n79e825 se rie s machin e cycl e n79e825 se rie s clock cycl es 8032 clock cycl es n79e825 s e ries vs . 8032 speed ratio sjmp rel 80 2 3 12 24 2 jz rel 60 2 3 12 24 2 jnz rel 70 2 3 12 24 2 jc rel 40 2 3 12 24 2 jnc rel 50 2 3 12 24 2 jb bit, rel 20 3 4 16 24 1.5 jnb bit, rel 30 3 4 16 24 1.5 jbc bit, rel 10 3 4 16 24 1.5 cjne a, direct , rel b5 3 4 16 24 1.5 cjne a, #data , rel b4 3 4 16 24 1.5 cjne @r0, # data, rel b6 3 4 16 24 1.5 cjne @r1, # data, rel b7 3 4 16 24 1.5 cjne r0, #d ata, rel b8 3 4 16 24 1.5 cjne r1, #d ata, rel b9 3 4 16 24 1.5 cjne r2, #d ata, rel ba 3 4 16 24 1.5 cjne r3, #d ata, rel bb 3 4 16 24 1.5 cjne r4, #d ata, rel bc 3 4 16 24 1.5 cjne r5, #d ata, rel bd 3 4 16 24 1.5 cjne r6, #d ata, rel be 3 4 16 24 1.5 cjne r7, #d ata, rel bf 3 4 16 24 1.5 djnz r0, rel d8 2 3 12 24 2 djnz r1, rel d9 2 3 12 24 2 djnz r5, rel dd 2 3 12 24 2 djnz r2, rel da 2 3 12 24 2 djnz r3, rel db 2 3 12 24 2 djnz r4, rel dc 2 3 12 24 2 djnz r6, rel de 2 3 12 24 2 djnz r7, rel df 2 3 12 24 2 djnz direct, rel d5 3 4 16 24 1.5 table 9-1: instruction set for n79e825/824 N79E825A/824a/823a/822a data sheet - 56 - 9.1 instruction timing this se ction is impo rtant becau se so me appli c atio ns u s e software in structio ns to g ene ra te timing delays. it also provide s m o re informati on about timing differen c e s betwe en th e n79e8 25 serie s and the stand ard 8051/5 2 . in n79e8 25 serie s , ea ch m achi ne cycle i s four clo c k p eriod s lo ng. each clo ck p eriod i s calle d a state, and ea ch ma chin e cycle consi s ts of four states: c1 , c2 c3 an d c4, in order. both clock edg es are use d for internal timing, so the dut y cycle of the clock should b e as close to 50% as possibl e to avoid timing confli cts. the n79e82 5 se ries doe s one op -code fetch per m a chin e cycl e, so, in most instruction s , the numbe r of machine cycles re quire d is equal to the number o f bytes in the instructio n. there a r e 256 available op-c o des . 128 of them ar e s i ngle- c y c l e ins t r u c t ions , so many op-c o des ar e executed in jus t four c l ocks perio d. some of the other op-cod e s are t w o- cy cle i n st ru ct ion s , an d most of the s e h a ve two - byte op- cod es. ho we ver, there are some in struction s that have one -byte instru ct ion s y e t t a ke t w o cy cles t o execute. on e important ex ampl e is the movx instru ction. in the sta n d a rd 805 2, the movx in st ructio n i s al w a ys tw o ma c h in e c y c l es lo ng . ho we ve r , in the n79e8 25 seri es ea ch m achine cy cle is made of only 4 clo ck p eri o ds comp are d to the 12 clo c k pe riod s for the stan dard 8 052. therefore, e v en though t he numbe r of catego rie s has increa sed, each instru ction i s at least 1.5 to 3 times faste r than the sta ndard 805 2 in terms of clo c k peri od s . single cycle c4 c3 c2 c1 cpu clk ale psen ad<7:0> address <15:0> a7-0 address a15-8 data_ in d7-0 figure 9-1: single cycle instruction timing N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 57 - revision a02 instruction fetch c4 c3 c2 c1 op-code address a15-8 address a15-8 ale psen pc ad<7:0> a ddress<15:0> cpu clk operand fetch c4 c3 c2 c1 operand pc+1 figure 9 - 2: t w o c y cles instruction timing operand operand a7-0 a7-0 a7-0 op-code address a15-8 address a15-8 address a15-8 operand fetch operand fetch instruction fetch c2 c3 c4 c2 c3 c4 c4 c3 c2 c1 c1 c1 cpu clk ale psen ad<7:0> a ddress<15:0> figure 9 - 3: th re e c y cles instruction timing N79E825A/824a/823a/822a data sheet - 58 - operand operand operand op-code address a15-8 address a15-8 address a15-8 address a15-8 a7-0 a7-0 a7-0 a7-0 operand fetch operand fetch operand fetch instruction fetch c2 c1 c4 c3 c2 c1 cpu clk ale psen ad<7:0> a ddress<15:0> c4 c3 c2 c1 c4 c3 c2 c1 c4 c3 figure 9 - 4: fou r c y cles instruction timing operand operand operand op-code address a15-8 address a15-8 address a15-8 address a15-8 a7-0 a7-0 a7-0 a7-0 operand fetch operand fetch operand fetch operand fetch instruction fetch c2 c1 c4 c3 c2 c1 cpu clk ale psen ad<7:0> a ddress<15:0> c4 c3 c2 c1 c4 c3 c2 c1 c4 c3 c2 c1 c4 c3 operand a7-0 address a15-8 figure 9-5: five cycles instruction timing N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 59 - revision a02 10 power manageme n t the n79e82 5 se rie s ha s several feat ures that hel p the user to co nt rol the po wer con s umpti on of the device. the s e mode s are discu s sed in the next two section s . 10.1 idle mode the u s e r can put the devi c e into idle mo de by writing 1 to the bit p c on.0. the ins t ruct ion that s e ts the idle bit is the last instru ction t hat will be executed b efore the dev ice goe s into idle mode. in the idl e mode, the clo ck to the cp u is halted, b u t not to t he i n terrupt, tim e r, watch dog timer, i2c, p w m a nd serial p o rt bl ocks. t h is fo rce s the cpu state to b e froze n ; the pro g ram co unte r , the stack pointer, the program status word, the accu mulato r and the othe r registe r s hol d their co nte nts. the port pins hol d the logical st ates they ha d at the time idle wa s act i vated. the idle mod e ca n be termi nat ed in two ways. since the interrupt controlle r is still active, the activation of any enable d interrupt ca n wa ke u p the processo r. this will a u tomatica lly clea r the idl e bit, terminat e the idle m ode, an d the interru pt service routi ne (isr) will be execut ed. after the isr, execution of the program will continue from the instru ction wh ich put the de vice into idle mode. the idle mo de can also be exited by activating th e re set. th e device ca n p ut into re set either by applying a lo w on th e external / r st pi n, a power o n re set con d ition or a watchd og time r reset. th e external re se t pin has to be held low for at leas t two ma chine cycle s i.e. 8 clock peri od s to be recogni ze d a s a valid reset. in the reset condition t he pro g ra m counter i s re set to 0000h and all the sfrs a r e set to the reset condition. since the cloc k is alrea dy runni ng there is no delay and executio n start s immedi ately. in the idle mode, the watch dog timer co ntinue s to run, and if enabled, a time-out will cause a watchdog timer interrupt whi c h will wa ke up the device. the software m u st reset the watchdo g timer in orde r to pree mpt the reset whi c h will occur aft er 512 clo ck perio ds of th e time-out. whe n the n7 9e825 se rie s are exiting from an idl e m ode with a re set, the in stru ction follo win g the on e whi c h put the device into idle mode i s n o t execut ed. so there is n o dang er of u nexpe cted writes. 10.2 po w e r do w n mode the devi c e can be put int o powe r do wn mode by writ ing 1 to bit pcon. 1 . the instru ction th at doe s this will be the last instruct ion to be executed before the device goes into p o wer down mode. in the powe r down mode, all the clo c ks are sto pped an d the device come s to a halt. all activity is completely stopp ed and the powe r co nsum ption is redu ce d to the lowe st possible value. t he port pin s output the values held by their respective sfrs . the n79e825 series will exit the power down mode with a reset or by an external int e rrupt pin enabl ed as l evel detected . an external reset ca n be used to exit the power d o wn state. th e low on /rst pin terminates th e powe r down mode, an d re st art s the clo ck. t he p r og ram execution will re sta r t from 000 0h. in the powe r down mod e, the clo c k is stoppe d, so the watchdog ti mer cann ot b e use d to provide the re set to exit power d o wn mo de wh en it s cl oc k so ur ce is ex t e rnal os c or cry s t a l. the source s that can wa ke up from th e powe r do wn mode a r e ex ternal inte rru p ts, keyb oard interru pt (kbi), bro w no ut reset (b or), and co mpa r ator inte rrupt (cmf 1, cmf 2 ). the n7 9e82 5 seri es can be wa ke n up from the power do wn m o d e by forcing a n external int e rrupt pin activation, p r ovided the correspon ding interrupt is e nable d , whil e the glob al e nable (ea) bi t is set. if these conditi ons are met, then either a low-l e vel or a falling-edg e at external interrupt pin will re-sta rt the oscillato r. the d e vice will then execute the inte rr upt se rvice ro utine for th e corre s p ondin g extern a l interrupt. after the interrupt s e rv ice routine i s co mpleted, the prog ram executio n retu rns to the instru ction after one whi c h put the device into powe r down mod e and contin ues from there. during powe r do wn mode, if aux r 1.lpbov = 1 and aux r 1.bo d = 0, the internal rc clo c k will b e enabl ed N79E825A/824a/823a/822a data sheet - 60 - and he nce sa ve powe r . N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 61 - revision a02 11 res e t conditions the u s e r ha s several ha rd ware related option s for pl acin g the n7 9e825 se rie s into re set co ndition. in gene ral, most regi ster bit s go to their re set value ir respective of the reset co nditi on, but there are a fe w flags who s e state dep end s on the sou r ce of re set. the u s er ca n use th ese flags to dete r mine th e cau s e of re se t using softwa r e. 11.1 source s of rese t 11.1.1 external re set the device sample s the /rst pin every machine cy cle du ring st ate c4. the /rst pin must be held low for at least two machi ne cycle s before the reset circuitry appli e s an internal reset signal. thus, this reset is a syn c hrono us o pe r ation an d re quire s the cl o ck to be runni ng. the devi c e remain s in th e re set state as lo ng a s / r st is l ow a nd re main s l ow u p to two machine cycle s afte r /rst is dea cti v ated. then, the devic e be gins pro gram executio n at 0000 h. the r e are no flags a s so cia t ed with the external re se t, but, si nce the other two re set source s do have fl ags, th e external reset is the cau s e i f those flags are cl ea r. 11.1.2 po w e r-on r eset (por ) the soft ware must cl ear the por flag af ter reading it. otherwise it will not be possi ble to correctly determi ne future reset sou r ce s. if the power fail s, then the device will on ce agai n go into re se t state. whe n the po wer returns to the prope r o peratin g level s , the device will again p erf orm a po we r on re set delay and set the por flag . 11.1.3 watchdog timer reset the watchdo g time r is a f r ee -ru nnin g timer with p r o gramm able ti me-o ut interv als. th e p r og ram m ust clea r the watchd og time r before th e time-o ut interv al is re ached to restart th e cou n t. if th e time-out interval is rea c he d, an inte rru pt flag is set. 512 clo c ks later, if the watchdo g re set is en able d and th e watchdo g ti mer h as not been clea re d, the wat c hd o g timer gen e r ates a reset. the reset co ndition is maintaine d b y the hard w a r e for two ma chin e cycl es , and the wtrf bit in wdcon is set. afterwards, the device b e gins p r og ram executio n at 0000 h. 11.2 r e se t state whe n the device is reset, most regi sters return to th eir initial state. the watch dog timer is disa bled if the reset sou r ce wa s a po wer-o n re set. the port re gi sters are set to ffh, which puts most of the port pins i n a hi gh state. the p r ogra m count er i s set to 0 000h, a nd th e sta ck point er i s re set to 07h. after this, the device remai n s in t he re set state as long a s th e reset con d itions a r e satisfied. re set does not affect th e on-chip ram, however, so ram is pre s e r ved as long as vdd remain s above a ppro x imately 2 v, the minimu m ope rating vo ltage for th e ram. if vdd fall s b e lo w 2 v, the ram co ntent s are also lost. in either ca se, the sta c k pointer i s al ways re set, so t he st ac k con t ent s ar e los t. N79E825A/824a/823a/822a data sheet - 62 - sf r r e s e t val u e sf r nam e re set v a l u e sf r nam e re set v a l u e p0 1111 1111b i2dat xxxx xxxxb sp 0000 0111b i2status 0000 0xxxb dpl 0000 0000b i2timer 0000 0000b dph 0000 0000b i2clk 0000 0000b pcon 00xx 0000b i2con 0000 0000b tcon 0000 0000b i2 addr xxxx xxxxb tmod 0000 0000b ta 1111 1111b tl0 0000 0000b psw 0000 0000b tl1 0000 0000b pwmp1 xxxx xx00b th0 0000 0000b pwm0h xxxx xx00b th1 0000 0000b pwm1h xxxx xx00b ckcon 0000 0000b pw m2h xxxx xx00b p1 1111 xx11b pwm3h xxxx xx00b divm 0000 0000b wdcon 0x00 0000b scon 0000 0000b pwmp0 0000 0000b sbuf xxxx xxxxb pwm0l 0000 0000b p2 xxx xx11b pwm1l 0000 0000b kbi 0000 0000b pwmcon1 0000 0000b auxr1 0000 0000b pwm2l 0000 0000b ie 0000 0000b pwm3l 0000 0000b saddr 0000 0000b pwmcon2 0000 0000b cmp1 0000 0000b pwmcon3 xxxxxxx0b cmp2 0000 0000b acc 0000 0000b p0m1 0000 0000b adccon xx00 0x00b p0m2 0000 0000b adch xxxx xxxxb p1m1 0000 0000b eie xx000 000b p1m2 0000 0000b b 0000 0000b p2m1 0000 0000b p0ids 0000 0000b p2m2 xxxx xx00b iph xx00 0000b ip0h x000 0000b ip1 xx00 0000b ip0 x000 0000b nvmaddr 0000 0000b saden 0000 0000b nvmdat 0000 0000b n v mcon 00xx xxx xb table 11-1: sfr reset value N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 63 - revi si on a0 2 the wdco n sfr bits are set/cle are d in reset conditi on dep endin g on the sou r ce of the reset. extern al res e t wa tchdo g re set po w e r on re set wdco n 0x0x0xx0b 0x0x01x0b 0100 0000b the wdcon sfr is set to a 0x00 0000b on the reset. wt rf (wdcon. 2 ) is set to a 1 on a watchdo g timer re set, but to a 0 on power on/d own re set s . wt rf (wdcon.2 ) is not altered by external re se t. ewrst (wdco n.1 ) is clea red by any reset. software or any reset wi ll clear wdif(wdcon.3) bit. some of the bits in the wdco n sf r (wdrun , wdcl r, ewrst, wdif, wd0 and wd1) h a ve unre s tri c ted read acce ss whi c h req uire d timed acce ss pro c ed ure to write. t he remai ning bits have unre s tri c ted write a c cesse s . please refe r ta regi ster descri ption. N79E825A/824a/823a/822a data sheet - 64 - system stop system normal run wdg stop wdg normal run 512 watchdog timer clocks crystal 6553 6 clo c k s internal rc 2 56 c l ocks crystal 65536 clocks internal rc 256 clocks v bo3.8 (bor enable) v bo 3. 8 (b or enabl e) v bo 3. 8 2 watchdog timer clocks figure 11-1: internal reset and vdd monitor timing diagram N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 65 - revi si on a0 2 system stop system normal run 0.3vdd crystal 65536 clocks internal rc 256 clocks crystal 65536 clocks internal rc 2 56 cl o c ks system within power down mode system not in power down mode at least 4 clocks 0.7vdd v bo 3 .8 (b or e n a bl e ) figure 11-2: external reset timing diagram N79E825A/824a/823a/822a data sheet - 66 - 12 interrup ts the n79e 82 5 serie s have four priority level interru pt s stru cture wi th 13 interrup t sources. ea ch of the interrupt sou r ce s has an individual prio rity bit, fl ag, interrupt vector and enabl e bit. in addition, the interrupts can be globally e nable d or di sabled. 12.1 interrupt s ources the extern al interru pts int0 and int1 can b e eit her edg e trig gere d o r leve l trigge red, d epen ding on bits it0 and it1. the bits ie0 and ie1 in the tco n re giste r are the flags whi c h a r e ch ecked to gene rate the interrupt. in the edg e trig gere d mo de, the intx inp u ts a r e samp led in eve r y machi n e cycle. if the sample i s hi gh in one cy cle and lo w in th e next, then a high to lo w tran sition i s detecte d and the interrupts requ est flag iex in tco n is set. the flag bit reque sts th e interru pt. since the external inte rrupts are sa mpled eve r y machi ne cycl e, they have to be held hi g h or lo w for a t least one compl e te ma chin e cycle. the iex flag is automati c all y cleare d wh en the servi c e routine is called. if th e level triggere d mode is sel ected, then the requ estin g s ource ha s to hold the pin low till the in terru pt is servi c ed. the iex flag will not be cleared by the hardware on entering the service routine. if the interrupt co ntinue s to be held low even after the se rv ice ro utine is compl eted, then the pro c e s sor m ay ackno w le dge anothe r interrupt requ est from the sam e sou r ce. the time r 0 and 1 interru p ts are ge ne rated by the tf0 and tf1 flags. these flags are se t by the overflow in th e timer 0 an d timer 1. the tf0 and tf 1 flags are au tomatically cl eare d by the hard w a r e whe n the timer interrupt is servi c ed. the watchd og timer ca n be used a s a system monitor o r a simpl e timer. in eith er ca se, whe n the time-out count is reach ed, the watchdo g timer interrupt flag wdif (wdcon. 3 ) i s set. if the interru pt is ena bled by t he e nable bit eie.4, then an interrupt will o c cur. the se rial bl ock can g ene rate inte rrupt on rece pti on or tra nsmissi on. the r e a r e two inte rru pt sou r ce s from the seri al block, whi c h are o btaine d by the ri and ti bits in the sco n sf r. the s e bits are no t automatically cleared by the hardw are, and the user will have to clear these bits by software. all the bits that generate interrupt s ca n be set or reset by software, and t hereby softwa r e initiated interrupts can be gene rate d. each of the individual in terru pts can be ena bled o r disa bled by setting or clea ring a bit in the ie sfr. ie also has a gl obal enable/di sa b l e bit ea, which can be cl eare d to disa ble all interrupts. the adc can gene rate i nterrupt after fi nish ed adc conv e r ter. t h ere i s o ne int e rrupt sou r ce , which i s obtaine d by the adci bit in the adccon sfr. thi s bit is not au tomatically cl eare d by the hard w a r e, and the u s er will have to cl ear this bit u s ing software. the two com parato r s can gene rate inte rru pt after co mparator out put ha s toggl e occu rs by cmf1 and cmf2. the s e bits are not automatically clea red by th e hard w a r e, and the user will have to cl ear the s e bits usi ng software. the i2c funct i on can gen erate interru pt, if ei2c and ea bits are enabled, whe n si flag is set due to a new i2 c statu s co de is g e n e rated, si flag is gen er ate d by hard w a r e and mu st be clea red by softwa r e. the pwm fu nction can g enerate interrupt by bkf flag, after exte rnal b r a k e pi n has bra k e occurre d. this bit will be cleared by software. the inte rru pt flags a r e sampled every machin e cycle. in the same ma chi ne cy cle, th e sam p led interrupts a r e polled an d their p r io rity is resolved. if certai n condit i ons a r e met then the ha rd ware will execute an internally generated lcal l instruction whi c h will vector the process to the a ppropri ate interrupt vect or add re ss. the co ndition s for gene ratin g the lcall are; 1. an interrup t of equal or h igher p r io rity is not cu rrent l y being se rviced. 2. the cu rren t polling cycl e is the last m achi ne cy cle of the instru ct ion cu rrently being exe c ut e. 3. the current instruction does not involve a write to ie, eie, ip0, ip0h, ip1 or iph1 registers and is N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 67 - revision a02 not a reti. if any of these conditio n s are not met, then the lcall will not be gen erate d . the polling cycle i s repe ated eve r y machine cycle, with the interrupt s sa mp led in the same ma chin e cycle. if an interrupt flag is active in one cy cle but not re spo nded to, and is not active whe n the abo ve con dition s are met, the denied int errupt will not be servi c ed. this me ans t hat active interrupts a r e n o t rememb ered; every polling cycle i s ne w. the p r o c e s sor respond s to a valid interrupt by ex ecutin g an l c all in struction to the a ppro p ri ate servi c e routi ne. thi s may or may n o t clea r the fla g whi c h ca u s ed th e inte rrupt. in case of timer interrupts, th e tf0 or tf 1 flags are cleare d by hardware whe n ever the pro c e s sor vecto r s to the approp riate timer servi c e routine. in ca se of external interrupts, int0 and int1 , the flags are clea re d only if they are edge trigge red. in case of serial in terrupts, the flags are not clea red by hard w are. the watchdo g timer interrupt flag wdif has to be cle ared by soft ware. the h ard wa re lca ll behave s exactly like the softwa r e l c all in stru ct ion. this in struction save s the progr am cou nter cont ents onto the stack, b u t does n o t save the pro g ram statu s wo rd psw. the pc is re loade d with the vecto r address of that interrupt which cau s ed t he lcal l. t hese add re ss of vector for the different sou r ce s are as follows: v e ctor locations for inte rrupt s o urces sour ce vector ad dress s our ce vector ad dress external interrupt 0 0003h timer 0 overflow 000bh external interrupt 1 0013h timer 1 overflow 001bh serial port 0023h brownout interrupt 002bh i2c interrupt 0033h kbi interrupt 003bh comparator 2 interrupt 0043h - 004bh watchdog timer 0053h adc interrupt 005bh comparator 1 interrupt 0063h - 006bh pwm brake interrupt 0073h - 007bh table 12 -1: vector lo catio n s for interrupt source s execution co ntinue s from the vect ored address till a n reti instru cti on is executed. on exe c ution of the reti instructio n the pr oce s sor p op s the stack an d loads the p c with the co ntents at the top of the stack. the user must take care that the status of the stac k is re sto r ed to what it wa s after the hard w a r e lcall, if the executio n is return to the interr upted progra m . the processo r doe s not notice a nything if the sta ck co n t ents a r e mo dified an d wil l pro c ee d wi t h execution f r om the add ress put b a ck into pc. note that a ret inst ru ction wo uld pe rform exactly the sam e proce s s as a re ti instruct ion, but it woul d not inform the interrupt co ntroll er that the interru pt servi c e routine i s compl eted, a nd woul d leave the controller still thinking that the servi c e rout ine is underway. N79E825A/824a/823a/822a data sheet - 68 - 12.2 priority le vel struc tu r e the n79e8 2 5 se rie s u s e s a four prio rit y level in terrupt structu r e (high e st, hig h , low an d lo west) and sup port s up t o 13 interrupt sou r ces. th e interrupt so urces ca n be individually set to either hi gh or lo w levels. natu rally, a higher prio rity interrupt can not b e interrupted by a lower p r i o rity interru pt. howeve r there exists a pre-d e fined hiera r chy among st the inte rru pts themse lves. this hie r archy com e s into play whe n the inte rru pt co ntroll er ha s to re solve simult a n eou s re que st s havin g the same pri ority level. this hiera r chy is defined as t able b elow. this all ows great flexibilit y in controlli ng an d han d ling many int e rr upt so ur ce s. priorit y bi t s ipxh ipx interrupt priority level 0 0 level 0 (lowest priority) 0 1 level 1 1 0 level 2 1 1 level 3 (highest priority) table 12 -2: f our-level interrupt pri o rity each inte rru pt source ca n be individu ally prog ram m ed to one of four prio rity levels by setting o r clea ring bit s i n the ip0, ip0h, ip1, and ip1h regi ste r s. an interrup t service r outi ne in progress ca n be interrupted b y a higher pri o rity interrupt , but not by a nother inte rru pt of the same or lowe r pri ority. the highe st prio ri ty interrupt service can no t be inte rru p t ed by any other inte rru pt sou r ce. s o , if two requ est s of different prio rity levels are receive d simu ltaneou sly, the requ est of highe r prio rity level is servi c ed. if reque sts o f the sa me prio rity level are re ceive d sim u ltane o u sly, an i n te rnal polling seq uen ce determi ne s which re que st is servi c ed. t his i s called the a r bitratio n ran k in g. not e that the a r bitration ran k ing i s onl y used to re solve simultan eou s req u e s ts of the sam e priority level. as belo w tab l e summ ari z e s the interrupt source s, flag bits, vector a ddre s se s, en able bits, pri o rity bits, arbitration ra nkin g, and whether e a ch interrupt may wa ke up the cpu fro m power do wn mo de. source fl a g vector a ddress interrupt en a b le bits interrupt priority fl a g cle a r e d by a rbitr a t i on r a nking power down w a ke up ext er nal in te rru p t 0 ie0 0 0 0 3 h ex0 (ie0 .0 ) ip0 h .0 , ip0 . 0 h a rdware, follow the inverse of pin 1(highest) yes bro w n out det e ct bof 002b h ebo (i e. 5) i p0h. 5 , i p0. 5 software 2 yes wat c hdog ti m e r wd if 0 0 5 3 h ewd i (eie.4 ) i p1 h . 4 , ip1 . 4 software 3 no ti m e r 0 in te rru p t tf0 000b h et 0 (i e. 1) i p 0h. 1 , i p 0. 1 h a rdware, s o ftware 4 no i2 c in te rru p t si 0 0 3 3 h ei2 c (eie.0 ) ip1 h .0 , ip1 . 0 software 5 no adc co nvert e r adci 005b h ead (i e. 6) i p 0h. 6 , i p 0. 6 h a rdware 6 yes (1) N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 69 - revision a02 continued . sourc e fla g vecto r ad d ress inte rrupt enable bits inte rrupt priority f l ag cleared by a r bitra t ion ra nk ing po w e r do w n w akeu p ext er nal interrupt 1 i e 1 001 3h ex1 (i e. 2) i p 0h. 2 , i p 0. 2 h a rdware, follow the inverse of pin 7 yes kbi i n t e rrupt kbf 003b h ekb (ei e. 1 ) i p1h. 1 , i p1. 1 software 8 yes comp arat or 1 in te rru p t c m f1 0 0 6 3 h ec 1 (eie.2 ) ip1 h .2 , ip1 . 2 software 9 yes t i mer 1 i n t e rrupt tf1 001b h et 1 (i e. 3) i p 0h. 3 , i p 0. 3 h a rdware, s o ftware 10 no comp arat or 2 in te rru p t c m f2 0 0 4 3 h ec 2 (eie.3 ) ip1 h .3 , ip1 . 3 software 11 yes serial port t x and r x ti & ri 002 3h es (i e. 4) i p0h. 4 , i p0. 4 software 12 no pwm i n t e rrupt bkf 007 3h epwm (ei e . 5 ) i p1h. 5, i p 1. 5 software 13 (lo w e s t ) no note : 1. t he ad c converte r can w ake u p po w e r do w n m ode whe n its clock source is from internal rc. table 12 -3: vector lo catio n for interru pt sou r ces a nd power do wn wa keu p 12.3 respon se time the response time for each interrupt source depend s on several factors, such as the nature of the interrupt and the instruction underway. in the case of external interrupts int0 and int1 , they are sampl ed at c3 of every machi ne cy cle and then t hei r co rre sp ondi ng interrupt flags iex will be set o r reset. the ti mer 0 and 1 overflow flags a r e set at c3 of the m a chi ne cycle in whi c h overflow ha s occurre d . these flag valu es are polled only in the next machine cycle. if a reque st is active and all three con d itio ns a r e met, then the h a rd ware ge nerat ed lca ll is execute d. thi s lca ll itse lf take s four ma chi n e cycle s to b e com p leted. thus there is a minimum time of five machi ne cycle s betwe en the interrupt flag bein g set and the inte rrupt servi c e ro utine bein g e x ecuted. a longer resp onse time sh ould be a n tici pated if any of the three condition s are not met. if a highe r or equal prio rity is bei ng servi c ed, the n the interrupt late ncy time o b viously d epe nd s on th e natu r e of th e servi c e ro utine curre n tly being exe c ut ed. if the po lling cycle is not the last machine cy cle of the instru ction be ing execute d, then an additional delay is introd uced. the maximu m resp on se time (if no other interrup t is in service ) occu rs if the n79e825 se ries a r e perfo rmi ng a write to ie, eie, ip0, ip0h, ip1 or ip1h and then execute s a mul or div instru ction. from the time an interru pt source i s activated, the longe st rea c t i on time is 1 2 machi ne cy cles. thi s incl ude s 1 ma chi ne cycl e to d etect the interrupt, 2 m a c h ine c y c les to c o mplete t he ie, eie, ip0, ip0h, ip1 or ip1h ac ce ss, 5 machi n e cy cle s to compl ete the mul or di v instru ction and 4 m achin e cycl es to complete the h ard wa re l c a ll to the interrupt vect or location. thus in a si ngle-i nterrupt system the interrupt resp onse time will always be more than 5 machine cycle s and n ot more than 12 machi ne cycles. the m a ximum laten c y of 12 machine cycle s is 48 clock cycle s . note that in the standa rd 805 1 the maxi mum latency is 8 machi ne cycles which equal s 96 N79E825A/824a/823a/822a data sheet - 70 - machi ne cy cl es. thi s is a 50% red u ct io n in t e rms of clo ck p e rio d s. 12.4 interrupt in puts the n79e82 5 se ries have 13 interrupts sou r ce, and two individu al interru pt inp uts so urce s, one is fo r ie0, ie1, bo f, kbf, wdt, adc, cm f1 and cmf 2 , and other is if0, if1, ri+ti ,si and bkf. two interrupt inp u t s are ide n tical to those p r ese n t on t he stand ard 80 c51 mi cro c o ntroller a s sho w in belo w figures . if an external interrupt is en abled when t he n7 9e825 seri es a r e p u t into power down o r idle m ode, the interrupt will cause the pro c essor to wake up and resu me ope ration. ie0 ex0 ie1 ex1 bof ebo kbf ekb adci eadc wdt ewdi cm1 ec1 cm2 ec2 ea w ak eup (if in power down) i nt er r upt to c p u figure 12-1: interrupt sources that can wake up from power down mode N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 71 - revi si on a0 2 ei2 si es ri+ti et1 tf 1 et0 tf 0 ea int errupt to cpu bk f ep wm figure 12-2: interrupt sources that cannot wake up from power down mode N79E825A/824a/823a/822a data sheet - 72 - 13 programmable timers/counters the n79e 82 5 serie s have two 16-bit progra mm abl e timer/co unters and one progra mmabl e watchdo g timer. the watchdo g timer is ope rationally quite different from the other two timers. it?s timer/co unters have ad ditional timer 0 or timer 1 ov er flow tog g le output ena ble feature a s compa r e to conve n tional timer/co unters. this time r overflow to ggle outp u t can b e co nfigure d to automatically toggle t0 o r t1 pin output whe never a ti mer overflo w occurs. 13.1 timer/cou n ters 0 & 1 the n79e82 5 se rie s hav e two 16 -bit timer/counte r s. ea ch of these time r/cou n ters ha s two 8 bit regi sters whi c h form the 16 bit counting registe r . fo r timer/co unt er 0 they are th0, the upper 8 bits regi ster, and tl0, the lowe r 8 bit registe r . similarl y timer/counte r 1 has two 8 bit registe r s, th1 an d tl1. the two can be confi gure d to o perate eithe r a s timers, cou n ting ma chin e cycles or as counters c o unting external inputs . whe n config ured a s a "timer", the timer cou nts clo ck cy cle s . the timer clock can be pro grammed to be thought o f as 1/12 of the system clock or 1/4 o f the system cl ock. in the "counter" m ode, the regi ster i s in creme n ted o n the falling e d ge of the exte rnal in put pin, t0 for ti mer 0, and t 1 for timer 1. the t0 a nd t1 input s are sampl ed in every machin e cycle at c4 . if the sampl ed value is hi gh in one machi ne cy cl e and low in the next, then a valid high to low tran sition on the pin is recogni ze d and the cou nt regi ste r is in cre m ent ed. since it t ake s two ma chin e cy cle s to re cog nize a negative tra nsition on the pin, the maximum rat e at which counting will take pla c e is 1/8 of the m aster clo ck freque ncy. in either the "ti mer" o r "co u n ter" mod e , the count reg i ster will be update d at c3. the r efo r e, in the "timer" mode , the reco gni zed negative transitio n on pi n t0 and t1 can cause the count regi st er value to be update d only in the machi ne cy cle followin g the o ne in whi c h th e negative ed ge wa s dete c ted. the "time r " or "counte r " functio n is sel e cted by the " t c/ " bit in the t mod sp eci a l fun c tion re gister. each time r/ cou n ter ha s one sel e cti on bit for its own; bit 2 of tmod se lects the fun c tion for timer/counte r 0 and bit 6 of tmod sele cts the functio n for timer/counte r 1. in addition each timer/counte r can be set to operate in any one of four po ssi ble mode s. the mode sel ectio n is done by bits m0 an d m1 in the tmod sf r. 13.1.1 time-base selection the n7 9e82 5 seri es can operate like t he stan dard 8051/5 2 family, counti ng at the rate of 1/12 of the clo ck sp eed, or in tu rb o m ode, countin g at the rate of 1/4 cl ock sp eed. th e sp e ed is controll ed by the t0m and t 1 m bits in ckcon, and the default value is ze ro, whi c h use s the sta ndard 805 1/5 2 spe ed. 13.1.2 mode 0 in mode 0, the timer/counter is a 13-bit counter. the 13-bit counter consists of thx (8 msb) and the five lower bits of tlx (5 lsb). the upper three bi ts of tlx are ignored. the timer/counter is enabled when trx is set and either gate is 0 or intx is 1. when t c / is 0, the timer/counter counts clock cycles; when t c / is 1, it counts falling edg e s on t0 (p1. 2 fo r timer 0 ) or t1 (p0.7 for timer 1). for clo ck cycle s , the time base may be 1/12 or 1/4 clo ck spe ed, and the falling edg e of the clo c k increme n ts the counte r . when the 13-bi t value move s from 1fff h to 0000h, the timer overflow flag tfx is set, and an interrupt occurs if enabled. this i s illustrated in next figure bel ow. in ?timer? mode, if output toggle enable bit of p2m1 .t0oe or p2m1.t1oe is enabled, t0 or t1 output pin will toggle whenever a timer overflow occurs. N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 73 - revision a02 figure 13 -1: tim er/count ers 0 & 1 in mode 0 13.1.3 mode 1 mode 1 is si milar to m ode 0 exce pt that the co unting regi ster fo rm s a 1 6-bit co u nter, rath er th an a 1 3- bit counter. t his mean s that all the bits of thx and tlx are use d . roll-over o c curs whe n the timer moves from a count of ffffh to 0000h . the timer overfl ow flag t fx of the rele vant timer is set and if enabl ed an i n terrupt will occur. t he selectio n of the ti me-b ase in the timer m ode i s simil a r to that in mode 0. the gate functio n operates simi larly to that in mode 0. figure 13-2: timer/counters 0 & 1 in mode 1 N79E825A/824a/823a/822a data sheet - 74 - 13.1.4 mode 2 in mode 2, th e timer/cou n ter is in the auto reload mo de. in this mode, tlx acts as 8-bit count registe r , while t h x ho lds the reloa d value. wh e n the tlx re gister overflo w s from ffh to 00h, the tfx bit in tco n is set and tlx is re loade d with the conte nts of thx, and the cou nting pro c e ss conti nue s from here. th e rel oad ope ratio n leaves t he contents of the thx registe r unchan ged. cou nting is e nable d by the trx bit and pro per set t ing of gate and intx pins. as in the other two mode s 0 and 1 mod e 2 allows counti ng of either cl ock cycl es (cl o ck/12 or clo ck/4 ) or p u lse s on pin tn. in ?timer? mo de, if output toggle en able bit of p2m1 .t0oe or p2m1 .t1oe is ena bled, t0 or t 1 output pin will toggle when ever a timer overflo w occurs. figure 13 -3: tim er/count er 0 & 1 in mode 2 13.1.5 mode 3 mode 3 has different operating methods for the two timer/counters. for timer/counter 1, mode 3 simply freezes the counter. timer/counter 0, however, conf igures tl0 and th0 as two separate 8 bit count registers in this mode. the logic for this mode is shown in the figure. tl0 uses the timer/counter 0 control bits t c/ , gate, tr0, int0 and tf0. th e tl0 ca n be use d to co unt clock cycle s (clo ck/12 o r clo ck/4 ) or 1-t o-0 tra nsitio n s on pi n t0 a s dete r mi ne d by c/t (tmo d.2). t h 0 is f orced a s a cl ock cycl e cou nter (clo ck/12 or clo c k/4) and take s over the us e of tr1 and tf1 from timer/cou nter 1. mode 3 is use d in ca se s where an e x tra 8 bit time r is n eed ed. with time r 0 in mode 3, ti mer 1 ca n stil l be u s ed in mode s 0, 1 and 2, but its flexibility is somewhat lim i t ed. while its basi c fun c tio nality is maint a ined, i t no lon ger ha s cont rol ove r i t s overflo w fl ag tf1 and t he en able bit tr1. tim er 1 can still be u s ed as a timer/co unter and retains the use of gate and int1 pin. in this co ndition it can be turned on and off by swit chin g it out of and i n to its o w n mode 3. it ca n also be used a s a b aud rate g ene rat or for th e seri al po rt. in ?timer? mode, if output toggle enable bit of p2m1 .t0oe or p2m1.t1oe is enabled, t0 or t1 output pin will toggle whenever a timer overflow occurs. N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 75 - revision a02 figure 13-4: timer/counter mode 3 N79E825A/824a/823a/822a data sheet - 76 - 14 nvm memory the n79e8 2 5 se rie s h a ve nvm data m e mory of 25 6 bytes for cu stomer? s data store u s ed. t he nvm data mem ory has fou r pa ges area a nd each p age h as 6 4 byte s a s bel ow fig ure. the page 0 add re ss is from fc00 h ~ fc3fh , page 1 address is from f c 40h ~ fc7 f h , page 2 addre s s is fro m fc80h ~ fcbfh , and page 3 add re ss i s from f c c0h ~ fcff h . the nvm me mory can be read/ write by custom er progra m to access. read nvm data is by movc a,@a+dptr instru ction, and write dat a is by sfr of nvmaddr, nvmdat and nvm c o n . before write data to nvm memory , the page must be era s ed by providing page ad dre ss on nvmaddr, which low byte address of on-chip code mem o ry space w ill decode, then set eer of nvmcon.7. this will automatically hold fetch progra m cod e and pc co u n te r, and exe c ute pag e erase. after finishe d , this bit will be cleared by hardware. the erase time is ~ 5ms. for w r iting d a ta to nvm memory, use r must se t ad dre ss a nd da ta to nvmaddr an d nvm d at, then set ewr of nvmcon.6 t o initiate nvm data write. the u c will h o l d pro gra m code an d pc cou nter, and then wri t e data to m appin g addre ss. up on wri t e completio n , the ewr bit will be cleare d by hard w a r e, the uc will conti nue exe c ute next instru ction. the program time is ~5 0us. o n - c h i p c ode m em or y s p ace 00 00 h 16k/8k/4k/2k bytes on-chip code memory u nus ed c ode m em or y unused code memory config 1 3 f ffh / 1 fffh 4 0 00h / 2 00 0h ffffh page 0 64 bytes p age 1 64 b y t es p age 2 64 b y t es p age 3 64 b y t es fc 0 0 h fc 3 fh fc 4 0 h fc 7 fh fc 8 0 h fc bfh fc c 0 h fc ffh n v m d a t a me mo r y a r e a fc00h config 2 fc ffh 256 b y t es nv m d a t a me mo r y fb ffh figure 14-1: n79e825/824 memory map N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 77 - revision a02 15 watchdog t i mer the wat c hd o g timer is a free-run ning timer whic h can be p r og rammed by the use r to serve as a system mo nitor, a time-b a s e ge ne rator or an eve n t time r. it is basi c ally a set of dividers that divide the system clo c k. the divide r o utput is sele ctable an d det ermin es th e time-o ut interv al. whe n the time-out occurs a flag is set, whi c h can cau s e a n interru pt if enable d, and a system reset can al so be cau s e d if it is ena bled. the inte rru p t will occu r if the indi vidua l interrupt en able a nd the global enabl e are set. the inte rru pt and reset functio n s are indep ende nt of each oth e r an d may be u s ed se p a rately o r together d e p endin g on the user? s softwa r e. wdif 512 clock delay mux wdrun wd1,wd0 wdcl r ew d i ewrst reset interrupt 00 01 10 11 wtrf 2 6 -bits coun te r time-ou t selector 16 0 17 19 20 22 23 25 ( r eset watchdog) (wdcon.1) (w dc on .3) (eie.4) ( wd con.2) (w d c o n .0) ( w dcon.7) (wdcon.5/4) fcpu figure 15 -1: wat c hdog timer the watchdo g timer sho u l d first be restarted by usi ng wdcl r. this en sures that the timer start s from a kno w n state. the wdclr bit i s u s ed to re start t he wat c hd o g timer. thi s bit is self clea ring, i.e. after writing a 1 to this bit the software will automat i c ally clear it. the wat c hdog timer w ill now count clo ck cy cle s . the time-o ut interval is sele cte d by the two bits wd1 and wd0 (wdcon.5 an d wdco n.4 ) . whe n the sel e cted time -o u t occurs, the watchdo g int e rrupt flag wdif (wdco n .3) is set. after the time-out ha s occurre d , the watchdo g ti mer wait s for an additiona l 512 clock cycles. if the watchdo g reset ewrst (wdco n.1) is enabled, then 512 clo c ks after the time-o ut, if th ere is no wdclr, a system reset due to watc hdog timer will occur. t h is will la st for t w o machine cycles, and the wat c hdog timer reset flag wt rf (wdcon.2) will be set. this indi cates to the software that the watchdo g wa s the ca use o f the reset. whe n use d as a simpl e timer, the reset and interrupt function s are disa bled . the timer will set the wdif flag eac h time the ti mer c o mpletes the s e lec t ed time interval. the wdif flag is polled to detect a time-out a nd the wdclr allows softwa r e to resta r t the timer. t h e watchdo g ti mer can also be u s e d as a very lon g timer. the interrupt featu r e is ena bled in this c a se. every time the time-out o c curs an interrupt will occur if the gl obal interru p t enabl e ea is set. the main u s e of the watchd og time r is as a sy ste m monitor. this is impo rt ant in real-ti m e cont rol appli c ation s . in case of some po we r glitche s or el ectro - ma gneti c interfe r en ce, the pro c e s sor may begin to exe c ute erra nt code. if this is left unc h e c ked the ent ire syste m may cra s h. usi ng the watchdog timer interrupt during software developm ent will allow the user to select ideal watchdog reset location s. the code i s first written without the watchdo g interrupt or re set. then the watchdo g interrupt is e nable d to identify code l o catio n s wh e r e interrupt occurs. the use r can no w insert N79E825A/824a/823a/822a data sheet - 78 - instructions to reset the watchdog timer, which will allow the code to run without any wat c hdog timer interrupts. no w the watch dog time r re set is e nabl e d and the watchd og inte rrupt may be disa bled. if any errant code is executed now, then the reset watchdog timer inst ructions will not be executed at the requi re d instant s and watchdo g re set will o c cur. the watch d o g timer time -out sele ction will re sult in different time -out value s d epen ding o n the clo ck spe ed. the reset, wh en e nable d , will occur when 5 1 2 clo c ks after time-out ha s occurre d . wd1 wd0 interr upt time-out re set time-out numb e r of clocks time @ 10 mhz 0 0 2 17 2 17 + 512 131072 13.11 ms 0 1 2 20 2 20 + 512 1048576 104.86 ms 1 0 2 23 2 23 + 512 8388608 838.86 ms 1 1 2 26 2 26 + 512 67108864 6710.89 ms table 15 -2: t ime-o ut value s for the watchd og time r the watchdo g timer will de disabl ed by a power-o n/fail reset. the watchdog timer reset doe s not disa ble the watchd og time r, but will rest art it. in gene ra l, software sho u ld resta r t the timer to p u t it into a kno w n state. the co ntrol bits that su p port the watchdog tim e r a r e discu s sed belo w . 15.1 watc hdo g contr o l wdif: wdcon.3 - watchdog tim e r interrupt flag. this bi t is set when ever th e time-out o c curs in the watchdo g timer. if the watchd og interrupt is enable d (eie.4), then an interrupt will occu r (if the global interrupt ena ble is set and other interru p t requireme nts are met ) . software o r a n y reset can clea r this bit. wt rf: wdcon.2 - watchdog time r re set flag. t h is bit i s set whe never a watchdo g reset occu rs. this bit is useful for determined the ca use of a rese t. software must read it, and clea r it manually. a powe r-fail re set will cl ear this bit. if ewrst = 0, then this bit will not be af fected by the watch dog timer. ewrst: wdco n.1 - e n a b le watch d o g time r rese t. this bit wh en set to 1 wi ll enabl e the watchdo g timer reset function. setti ng this bit to 0 will disabl e the watchdog timer reset function, but will leave the timer run ning. wdcl r: wdco n.0 - reset watchd og timer. this bit is used to clear the watchd og tim er and to restart it. this bit is self-cl earing, so after the software writes 1 to it t he hardware will automatically clea r it. if the watchdo g timer re set is enable d, then the wdcl r has to be set by the user within 512 clo c ks of the time-o ut. if this is not do ne then a wat c h dog time r re set will o c cur. N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 79 - revision a02 15.2 clock co ntrol of watchdog wd1, wd0: wdco n.5, wd co n.4 - watchdo g ti mer m ode select bit s . th ese t w o bit s sele ct the time-out interval for the watchdo g timer. the re set time is 512 clo cks longe r than the interru pt time-o ut value. the default watchdo g time-out is 2 17 clocks, whi c h i s the shorte st time-out peri od. the wdrun, wd0, wd1, ewrs t, wdif and wdclr bits are prote c te d by the timed acce ss pr oce dure. this prevents softwa r e fro m accid entall y enabling or disabling th e watchd og timer. more importa ntly, it makes it highly improb able that erra nt code can e nable o r disa ble the wat c h dog time r. N79E825A/824a/823a/822a data sheet - 80 - 16 serial p o rt (uart) serial po rt in the n79e82 5 seri es i s a full dupl ex port. the n7 9 e 825 se rie s provide the u s er with addition al fea t ures su ch a s the frame erro r dete cti on and the a utomatic add r ess re cog nition. the seri al p orts a r e cap able o f synchro nou s a s we ll a s asyn ch ron o us com m uni cation. in syn c hrono us mode the n79e825 se ri es g ene rate the clo c k and o perate s in a half duplex mo de. in the asyn chrono u s mod e , full duplex ope rati on is avail abl e. this me an s that it can simultaneo usly transmit and re ceive data. the tra nsmit re giste r and the re ceive buffer are both add re ssed a s sbuf special functio n re g i ster. howeve r any write to sbuf will be to the transmi t registe r , whi l e a read fro m sbuf will be from the receive r buffer regi ste r . the seri al port can op erate in four different modes a s descri bed b el ow. 16.1 mode 0 this mod e p r ovide s syn c hron ou s com m unication with external device s . in this mode seri a l data is transmitted and re ceived on the rxd line. txd is used to tran smit the shift clo ck. the t x d clock is provide d by the n79e8 25 seri es w heth er the device is tran smitting or receiving . this mode is therefo r e a half duplex mode of serial communi cati on. in this mo de, 8 bits are transmitted or received pe r frame. the lsb is t r an smitted/receive d first. the baud rat e is fixed at 1 / 12 or 1/4 of the oscill ator frequ en cy. this bau d rate is determi ned by the sm2 bit (sco n.5) . wh en this bit is set to 0, then the seri al port run s at 1/12 of the clo c k. whe n set to 1, the se rial port run s at 1 / 4 of the clo c k. this additi onal fa cility of prog ram m able b aud ra te in mode 0 is the o nly differen c e b e t ween th e st anda rd 8 051 and the n79e8 25 seri es. the function a l block diag ra m is shown below. data e nters an d lea v es the seria l port on the rxd line. the txd line is use d to output the shif t clock. the shift clock is u s ed to shift data into and out of the n79e8 25 series an d the device at the other en d of the line. any instru ction that cau s e s a write t o sbuf will sta r t the transmi ssi on. the shift clock will be activated and data will be shifted ou t on the rxd pin till a ll 8 bits are tran smitted. if sm2 = 1, then the data on rxd will appe ar 1 clo ck peri od before the falling edge of shift clock on txd. the clock on txd then remai n s l o w for 2 clock perio ds, and then goe s high again. if sm2 = 0, the data on rxd will appea r 3 clock peri ods befo r e the falling edge of shift clo ck on tx d. the clo ck on txd then re mains l ow fo r 6 clo c k pe rio ds, an d then goe s hig h again. t his e nsu re s that a t the re ceivin g end the d a ta on rxd li ne can eithe r b e clo c ked on the ri sin g edge of the shift clock on txd or latc he d whe n the txd clo ck i s lo w. N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 81 - revision a02 1/12 fcpu 0 tx c l o c k rx cl o ck ti ri tx shift rx s ta rt rx sh i ft loa d s b u f shift cl ock ri ren sm2 clo c k si n parout sbuf r ead sb u f internal data bus serial controllor clock l oad parin tx s t a rt internal data bus sbuf wri t e to sout transmit shift register serial interrupt rx d tx d rx d p1.1 a lter n at e i n pu t f u nc t i o n p1 .1 alte rna t e ou tpu t f unc tio n p1 .0 alte rna t e ou tpu t f unc tio n 1/4 1 figure 16 -1: seri al port mode 0 the ti flag is set high in c1 following the end of transmi ssio n of the last bit. th e serial po rt will receive data whe n ren is 1 and ri is ze ro. th e shift clock (t xd) will be activated and the serial po rt will latch data on the ri sing e dge of shift clo ck. t he extern al d e vice shoul d therefo r e p r e s ent data on the falling edge o n the shift clo c k. this p r o c e ss continue s till al l the 8 bits ha ve been re cei v ed. the ri fl ag is set in c1 follo wi ng the la st ri sing edge of the shift clo ck on txd. t his will stop rec eption, till the ri i s clea red by so ftware. 16.2 mode 1 in mode 1, the full duplex asyn chrono u s mode i s used. serial co mmuni cation frame s are m ade up of 10 bits tran smitted on txd and received on rx d. the 10 bi ts co nsi s t of a start bit (0), 8 data bits (lsb first), an d a stop bit (1). o n re ceived, th e stop bit g o e s into rb8 i n the sfr s c o n . the b a ud rate in this mode i s variable. the seri al bau d can be progr a mmed to be 1/16 or 1/32 of the timer 1 overflow. since the tim e r 1 ca n be set to different reloa d value s , a wide varia t ion in baud rates is p o ssib le. tran smi ssi on begins with a write to sbuf. the se ria l data is brou ght out on to txd pin at c1 following the first roll -o ver of divide by 16 cou n te r. the next bi t is place d o n txd pin at c1 follo wing the next rollove r of the divide-by-16 cou n ter. thu s the trans mi ssion i s syn c h r onized to the divide-by -16 cou n ter and n o t dire ctly to the write to sbuf si gnal. after al l 8 bits of da ta are tran smitted, the stop bit i s transmitted. the ti flag is set in the c1 state a fter th e stop bit ha s been put o u t on txd pin. this will be at the 10th rollover of th e divide-by -1 6 cou n ter afte r a write to s b uf. N79E825A/824a/823a/822a data sheet - 82 - re ceptio n is enabl ed only if ren is high. the seri a l por t actually starts the re ceiving of serial data, with the dete c tion of a falling edge o n the rxd pin. t he 1-to -0 de tector continu ously monito rs the rxd line, samplin g it at the rate of 16 times the se lected baud rate. whe n a falling edge is det ected, the divide?by-16 cou n ter is im mediately re set. this helps to align the bit bounda rie s with the roll overs of the divide-by -16 co unter. the 16 states of the counte r effect ively divide the bit time into 16 sli c e s . the bit d e tection i s do ne on a best of three bases. the bi t detector sa mples the rxd pin, at the 8th, 9th and 10th co unter states. by usin g a majo rity 2 of 3 vo ting system, the bit val ue is sel ected. this is d one to improve the noise reje ction feature of the serial port. if the first bit detected after the falling edge of rxd pin is not 0, then this indi cate s an invalid sta r t bit, and the re ception i s i mmediately a borted. t he serial p o rt a gai n loo k s for a fallin g edge i n the rxd lin e. if a valid sta r t bit is dete c te d, then the rest of the bits a r e al so detecte d and shifted into th e sbuf. after shifting in 8 data bits, there is one more shift to do, after which the sbuf and rb8 are loade d and ri is set . however ce rtain con ditio ns must be met before the loading a nd setting of ri can be done. 1. ri must be 0 and 2. either sm2 = 0, or the re ceived stop bi t = 1. if these co ndi tions are met , then the sto p bit goes to rb8, the 8 d a ta bits go into sbuf and ri is set. otherwise the received frame may be lost. after the mi ddle of the stop bit, the receiver go es ba ck to looki ng for a 1-to-0 tran sition on the rx d pin. figure 16-2: serial port mode 1 N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 83 - revision a02 16.3 mode 2 this mod e use s a total of 11 bits in asynch ron ous full-dupl ex communi cation. the function al descri ption i s sho w n i n the figure belo w . the fra m e cons i s ts of on e sta r t bit (0 ), 8 data bit s (lsb first), a pro gramma ble 9th bit (t b8) an d a sto p bit (0 ). the 9th bit re ceiv ed is put into rb8. the ba ud rate is prog ram m abl e to 1/32 or 1/64 of the oscill ator fre q u ency, whi c h i s determi ned by the smo d bit in pcon sf r. tran smi ssi on begins with a write to sbuf . the se ria l data is brou ght out on to txd pin at c1 followin g the first roll-o v er of the divide-by- 16 counter. the next bit is place d on txd pin at c1 followin g the next rollove r of the divide -by-16 co unt e r . thu s the t r ansmi ssion is synchroni ze d to the divide-by -16 cou nter, and not directly to the wr ite to sbuf signal. after all 9 bits of data are transmitted, the stop bit is transmitted. the ti flag is set in the c1 state after the stop bit has b een put out on tx d pin. this will be at the 1 1 th rollove r o f the divide-b y -16 counte r after a write to sbuf. re ceptio n is enabl ed only if ren is high. the seri a l por t actually starts the re ceiving of serial data, with the dete c tion of a falling edge o n the rxd pin. t he 1-to -0 de tector continu ously monito rs the rxd line, samplin g it at the rate of 16 times the se lected baud rate. whe n a falling edge is det ected, the divide- by-16 counte r is i mmediately reset. thi s hel ps to align th e bit bound aries with th e rollovers of the divide-by-16 counte r . t he 16 state s of the co unte r effectively d ivide the bit time into 1 6 sli c e s . the bit detectio n i s do ne o n a best of th ree bases. t he b it detecto r sa mples the rxd pin, at th e 8th, 9th and 10th co u n ter state s . by using a majority 2 of 3 voting syste m , the bit value is sele cte d . this is done to imp r o v e the noise rejectio n featu r e of the se ria l port. figure 16-3: serial port mode 2 N79E825A/824a/823a/822a data sheet - 84 - if the first bit detecte d after the falling edge of rxd pin, is not 0, th en this indica tes an invalid start bit, and the rece ption is imm e diately abo rte d . the serial port ag ain loo ks fo r a fallin g edge i n the rxd line. if a valid start bit is detected, then the rest of t he bits are al so de tected and shifted into the sbuf . after shifting in 9 data bits, there is one more shift to do, after which the sbuf and rb8 are loade d and ri is set . however ce rtain con ditio ns must be met before the loading a nd setting of ri can be done. 1. ri must be 0 and 2. either sm2 = 0, or the re ceived stop bi t = 1. if these co ndi tions are met , then the sto p bit goes to rb8, the 8 d a ta bits go into sbuf and ri is set. otherwise the received frame may be lost. after the mi ddle of the stop bit, the receiver go es ba ck to looki ng for a 1-to-0 tran sition on the rx d pin. 16.4 mode 3 this mod e is similar to mode 2 in all aspe cts, ex ce pt that the b aud rate is p r og ramm able . the user must first initialize the serial related sfr scon before any co mmuni cation can take place. thi s involves sele ction of th e m ode a nd b a u d rate. t he ti mer 1 should also be i nitia lized if m ode s 1 and 3 are used. in all four mode s, tran smi ssi o n is starte d b y any instruct ion that u s e s sbuf a s a d e stinatio n regi ster. re ception is initiated in mode 0 by t he condition ri = 0 and ren = 1. this will gene rate a clo ck o n the txd pin an d shift in 8 bits on the rx d pi n. reception i s initiated in the othe r mod es by the incomi ng start bit if ren = 1. the external device will start the com m unication by transmitting the start bit. figure 16 -4: seri al port mode 3 N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 85 - revi si on a0 2 sm0 sm1 mode type baud cloc k frame siz e start bit st op bit 9th bit function 0 0 0 synch. 4 or 12 t c lk s 8 bits no no none 0 1 1 asynch. timer 1 10 bits 1 1 none 1 0 2 asynch. 32 or 64 t c l k s 11 bits 1 1 0, 1 1 1 3 asynch. timer 1 11 bits 1 1 0, 1 table 16 -5: serial port mo de summa ry table 16.5 framing error detection a frame e r ror o c curs wh en a valid stop bit is n o t det ecte d. thi s could in dicate incorre c t seri al dat a comm uni cati on. typically the frame error i s du e to n oise and co ntention o n the se rial comm unication line. the n79 e 825 se rie s have the facil i ty to detect su ch framin g erro rs a nd set a flag which can be che c ked by software. the fra m e erro r fe bit is locate d in scon.7. thi s bit is normally use d as sm0 in the stand ard 80 51 family. howe ver, in the n79e825 seri e s it serves a dual functio n and is call ed sm0/fe. there are actually two sep arate flag s, one for sm0 and the other for fe. the flag that is actually acce ssed as scon. 7 is d e termin ed by smod0 (p co n.6) bit. whe n smod0 is set to 1 , then the fe flag is indicated in sm0/fe. when smod0 is set to 0, then the sm0 flag is indi cated in sm0/fe. the fe bit is set to 1 by hardware but must be cl ear e d by software . note that smod0 m ust be 1 whil e readi ng or wri t ing to fe. if fe is set, then any follo win g frames rece ived without any erro r will not clea r the fe flag. the cle a rin g h a s to be do ne by software. 16.6 multiproce ssor co mmunication s multipro ce ssor commu nications m a kes use of the 9t h data bit i n mode s 2 a nd 3. in the n79e8 2 5 seri es, the ri flag is set on ly if the received byte corresp ond s to the given or broad ca st address. this hard w a r e fea t ure eliminate s the software overhea d required in ch ecking every received add ress, and greatly sim p lifies the softwa r e programm e r task. in the multiproce ssor com munication m ode, the a d d r ess bytes are disting u ishe d from the d a ta bytes by transmitting the add re ss with the 9th bit set high. whe n the ma ster p r o c e s so r wa nts to tra nsmit a block of data to one of the slave s , it first sen d s out the addre s s of the targeted sl a v e (or slave s ). all the slave p r o c e s sors sh ould h a ve their sm 2 bit set high whe n waitin g for a n ad dress byte. thi s en su re s that they will be interrupt ed only by the rec eption of an address byte. the automatic addre s s recognitio n feature en su re s that only the addresse d sl ave will be in terrupted. the addre s s com pari s on is don e in hardwa r e not software. the add re sse d slave cl ears the sm2 bit, thereby cl ea ri ng the way to receive d a ta bytes. with sm2 = 0, the slave will be interrupte d on the re ce ption of ev ery single compl e te frame of data. the un addresse d slave s will be unaffected, a s they will be still waiting fo r their ad dre s s. in mode 1, the 9th bit is the stop bit, which i s 1 in ca se of a valid frame. if sm2 is 1, then ri is set only if a valid frame is received and the received byte matche s the given or broad ca st ad dre ss. N79E825A/824a/823a/822a data sheet - 86 - the maste r processo r ca n sele ctively co mmuni cate wi th group s of slaves by usin g the given addre s s. all the slaves can b e add ressed tog e th er u s ing t he broad ca st ad dre ss. t he a ddre s se s for each slave are defin ed b y the saddr and sade n sfr s . the slave add re ss i s an 8 - bit value spe c ifi ed in the saddr sfr. the saden sfr i s a c tually a mask for the byte value in saddr. if a bit p o sition i n saden is 0, then the correspon ding bi t position in saddr is don't care. only those bit position s in saddr who s e corre s p on ding bit s in s a den a r e 1 are u s e d to o btain the giv en add r e ss. this give s the use r flexibility to addre ss m u ltiple sl aves with out cha ngin g the slave ad dre s s in saddr. the followi ng example sh o w s h ow the u s er can d efin e the given addre s s to add ress different slave s . slave 1: saddr 1010 0 100 saden 1111 1 010 given 1010 0x0x slave 2: saddr 1010 0 111 saden 1111 1 001 given 1010 0xx1 the given a d dre ss fo r slave 1 and 2 differ in the lsb. fo r slave 1, i t is a don't ca re, while fo r slave 2 it is 1. th us to comm uni cate only with sla v e 1, the ma ster m ust se nd an add re ss with lsb = 0 (1 010 0000 ). simila rly the bit 1 p o sition i s 0 fo r sl ave 1 a n d don't care fo r sl ave 2. he nce to co mm unicate only with sla v e 2 the ma ster h a s to transmit a n ad dre ss with bi t 1 = 1 (10 1 0 0011 ). if the maste r wishe s to co mmuni cate with both slave s simulta neo usly, then the addre s s mu st have bit 0 = 1 and bit 1 = 0. the bit 3 positio n is don't care fo r both the sl aves. thi s allo ws two diffe ren t addre s se s to sele ct both slave s (1010 0 001 a n d 1010 0 101 ). the ma ster can comm uni cate with all the slave s si multaneo usly with the bro adcast add r e ss. thi s address i s fo rmed f r om th e logi cal o r of the saddr an d sade n sfrs. th e ze ros in the result are defined a s d on't ca re s. in most ca se s the broad ca st addre s s is ffh. in the previou s case, the broad ca st addre ss i s (1 11 1111x) fo r sla v e 1 and (11 1 1111 1) for sla v e 2. the saddr and sade n sfrs are l ocated at add re ss a9 h an d b9h re sp ective ly. on reset, these two sfrs are initialize d to 00h. this result s in gi ven ad dre ss an d broad ca st address being set as xxxx xxxx (i.e. all bits don't care). this effectively re moves the multiprocessor communi cations feature, sin c e any sel e ctivity is disabled. N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 87 - revision a02 17 time access proctection the n79e 82 5 serie s hav e a new feature, like t he watchd og timer whi c h is a crucial to proper operation of the system. if left unprotected, errant code may writ e to the watchdo g co ntrol bits resulting i n in corre c t op era t ion and lo ss of cont rol. in orde r to prev ent this, the n79e8 25 se ri es h ave a prote c tion scheme whi c h controls the write acce ss to critical bits. this prote c tion schem e is done usin g a timed access. in this meth od, the bits whi c h a r e to be protec te d have a tim ed write en a b le win d o w . a write is su ccessful on ly if this wind ow is active, otherwise the write will be discarded. t h is write e nabl e win d o w is open for 3 machin e cycles if certa i n conditio ns are met. after 3 machin e cycle s , this wind ow automatically clo s e s . the wind ow is o p ened by writ ing aah and immediately 5 5h to the timed acces s (ta) sfr. this sfr is lo cated at address c7h. th e sugg este d cod e for ope ning the timed access wind ow i s ta reg 0c7h ;define ne w registe r ta, located at 0 c 7 h mov ta, #0aah mov ta, #055h whe n the sof t ware write s aah to the t a sfr, a counter is start ed. this cou nter wait s for 3 machine cycle s loo k in g for a write of 55h to ta. if the seco nd write (5 5h) o c curs within 3 machi ne cycl es of the first write (a ah), then the timed acce ss win d o w is open ed. it remains ope n for 3 ma chi ne cycle s , durin g which the user m a y write to the p r otecte d bi ts. once the win dow clo s e s th e pro c e du r e must be repe ated to a c cess the oth e r protecte d bits. examples of timed asse ssing a r e sho w n bel ow. example 1: valid acce ss mov ta, #0aah ;3 m/c note: m/c = mac h ine cy c l es mov ta, #055h ;3 m/c mov wd co n, #00 h ;3 m/c example 2: valid acce ss mov ta, #0aah ;3 m/c mov ta, #055h ;3 m/c n o p ; 1 m / c setb ewrst ;2 m/c example 3: valid acce ss mov ta, #0aah ;3 m/c mov ta, #055h ;3 m/c orl wdco n, #00 0000 10b ;3m/c example 4: invalid acce ss mov ta, #0aah ;3 m/c mov ta, #055h ;3 m/c n o p ; 1 m / c n o p ; 1 m / c N79E825A/824a/823a/822a data sheet - 88 - c l r e w t ; 2 m / c N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 89 - revision a02 example 5: invalid acce ss mov ta, #0aah ;3 m/c n o p ; 1 m / c mov ta, #055h ;3 m/c setb ewt ;2 m/c in the first three example s , the writing to the p r ote c ted bit s i s done befo r e the 3 ma chi n e cy cle s wind ow clo s e s . in example 4, however, the writing t o the prote c t ed bit occu rs after the win dow h a s clo s ed, a nd so the r e i s e ffectively no cha nge i n th e statu s of t he p r ote c ted bit. in example 5, the se con d write to ta occurs 4 machine cycle s after t he first write, therefore t he timed acce ss wi ndo w i s not open ed at all, and the write to the protected bit fai ls. N79E825A/824a/823a/822a data sheet - 90 - 18 key b oard interrupt (kbi) the n7 9e82 5 seri es are provide d 8 keyboard interrupt functio n to detect key pad statu s which key is acted, an d all ow a single i nterrupt to be gene rat ed when any key is presse d on a keybo a rd o r keyp ad con n e c ted to spe c ific pin s of the n79e8 25 seri es, a s sho w n belo w figure. thi s i n terrupt may be u s e d to wake up the cpu from idle or power down modes , after c h ip is in powe r down or idle mode. keyboard fun c tion i s supp o r ted throug h by port 0. it can allo w a n y or all pins of port 0 to be e nable d to cau s e thi s int errupt. port p i ns a r e en abl ed by the set t ing of bits of kbi0 ~ kbi7 in the kbi reg ister, a s sho w n belo w figure. the keyboard interru pt flag (kbf) in the auxr1 regi ster is set when any enabl ed pin is pulled lo w while the kbi interrupt fun c tion is activ e, and the low pulse must be more than 1 mach ine cycle, an interrupt will be generate d if it has been ena bled. the kbf bit set by hardware and must be cleared by so ftware. in order to determine wh i c h key was pressed, the kbi will allow the inte rru pt se rvice routine to poll port 0. p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.0 kbi.0 kbi.1 p0.1 kbi.2 kbi.3 kbi.4 kbi.5 kbi.6 kbi.7 ekb (from eie register) kbf (kbi interrupt ) figure 18-1: keyboard interrupt N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 91 - revision a02 19 analog comparators the n79e 82 5 serie s are provided two compa r ato r s. input and output options allo w use of the comp arators in a number o f differ ent configuratio ns. the com parator output is a logical one when its positive inp u t is gre a ter th an its ne gative input, other wise the outp ut is a ze ro. each comp a r ator ca n be co nfigured to cause to an inte rrupt wh en the output value ch ang e . the block di agra m is a s b elow. each com parator ha s a co ntrol r egi ster (cmp1 and cmp2), both i nputs are ci nna, cinnb, cmpre f and inte rnal referen c e vol t age, and o u t puts are cm p1 and cmp2 by setting oen bit. afte r ena ble comp arators the com pa r at or ne ed waite d stabl e ti me to guarantee comp arator o u tput. if programmer use d internal refere nce vo ltage, it will be set oen bi t to ?1?. the value of internal refe ren c e voltage (vref) i s 1.19 v +/- 10%. - + cmf1 c m p 1 (p0.6) interrupt cn1 cp1 vr ef co 1 oe 1 c h a nge d e t ect c o m parat or1 (p 0 . 4 ) c in 1 a (p 0 . 3 ) c in 1 b (p 0 . 5) c m p r e f - + cmf2 c m p 2 (p0.0) interrupt cn2 cp2 co 2 oe 2 c h a nge d e t ect c o m parat or2 (p 0 . 2 ) c in 2 a (p 0 . 1 ) c in 2 b c m p 1 a n a l o g c irc u it cmp2 analog circuit vref ce1 ce2 en a b l e cmp1 enable cmp2 en figure 19-1: analog comparators N79E825A/824a/823a/822a data sheet - 92 - 20 i/o port configuration the n79e8 2 5 se rie s hav e three i/o p orts, po rt 0, port 1 a nd p o rt 2. all pin s of i/o port s can b e config ure d to one of four types by software exce pt p1.5 is only input pin. wh en p1.5 is configure d reset pin by rpd=0 i n the co nfig 1 registe r , the n79e825 serie s can su ppo rt 15 pi ns by u s e cry s tal. if used on -chi p rc oscillat or the p1.5 i s configu r e d in put pin, the n79e825 se rie s can be su p ported up to 18 pins. th e i/o ports co nfiguratio n se tting as belo w table. pxm1. y pxm2. y port in put / out p ut mo de 0 0 qua si-bidirectional 0 1 push -pull 1 0 input only (hi gh impeda nce) p2m1.pxs=0 , ttl input p2m1.pxs=1, schmitt input 1 1 open drai n table 20 -1: i/o port co nfiguratio n tabl e all port pins can be d e termined to hig h or low afte r re set by co nfigure prhi bit in the c onfig 1 regi ster. after reset, the s e pins a r e in q uasi - bidi re ctional mod e . the port pin of p1.5 only is a schmitt trigge r input. enabled togg le output s fro m timer 0 a nd time r 1 b y t0oe an d t1oe on p2 m1 re giste r , the outp u t freque ncy of timer 0 o r ti mer 1 is by ti mer overflo w . each i/o port of the n79e825 se rie s may be sele ct ed to use ttl level inputs or schmit t inputs by p(n)s bit on p2m1 regi ste r , where n is 0, 1 or 2. when p(n)s is set to 1, ports are selecte d schmitt trigge r inputs on port(n). the p2.0 (xtal2) ca n be configured clo ck outp ut wh en use d on-chip rc or external o s ci llator is clo c k sou r ce, and the frequ en cy of clock ou tput is divide d by 4 on on -chi p rc clock or external oscillator. 20.1 quasi-bidi r ectional o u tput configuration after chip wa s power on o r reset, the all ports out put are this mod e, and output is common with the 8051. thi s m ode can be u s ed a s both a n input and o u tput without the need to reco nfigure the port. whe n the pin is pulled lo w, it is driven strongly and a b le to sin k a fairly large cu rre nt. these feature s are some wh at similar to an open d r ai n output except that there are thre e pull-up tra nsi st ors in the qua si-bi d ire c t i onal outp u t that serve diff erent pu rp oses. this m ode ha s three pull - u p re siste r s th at are ?st r ong ? pull - up, ?we ak? pull - up an d ?very wea k ? pull-u p. the ?st r on g? pull-u p is use d fast transiti on from l ogic ?0? cha nge to logic ?1 ?, and it is fast latch an d transitio n. when po rt pins is occur from logic ?0 ? to logic ?1?, the stron g pull- up will quickly turn on two cpu c l ocks to pull high then turn off. N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 93 - revision a02 the ?wea k? p ull-up i s turn ed on when t he input po rt pin is logi c ?1? level or itself is logic ?1 ?, and it provide s the most source curre nt for a qua si-bi dire c t i onal pin that output is ?1 ? o r port latch is logic ?0??. the ?very we ak? pull - u p is turned on wh en the port latch is logic ?1 ?. if port latch is logic ?0?, it will be turned off. the very weak pull-up i s support a very sma ll current that will pull the pin hi gh i f it is left floating. and the qua si-bidirection al port config uratio n is sh own as b elow figu re. if port pin is l ow, it can d r i v es large si n k cu rrent for output, and it is simila r wit h push-p ull a nd ope n drain o n sin k curre n t outpu t. port pin 2 cpu clock delay input data po r t l a t c h da t a pp p n vd d strong ve r y w eak we a k figure 20 -2: qua s i-bidirectional output 20.2 open drai n output configuration to configu r e this mode is turne d off all pull-u ps. if used simila r as a logic output , the port mu st has an external pull - up re siste r . t he ope n drai n port co nfiguration is sho w n as bel ow. port pin p o rt lat ch da ta n input data figure 20-3: open drain output N79E825A/824a/823a/822a data sheet - 94 - 20.3 push-pull output configuration the pu sh-pul l output mode has two st rong pull - up a nd pull-down structu r e tha t suppo rt larg e sou r ce and sin k cu rrent output. it remove s ?we ak? p ull-u p an d ?very wea k ? pull-up re si ster and re mai n ?stro ng pull-u p re sist er on qua si-b idire c tional o utput mode. the ?st r on g? pull-u p is always turn s on whe n port latch is lo gic ?1? to su ppo rt sou r ce cu rren t. the pus h - p u ll port co nfig uration i s sh o w n in bel ow f i gure. the n79e 82 5 serie s have three port pins that can? t be config ure d . they are p1.2, p1.3, and p1.5. the port pin s p1.2 and p1.3 a r e configu r ed to open drai n outputs. th ey may be us ed as in puts by writing one s to their resp ective po rt latches. port pin input data p o rt lat ch da ta p n vdd figure 20 -4: pus h-pull output 20.4 input onl y configurati on by configure this mode, the ports are only digita l input and disable digital output. the n79e825 series can select input pin to schmitt trigger or ttl level input by pxm1.y and pxm2.y registers. N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 95 - revision a02 21 oscillat o r the n79e825 seri es provides thr ee oscillator input option. these ar e configured at confi g regi ster (config1) t hat include on-chip rc oscillator op tion, external clock i nput option and cry s tal oscillator inp u t option. the cry s tal o scill ator inpu t frequen cy may be sup ported from 4mhz t o 20mhz, and without capa citor or resi stor. fosc0 fos c 1 00b 11b 01b crystal oscillato r extern al clock inpu t inte rnal rc o s cillator 16 bits ripp le counter divide-by-m (divm register) cpu clock po wer monitor reset power down 1/4 to adc block periphe ral cloc k f cp u f i gur e 21- 1 : o scillator 21.1 on-chip rc oscillator option the on-chip rc oscillator is fixed at 6mhz 50% frequency to support clock source. when fosc1, fosc0 = 01b, the on-chip rc oscillator is enabled. a clock output on p2.0 (xtal2) may be enabled when on-chip rc oscillator is used. N79E825A/824a/823a/822a data sheet - 96 - 21.2 external cl ock input option the cl ock so urce pin (x t a l1) is from external clo c k input by f osc1, fos c 0 = 11 h, and freque ncy rang e is form 0hz up to 20mhz. a clock output on p2.0 (xtal2) m a y be enable d when external clo c k input is used. the n79e825 series supports a clock output functi on when either the on-chi p rc oscillat or or the e xte r n a l c l ock in pu t o p tio ns is se lec te d . t h is a llow s e xte r n a l d e vic es to s yn ch r o n i ze to th e n 7 9 e 825 seri al. whe n enabled, via the enclk bit in the p2 m1 re giste r , the cloc k o utput appe ars on the xtal2/clko ut pin when ever the on -chip oscillato r is run n ing, in cluding in idle mode. the freque ncy of the clock o u tput is 1/4 o f the cpu clo ck rate. if the clock outp u t is not need ed in idle mode , it may be turned off prior to entering idle m ode, saving addition al po wer. the cl o ck outp ut may also be enabl ed wh e n the external clock inp u t option is sele cted. 21.3 cpu clock rate s e lec t the cpu clo ck of n7 9e8 25 series ma y be selecte d by the div m register . if divm = 00h, the cpu clock is run ning at 4 cp u clock p er machine c y c l e, and witho ut any divisi on from sou rce clock (fos c). whe n the divm registe r is set to n val u e, the cpu clock is divided by 2(dv im +1), so cpu clock fr equen cy division is from 4 to 512. th e user may use this fea t ure to set cpu at a lower speed rate for red ucing power consumptio n. this is very similar to the situatio n when cpu ha s en tered idle m ode. in addition this fr e quenc y division func tio n af fect all peripher a l timings as they are all s ourcing fro m the cpu c l ock(f c pu). N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 97 - revision a02 22 power monitoring function power-on detec t an d br ownou t are two addition al power mo nitoring fu n c tions imple m ented in n79e8 25 se r i es to prev e nt incorre ct opera tion du ring power u p and powe r drop or loss . 22.1 po w e r on detect the po wer? on detect function i s a de s ign ed to det ect po we r up after po wer v oltage rea c he s to a level where brownout detect can work. after po wer on detect, the p or (p con.4) will be set to ?1? to indicate an ini t ial powe r up con d ition. th e por flag wi ll be clea red by softwa r e. 22.2 bro w n out det ect the bro w n o u t detect fun c tion is dete c t power voltag e is drop s to bro w no ut voltage level, an d allows preventin g so me pro c e s s work o r indi cate power warmin g. the n79e8 25 series have two bro w nout voltage levels to select by bov (co n fi g1.4). if bo v =0 that bro w nout voltage l e vel is 3.8v, if bov = 1 that browno ut voltage lev e l is 2.5v. when the b r o w nout voltage i s d r op to sel e ct level, the b r ownout detecto r will detect and ke eps this a c tive until vdd is returns to above bro w no ut detect voltage. the brownout detect blo ck i s a s follow. boi (e nabl e b r ow nout d et ect ) brown ou t detect ci r c ui t 0 1 bof t o r eset t o b r o w nout int er rupt bo d figure 22 -1: bro w n out detect blo ck whe n bro w n out dete ct is enable d by bod (aux r1.6), the b o f (pcon.5 ) flag will be set and bro w no ut re set will occu r. if boi (auxr1.5) is set to ?1?, the b r o w nout dete c t will cau s e interrupt via the ea (ie.7) and ebo (ie.5) bits i s set. bof is cle a re d by softwa r e . in order to guarantee a correct dete c tion of brow no ut, the vdd fall time must be slowe r than 50mv/us, an d rise time i s slo w er th a n 2 mv/us to ensure a p r op er reset. N79E825A/824a/823a/822a data sheet - 98 - 23 puls e-width-modulat ed (pwm) output s the n79e8 2 5 se rie s h ave four p ulse width m odul ated (p wm) cha nnel s, an d the pwm o utputs a r e pwm0 (p0.1 ) , pwm1 (p 1.6), pwm2 (p1.7) and pwm3 (p0.0). the initial pwm outputs level corre s p ondin g ly depe nd o n the prhi l e vel set prio r to the chip reset. when prhi set to high, pwm output will initialize to high after chip reset; if prhi set to low, pwm output will be initialize to low after c h ip reset. the n79e 82 5 serie s su pp ort 10-bit s do wn co unter wi th cpu clo ck a s its input. the pwm count er clo ck, has the sam e frequen cy as the clock so urce f cpu = f osc . when the cou nter re ach es un derfl ow it will automatic rel oade d from counter regi st er. the pwm freque ncy is given by: f pw m = f cp u / (pwmp+ 1), whe r e pwmp is 10-bit s re g i ster of pw m p h.1, pwmph.0 and p w mpl.7~p w m p l.0. the co unter registe r will b e loaded with the pwmp registe r value whe n pwmrun, load an d cf are equal to 1; th e load bit will be automatically cleare d to zero on the next clock cycle, and at the same time the counter regi ster value will be loaded to th e 10 bits down co unter. cf flag is 10-bits do wn counter reaches underflow, the cf flag will be cl eared by software. the pul se wi dth of ea ch pwm outp ut is dete r mine d by the co mpare re gist ers of pwm0 l throu g h pwm3l a nd pwm0 h thro ugh pwm 3h. when p w m comp ar e re gi ster i s greate r than 10 -bit s counte r regi ster, the pwm outp u t is lo w. loa d bit has to be se t to 1 for alteration of p w mn width. after the new val u e s a r e written to t he pwm n re gisters, an d if load bit i s se t to 1, the ne w pwm n val ues will be loade d to the pwmn re gisters u pon the next underfl ow. the p w m output hig h pulses widt h is given by: t hi = (pwmp ? pwmn+ 1 ). notice, if comp are regi ste r is set to 000h, the pwmn output will st a y at high, and if com p a r e regi ster i s set to 3ffh, the pwmn o u tput will stu ck at low until there is a cha n ge in the com p a r e re gi ster . N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 99 - revision a02 10-bits counter compare register counter register pwm0 register pwmrun f cpu + - compare register pwm1 register + - compare register pwm2 register + - compare register pwm3 register + - pwm1i pwm2i pwm3i pwm0i pwm0b pwm1b pwm2b pwm3b 0 1 0 0 0 1 1 1 + - cf x x x x y y y y > > > > load pwmp register bken brake control bl ock bpen bkch clrpwm cl ear counter bkps brake pin (p0.2) bkf 0 1 brake flag e na bl e e x t er na l b r a k e p i n ( b pe n, bk c h ) = ( 1 , 0 ) p0 . 2 = 0 p0 . 2 = 1 p0.1 p1.6 p1.7 p0.0 pw m 0 pw m 1 pw m 2 pw m 3 pi n 2 0 ( p 0. 1) pi n 3 ( p 1. 6) pi n 2 ( p 1. 7) pi n 1 ( p 0. 0) figure 23-1: n79e825/824 pwm block diagram N79E825A/824a/823a/822a data sheet - 100 - the n79e82 5 se rie s devi c e s su ppo rt bra k e fun c tio n whi c h can be activated by softwa r e or extern al pin (p0.2). the bra k e f unctio n is co ntrolled by the pwm c o n 2 re giste r . the setting and detail s descri ption of software bra k e and external pin bra k e can be foun d at the brake conditio n table at the s f r se ct ion. as for extern al brake, the use r p r og ram can poll th e bra k e fla g (b kf) or en able pwm?s brake interrupt to determine whe n the external brake pin is asse rt ed and cau s es a bra k e t o occur. the brake pin (p0.2) can b e set to trig g er the b r a k e function by either lo w or hi gh level, by clea ring or setting the pwmcon2.6 (bkps) bit respectively. the detail s description of varies brake f unctions can be found in the bra k e condition tabl e . since th e brake pi n bein g asse rted will automatic a lly clear the run bit of pwm c o n 1.7 and bkf (pwm co n3. 0) flag will be set, the user program can poll this bit o r enable pwm?s bra k e int e rrupt to determi ne when the brake pin causes a brake to occur. the o t her method for detectin g a brake cau s e d by th e bra k e pin woul d be to ti e the bra k e pi n to one of the external i n terrupt pin s . this latte r approa ch is need ed if the brake sign al is of insuffi cient length to ensure that it can be capt ured by a polling ro utin e. when, after being asserted, the co ndition cau s i ng the brake is removed, the pw m outputs go to whateve r sta t e that had i mmediately p r ior to th e b r ake. t h is m e ans th at in order to go from bra k e b eing asse rted to having th e pwm r un without goin g through an i ndeterminate state, care must be taken. if the brake pin ca uses brake to be asserted, the fo llowing prototype code will allow the pwm to go from brake and then run smoothly afte r bra k e i s rele ase d . N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 10 1 - revi si on a0 2 1 . pwm n out put =pwmnb 2. h/ w set b kf=1 & pwmrun=0 3 . s / w sw i t ch t o s / w br ake ( b k e n,bpe n,bkch)=(1,0, 0) 4 . set pwmn compar a t or out put = pwm n b or a give n pat t e r n 1. cl ear 10- bit pwm coun t er c l rpwm =1 2. rel oad pwm p & pw m r egi st er s 3. enable br ake f unct i on ( b k e n,bpe n,bkch)=(1,1,0 ) 1. cl ear bkf pwm out put =pwm com par at or out put 2. re- s t a r t pwm runni ng by set t i ng p w mr un = 1 ; l o a d b it= 1 start end i n it iali z e pwm function 1 . set pwm cont r o l regs 2 . set pwm b r ake out put p a t t e r n ( p wm nb) 3 . ena ble br ake f unct i on ( b k e n,bpe n,bkch)=(1,1, 0) pwm starts running brake occurs? yes no br ake pi n i s asser t ed ? no yes figure 23-2: pwm brake function N79E825A/824a/823a/822a data sheet - 102 - 24 analog-to-digital conve r ter the adc co ntains a da c whi c h co n v erts the con t ent s of a su ccessive ap p r oximation re gister to a voltage (vda c) which is compa r ed to the analo g inp u t voltage (vin). the outpu t of the comparato r is fed to the succe ssive ap proximatio n control l ogi c whi c h controls the su ccessive ap pro x imation regi ster. a co nversi on is in itiated by setting adcs in the adccon registe r . the r e are two tri ggeri ng method s by adc to sta r t co nversi on, eith er by purely software start or extern al pi n stadc trig gerin g. the softwa r e start mo de i s u s ed to tri g ger a dc con v ersio n rega rdless of adcco n .5 (a dcex) bit is set or cleared. a conv ersion will start simply by s e tting t he adccon.3 (a dcs ) bit. as for the external stadc pi n trigg e r ing mode, adcco n .5 (a dcex) bit ha s to be set an d a rise ed ge pulse ha s to apply to stadc pin to trigger the adc conve r sion. for the rising e dg e triggeri ng method, a minimum of a t least 2 machine cy cle s symmetrical p u lse i s req u ired. the low-to-hi gh tran sition of stadc is recogni ze d at the end of a machi ne cy cl e, and the co nversi on comm en ce s at the begin ning of the next cycle. whe n a co n v ersio n is ini t iated by sof t ware, the conve r si on st arts at the be ginnin g of the machin e c ycle which follows the in st ru ction that set s adcs. adcs i s a c tually implem ented with tpw flip-flo ps : a com m an d flip-flop whi c h i s affecte d by set operation s , and a statu s flag whi c h i s a c cesse d duri ng rea d ope rations. the next two machi ne cy cl es are used to initiate the conve r ter. at the end of t he first cycle, the adcs status flag is set end a value of ?1? will be returned if the adcs fl ag is read wh ile the conversion is in prog re ss. sampling of the analo g input co mm en ce s at the end of the se co nd cy cle. duri ng the ne xt eight mach ine cy cle s , the voltage at t he p r eviou s ly sele cted pin of one of ana log inp ut pin is sam p le d, and this input voltage should be sta b l e in order to obtain a usef ul sampl e . in any event, the input voltage sl ew rate must be le ss than 10v /ms in orde r to prevent an und efined re sult. the succe s si ve approxim a t ion cont rol lo gic first sets t he mo st signi ficant bit and clea rs all oth er bits in the succe s si ve approxim ation regi ster (10 0000 00 00b) . the ou tput of the d a c (50% full scale ) i s comp ared to the input voltage vin. if th e input voltag e is greater t han vda c , then the bit re mains set; otherwise if is cleared. the succe s si ve approxima t ion cont rol lo gic no w sets the next most significa nt b i t (11 000 0 0 000b o r 01 000 0 000 0b, depe ndin g on the pre v ious re sult ), and the vdac is co mpa r ed to vin ag ain. if the input voltage is g r eate r the n vdac, th e n the bit rem a ins set; oth e r wi se it i s cl e ared. t his proce s s is repe ated until all ten bits have been tested, at which stage the re sult of the c onversio n is hel d in th e su ccessive a pproxim ation regi ster. the conv e r si on ta ke s four ma chine cy cle s p er bit. the e nd of th e 10 -bit conv ersi on i s flag ged by cont rol bit adcco n .4 (a dci ). the u ppe r 8 bits of the result are hel d in sp eci al functio n re gist er adch, a n d the two re maining bits are h e ld in a d cco n .7 (adc.1) an d adcco n .6 (adc.0 ) . the use r may ign o re the two le ast signifi cant bits in adccon and use the adc as an 8-bit converte r (8 u pper bit s in adch). in any event, the total actual con v ersio n time is 52 machin e cycle s . adci will be set and the adcs statu s flag will be re set 52 cycle s after the adcs is set. control bits adcco n .0 an d adccon.1 are used to control an an alog multiplex er whi c h sele cts o ne of 4 analog cha nnel s. an adc conversion in p r o g ress is u naffe cted by an e x ternal or softwa r e adc start. the result of a co mpleted co nver si on remain s unaffecte d provide d adci = logic 1; a ne w adc conversion alr eady in pro g ress is ab orte d wh en th e id le or po wer d o wn mod e is entere d . the re sult of a completed conversion (adci = l ogi c 1) remain s unaffecte d when enteri ng the idle mode. N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 10 3 - revi si on a0 2 dac ms b lsb succ es siv e appr ox im ation r egis t er vin + - c o m para t or start ready (stop) suc ces si ve app r oxi m ati o n c ontr ol logi c v da c figure 24 -1: suc c essive approxi m ation adc 24.1 adc resol u tion and analog supply : the adc circuit has its own supply pins (av dd and avss) and one pins (vref + ) connected to each end of the dac?s resi stance-l add er that the avdd and vref + are connected to vdd and avss is connected to vss. the ladder has 1023 equally spac ed taps, separated by a re si stance of ?r?. the first tap is located 0.5r above avss, and the last tap is lo cated 0.5r below vref+. thi s gi ves a total ladde r resi st ance of 10 2 4r. this st ructu r e en su res that the dac i s mo n otonic and result s in a symmetri c al quanti z ation error. for input voltages between vss and [(vref+) + ? lsb ], the 10-bit result of an a/d conversi on will be 0000 0000 00 b = 000 h. for input volta ges b etwe en [(vr ef+) ? 3 / 2 lsb] and vref+, the re sult of a conversi on will be 1111111111b = 3ffh. vref+ and a vss may be bet ween avdd + 0.2v and vss ? 0.2 v. vref+ should be positive with respect to vss, and the input voltage (vin) should be between vref+ and vss. the re sult ca n alway s be calcul ated fro m the followin g formula: re sult = vref vin 1024 + or res u lt = vdd vin 1024 N79E825A/824a/823a/822a data sheet - 104 - 10-bits adc block adc0(p0 .3) ad c[9:0] adci adcs vdd vref+ vss aadr[1 : 0] analog input multiplexer 0 1 p1.4 adcex adcen adc1(p0 .4) adc2(p0.5) adc3(p0.6) avss av dd rc_clk/2 1 0 rcclk f cpu /4 figure 24-2: the adc block diagram N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 105 - revision a02 25 i2c serial control the i2c bu s use s two wire s (sda a nd scl) to tra n sfe r informatio n betwe en devi c e s co nne cte d to the bus. th e mai n feature s of the bu s are: ? bidire ctiona l data transfe r betwee n ma sters and sla v es ? multimaste r bus (n o ce ntral maste r) ? arbitration betwe en sim ultaneo usly transmitting m a sters withou t corrupti on of serial d a ta o n the bus ? serial cl ock synch r oni zati on allo ws d e vice s with diffe rent bit rate s to comm uni ca te via one serial bus ? serial cl ock synch r oni zati on ca n be u s ed as a h and sha k e me ch a nism to susp end an d re su me se rial trans fer ? the i2c bu s may be use d for test and di agno stic p urp ose s t buf st o p sda scl start t hd;sta t low t hd;dat t high t f t su;dat repeated start t su;sta t su;sto stop t r figure 25 -1: i2c bus timing the device? s on-chi p i2c logic provide s the serial i n terface that meets the i2 c b u s s t an da r d mo de spe c ification. the i2c lo gic ha ndle s bytes tran sf e r autono mou s ly. it also kee ps track of seri al transfe rs, and a status regi ster (i2stat u s) refle c t s the statu s of the i2c bu s. the i2 c po rt, scl a nd s d a are at p1.2 and p1.3. w hen the i/o pi ns a r e used as i2 c p o rt, u s er mu st set the pins to logic high i n advance. whe n i2c po rt is enable d by setting ens to high, the internal states will be controlled by i2co n and i2c logi c har d w are. once a new stat us code is gen erated and store d in i2s tatus, the i 2 c inte rrupt fl ag (si) w ill b e set automa t ically. if both ea and ei2 c a r e al so in logic high, the i2c inte rru pt is req ue s te d. the 5 mo st significant bit s of i2st atus store s the i nternal state code, t he lo we st 3 bits a r e al wa ys ze ro and the co ntent keep s sta ble until si is cl eare d by s o ftware. 25.1 sio port the sio port is a serial i/o port, which supports all transfer modes from a nd to the i2c bus. the sio port ha ndles byte transfers au tonomously . t o enable this port, th e bit ens1 in i2con should be s e t to '1'. th e cpu inter f ace s to the sio port through the following six special func tion re gister s: i2con (con trol re g i ster , c0 h), i2 s t a t u s (stat u s regist er , b d h ) , i2da t (da t a registe r , bc h), i2addr (addres s register s, c1h), i2clk (clock rate registe r beh) and i2timer (t imer coun ter register , bfh). the sio h/w inte rfaces to the i 2 c bus via two pins: sda (p1.3, serial data line) and scl (p1.2, serial clock line) . pull up resistor is need ed for pin p1.2 and p1.3 for i2c opera tion as these ar e 2 open drain p i ns. N79E825A/824a/823a/822a data sheet - 106 - 25.2 the i2c co ntrol registers: the i2c ha s 1 control re gister (i2 c o n ) to control th e transmit/re c e i ve flow, 1 data registe r (i2 d at) t o buffer the tx/ r x data, 1 st atus regi ster (i2status ) to cat c h the st ate of tx/rx, reco gni zabl e slave address register for slave mode u s e an d 1 clock rate control blo c k for ma ster mode to gen erate the variable b aud rate. 25.2.1 the addres s registers, i2addr i2c port is eq uippe d with one slave add ress regi ster. the conte n ts of the regi st er are irrelev ant when i2c is in master mod e. in the slave mode, the se ven most sign ificant bits must be loade d with the mcu? s own slave add re ss. the i2 c h ardwa re will re act if the con t ents of i2addr are mat c hed with the received slave ad dre s s. the i2c po rt s su ppo rt the ?gene ral ca ll? function. if the gc bit is set the i2c port1 hardware will respon d to general call a ddre s s (0 0h). clear gc bit to disabl e ge neral call fun c tion. when gc bit is set, the i2 c is in slav e mode, it ca n be re ceiv e d the gene ra l call addres s b y 00h after master send general call addres s to i2c bus, then i t w ill follo w status of gc m ode. if it is in master mode, the aa bit must be cleared w h en it w ill send general call address of 00h to i2c bus. 25.2.2 the data re gister, i2dat this registe r contai ns a by te of serial d ata to be transmitted or a byte which h as just be en received. the cpu can read from o r write to this 8-bit dire ctly addressa ble sfr while it is not in the process of shifting a byte. this occurs whe n sio is in a defined state and the serial inte rrupt flag (si) is set. data in i2dat rem ains sta ble a s long as si bit is se t. while data is being shifted o ut, data on the bus is simultan eou sl y being shifted in; i2dat always contain s the last data byte presen t on the bus. thus, i n the event of arbitration lo st, the tr ansiti on from ma ster tra n smitter to slave re ceiver i s mad e with th e corre c t data i n i2dat. i2dat an d th e ackn owl edg e bit form a 9 - bit shift regi ster, the a c kno w led ge bit i s controlled by the sio hard w a r e an d cannot be acce ssed by t he cpu. serial data is shifted through the ackn owl edg e bit into i2dat on the risin g edg es of serial clo c k pul se s on t he scl lin e. whe n a byte has b een shif ted into i2dat, the serial data is available in i2dat, and t he ackno w led ge bit (ack or nack ) is returne d by the control lo gic duri ng the ninth clock pulse. serial d a ta is shifted out from i2dat on the falling edge s of scl clo ck pulses, an d is shifted into i2 dat on the risin g edg es of scl clo ck pulses. i2dat.7 i2dat.6 i2dat.5 i2dat.4 i2dat.3 i2dat.2 i2dat.1 i2dat.0 i2c data register: shifting direction N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 107 - revision a02 25.2.3 the control register, i2con the cpu ca n read from and write to this 8-bit, dire ctly addressable sfr. tw o bits are a ffected by hard w a r e: th e si bit is set whe n the i2c ha rd wa re req u e s ts a se rial inte rrupt, and the sto bit is clea red whe n a stop con d ition is present on the bu s. the sto b i t is also cl eared wh en ens = "0". ensi set to enable i2c seri al fu nction blo ck. whe n ens = 1 the i2c se ria l function ena bles. t he port latch e s o f sda1 and scl1 mu st be set to logic hi gh. sta i2c start f l ag. setting s ta to logi c 1 to enter ma ster mo de, the i2c ha rd wa re sen d s a start or re peat start con d ition to b u s when the bus i s free. sto i2c stop fl ag. in maste r mode, setting sto to tra n smit a sto p conditio n to bus th en i2c ha rd wa re will che c k th e bu s conditi on if a stop con dition i s d etected this f l ag will be clea red by ha rdware auto m atically. in a slave mode , setting sto resets i2c h a rd wa re to the defined ?not add re sse d? sl ave mo de. this m e ans it is no longer in the slave receiver mo d e to receive data from the maste r tran smit device. si i2c port 1 interrupt flag. when a new sio s t ate is pre s ent i n th e s1sta re gi ster, the si flag is set by hardware, a nd if the ea and ei 2c bits are both set, the i2c1 interrupt is requ este d. si must be cl ea red by soft wa re. aa asse rt ackn owle dge con t rol bit. whe n aa=1 prio r to addre ss or data re ceived, an ackno w le dge d (lo w level to sda) will b e returned d u r ing the a c kn owle dge clo c k pul se on the scl line whe n 1.) a slave is ackno w led g ing the address sent fr om master, 2.) the receiver devi c e s are a c kn owle dging th e data sent by transmitter. wh en aa=0 prio r to address o r d ata re ceived, a not a c kno w ledge d (hi gh l evel to sda) will be retu rn ed du rin g the ackno w le dge cl ock pul se on the scl line. 25.2.4 the status register, i2status i2status is an 8-bit rea d -only re giste r . the three l east si gnifica nt bits are al ways 0. the five most signifi cant bit s contain th e status co de. there are 23 possi bl e statu s code s. whe n i2status contai ns f8h, n o seri al interrupt i s req u e s ted. all other i2s tatus value s corre s po nd to define d s i o state s . whe n ea ch o f these states is ente r ed, a status i n terrupt is requ ested ( si = 1) . a va lid s ta tus c o de is pre s ent in i2status one machin e cycle after si is set by hard w are an d is stil l present one machin e cycle afte r si has b een reset by software. 25.2.5 the i2c clock baud rat e bits, i2clk the data bau d rate of i2 c is dete r mine s by i2clk r egiste r when sio is in a maste r mod e . it is not important when sio is in a slave mode. in the slave modes, sio w ill automati c ally synchronize with any clo ck fre quen cy up to 400 khz from master i2 c d e vice. the data bau d rate of i2 c setting i s dat a baud rate of i2c = f c p u / (i2clk +1 ). the fcpu =f osc/4. if fosc = 16m hz, the i2 clk = 40 (2 8 h ), so data baud rate of i2c = 1 6mhz/(4x (4 0 +1 )) = 97.56kbits/ s e c . the blo c k diagram is a s below figu re. N79E825A/824a/823a/822a data sheet - 108 - figure 25 -2: i2c timer count block diagram 25.3 modes of operation the o n-chip i2c po rts su pport five o p eration mod e s , ma ster t r a n smitter, m a ster re ceive r , slave transmitter, slave receiver, and gc call. in a given ap plicatio n, i2c port may operate as a mast er or as a sla v e. in the slave mode, the i2c port hard w a r e loo ks for its o w n slave add re ss and the ge neral call ad d r ess. if one of these add re sses i s detected, and if the slave is willin g to receive or transmit data f r om/to master(by setting the aa bit), acknowledge pulse will be transmi tted out on the 9th clo ck, hence an interrupt is requested on both maste r and sl ave device s i f interrupt i s enabl ed. wh en the micro c ontrolle r wi sh es to be com e the bus maste r , the h ard wa re wait s until th e bu s is free bef o r e the ma ster mode i s ent ered so that a po ssi ble slave a c tion i s not inte rru p t ed. if bus arbitration i s lo st in the ma ster mod e , i2c po rt switch es to the slave mod e immediately a nd ca n dete c t its own sl ave addre s s in the same se rial transfe r. 25.3.1 master tran smitter mode serial dat a o u tput throu g h sda while s c l o u tputs th e se rial clo c k. the first byt e tran smitted contai ns the slave ad dre s s of the receiving d e vice (7 bit s ) a nd the d ata dire ction bit. in this ca se the data direction bit (r/w) will be l ogic 0, an d it is represented by ?w? in the flow diagrams. thus the first byte transmitted is sla+w. serial data is transmitted 8 bi ts at a time. after each b y te is transm i tted, a n ackno w le dge bit is receive d . start and stop conditi ons a r e outpu t to indicate the begin n ing and the end of a se ria l transfe r. 25.3.2 master re c e iver mode in this case the data dire ction bit (r/ w) will be lo gic 1, and it is repre s e nted by ?r? in the flo w diagram s. thus the first by te transmitted is sla+r. serial data i s receive d via sda while scl outputs the se rial clo c k. serial d ata is re ceive d 8 bits at a time. after each b y te is re ceive d, an a ckn owl edge bit is tran smitted . start and stop con ditions are outp ut to indicate the begin nin g and e nd of a se ria l trans fer. 25.3.3 slave recei ver mode serial data a nd the se rial clo ck a r e re ceived thro u g h sda and scl. after each byte is received, an ackno w le dge bit is transm itted. start and st op con dition s are re co gnized as th e be gi nning and end of a se ri al tran sfer. a ddre s s recog nition is per f o rme d by ha rdware after reception of the sl ave address an d dire ction bit. N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 109 - revision a02 25.3.4 slave transmitter mode the first byte is re ceive d and h andle d as in th e sla v e receiver mode. howe ver, in this mode, the direction bit will indicate that the transf e r direction is reversed. serial data is transmitted via sda while the se rial clo c k is i nput th roug h scl. start a nd stop co nditi ons are reco gnized a s th e begin n ing and en d of a seri al tran sfer. 25.4 data transfer flo w in five operating modes the five operating mode s a r e: maste r /tra nsmi tter, m a ster/ r e c eive r, slave/transmitte r, slave/receiver an d g c call. bits sta, sto and aa in i2co n regi ster will dete r mine the n e xt state of the sio ha rd ware after si flag is clea re d. upo n co m p lexion of the new a c tion, a ne w status cod e wil l be up dated and the si flag will be se t. if the i2c in terrupt control bits (ea a nd ei2c) a r e enabl e, approp riate a c tion or software b r an ch of the new st at us code can be perfo rme d in the interru pt service routine. data tran sfe r s in ea ch mo de are sho w n in the followi ng figure s . *** lege nd fo r the followin g five figures: 08 h a start has been transmitted. ( st a , s t o , si , aa) = ( 0 , 0 , 0 , x) s l a + w w i l l be t r an s m i t t ed; ack bit will be received. 18 h s l a + w ha s be en t r an s m i t t e d; ack has been received. l a s t s ta te last act i on i s don e n ext s et t i ng i n s 1c o n e x p ec t e d nex t ac t i on next act i on i s don e ne w s t a t e s of t w ar e' s a c c e s s t o s 1d a t w i t h r espec t t o " e x pect ed next act i o n" : software should load the data byte (to be transmitted) into s1dat before new s1con setting is done. ( 1) d at a by t e w i l l b e t r ansm i t t ed: ( 2) s la + w ( r ) w i l l be t r ans m i t t ed : s o f t w a r e s hou l d l o ad t he s la + w / r ( t o be t r ans m i t t ed ) i nt o s 1d a t bef o r e new s 1c o n s et t i ng i s don e. ( 3) d at a by t e w i l l b e r ec ei v ed : s o f t w a r e c an r e ad t he r e c ei v ed d at a byt e f r om s 1d a t w hi l e a n ew st at e i s ent er ed. figure 25-3: legen for the following four figures N79E825A/824a/823a/822a data sheet - 110 - figure 25-4: master transmitter mode N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 111 - revision a02 figure 25 -5: mas ter receiver mod e N79E825A/824a/823a/822a data sheet - 112 - figure 25-6: slave transmitter mode N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 113 - revision a02 figure 25-7:slave receiver mode N79E825A/824a/823a/822a data sheet - 114 - figure 25-8:gc mode N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 115 - revision a02 26 icp(in-circuit pro g ram) flash p r ogram the contexts of flash in n79e825 serie s are empt y by default. u s er mu st pro g ram the flash eprom by external writer devi c e or by icp (in-ci rcuit program ) tool. in the icp tool, the user must take note of ic p?s program pi ns u s ed i n system boa rd. in some appli c ation ci rcuit s , the pins are lo cat ed at p1.5, p0.4 and p0.5, as below figure. du ring icp prog ram m ing , p1.5 must be set to hig h voltage (~1 0 .5v), and keepin g this v o ltage to u p d a te co de, data and/o r configure co nfig bits. after pro g ra mmin g compl e tion, the high voltage of p1.5 should b e relea s e d . so, it is highly recom m en ded use r po we r off then po wer on after i c p program ming ha s compl e ted on the system b oard. upo n entry in to icp progra m mode, all pin will be se t to quasi-bi di rectio nal mod e , and output to leve l ?1?. the n79e8 2 5 se rie s sup p ort prog ramm ing of fla s h eprom ( 16 k/8k/4k/2 k by tes ap flas h eprom) and nvm dat a memo ry ( 25 6 bytes). user ha s the option to pro g ram the ap flash an d nvm either individually or both. n79e82x p0 . 5 vdd p0.4 p1 . 5 / rs t [3 ] vs s to application vpp cl o c k vdd da t a vss icp programmer vcc jum per [1 ] ic p c onnector system board icp power jumper t o appli cati o n to application not e : 1. cir c uit r y separ at ion is opt i onally nee ded bet ween i c p an d ap plicat ion dur ing i c p oper at i on . 2. resi st or is opt i onal by appl icat i on 3. voltage of p1.5 is up to about 11v during icp peration [2] [2 ] [2] [2 ] figure 26 -1: appl ication circuit of icp note : 1. when using ic p to upgrad e cod e , the p1.5, p0.4 and p0.5 must b e taken w i thin de sign sy stem boa r d . 2. after p r ogra m finished b y icp, to suggest s y ste m po w er must p ower off and rem ove icp connector then p o w er on. 3. it is recom m e nde d tha t use r performs era se f unc tio n an d progra m m ing confi gure bi ts conti nuo usl y w i thout a n y in te rrupti on. N79E825A/824a/823a/822a data sheet - 116 - 27 config bits the n79e82 5 se ries have two co nfi g bits (co n fi g1, co nfi g2) that mu st be define at powe r up and ca n not be set after the program start of execution . those featu r es a r e co nfig ured throug h the use of two flash eprom byte s, and the fla s h epro m can be p r og ra mmed an d verified repe atedly. until the cod e insi de the flash eprom is co nfirmed ok, the co de can be prote c ted. the prote c ti on of flash eprom (co n fig2 ) and those operatio ns on it are describ ed belo w . the data of these bytes may be read by the m o vc in stru ction at the add resse s . 27.1 config1 bit name function 7 - reserved. 6 rpd re set pin disable bit: 0: enable re set functio n o f pin 1.5. 1: disable reset function of pin 1.5, and it to be used as an input port pin. 5 prhi port re set hi gh or lo w bit: 0: port reset to low s t ate. 1: port reset to high state. 4 bov brownout vol t age select bi t: 0: brown out detect voltag e is 3.8v. 1: brownout detect voltage is 2.5v. N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 117 - revision a02 continued bit name function 3 - reserved. 2 - reserved. 1 fosc1 cpu oscillator type select bit 1 0 fosc0 cpu oscillator type select bit 0 oscillator configuration bits: f o sc1 f o sc0 osc sou rc e 0 0 4mhz ~ 20mhz crystal 0 1 internal rc oscillator 1 0 reserved 1 1 external oscillator in xtal1 27.2 config2 c7: 16k/8k/ 4k/2k flash eprom lo ck bit this bit i s u s ed to protect the cu stome r ' s prog ra m co de. it may be set after the prog ram m er finishe s the program ming an d verifies sequ en ce. once this bit is set to l ogic 0, both t he fla s h ep rom data and confi g regi sters can not be acce ssed a gain. c6: 256 byt e data flash eprom l ock bit this bit is u s ed to prote c t the cu stome r ' s data c ode. it may be set after the pro g ramm er fini shes the prog ram m ing and verifie s seq uen ce. o n ce thi s bit is set to logic 0, both the d a ta flash eprom a n d co nfig reg i sters can not be acce ssed again. N79E825A/824a/823a/822a data sheet - 11 8 - bit 7 bit 6 function d e scriptio n 1 1 both security of 16kb/8kb/4kb/2kb program code and 256 bytes data area are unlocked. they can be erased, programmed or read by writer or icp. 0 1 the 16kb/8kb/4kb/2kb program code area is locked. it can?t be read by writer or icp. 1 0 don?t support (invalid). 0 0 both security of 16kb/8kb/4kb/2kb program code and 256 bytes data area are locked. they can?t be read by writer or icp. N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 119 - revision a02 28 electrical characte r ist i cs 28.1 absolute maximu m ratings symb o l par amet e r min max unit dc po we r supply vdd ? vss -0.3 + 7 .0 v input voltage vin vss-0.3 vdd+0.3 v operating te mperature ta -40 +85 c storage te m peratu r e tst -55 +15 0 c maximum current into v dd - 120 ma maximum cu rre nt out of v ss 120 ma maximum current su ck by a i/o pin 25 ma maximum current sourced by a i/o pin 25 ma maximum current suck by total i/o pins 75 ma maximum current sourced by total i/o pins 75 ma note : ex posure to conditions bey o nd those lis ted under absolute m a x i mum ratings ma y adversel y af fects the lift and reliability N79E825A/824a/823a/822a data sheet - 120 - 28.2 dc ele c t r ic al ch ar acte r i s tics (v ss = 0v, t a = - 40~85 c, unless ot herwise specif ied; typical value is t e st at ta=2 5 c) specific ation p a ra me ter s y m bol min. t yp. max. unit t est con di t ions 2. 7 5. 5 v v dd =4.5v ~ 5.5v @ 20mhz v dd =2.7v ~ 5.5v @ 12mhz operat in g volt age v dd 3. 0 5. 5 program a nd e r ase dat a f l ash. 15 25 ma n o loa d , /r st = v ss ,v dd = 5.0v @ 20mhz i dd1 5. 5 8 ma n o loa d , /r st = v ss , v dd = 3.0v @ 12mhz 19 29 ma v dd = 5.0v @ 20mhz, no load, /rst = v dd , run nop operat in g curr ent i dd2 5. 5 9 ma v dd = 3.0v @ 12mhz, no load, /rst = v dd , run nop i idle 11. 5 15 ma no lo ad, v dd = 5. 5v @ 20mhz id le c u rre n t 3 6. 5 ma no lo ad, v dd = 3. 0v @ 12mhz i pw dn 1 10 a no lo ad, v dd = 5. 5v @ disable bov function p o we r d o wn c u r r e n t 1 10 ua no lo ad, v dd = 3. 0v @ disab l e bo v f unct i on i nput curre nt p0, p1, p2 i in1 -50 - + 15 a v dd = 5.5v, 0 N79E825A/824a/823a/822a data sheet - 122 - *2. xtal 1 is a cmos inp u t. *3. pins of p0, p1 an d p2 can source a trans ition cur r ent w h e n the y a r e being ext e rna lly d r iven fro m 1 to 0. t h e transition current reaches its maximum value when vin approximate s to 2v. 28.3 the ad c c onvert e r d c elect r ical c h a r acte r istics (vdd ? vss = 3.0~5v, ta = -40~85 c, fosc = 20mhz, unless ot herwise specif ied.) specific ation p a ra me ter s y m bo l min. t yp. max. unit test conditions analog input avin v ss -0.2 v dd +0.2 v adc clock adcclk 200khz 5mhz hz adc circuit input clock conversion time t c 52t adc [1 ] us differential non-linearity dnl -1 - +1 lsb integral non-linearity inl -2 - +2 lsb offset error ofe -1 - +1 lsb gain error ge -1 - +1 % absolute voltage error ae -3 - +3 lsb notes : 1. tad c : the pe riod time of adc input clock. 28.4 the comp ar ator e l ectri c a l cha r a c t eristics (vdd ? vss = 3.0~5v, ta = -40~85 c, fosc = 20mhz, unless ot herwise specif ied.) specification p a ra me ter s y m bol min. t yp. max. unit test conditions comm on mo de ran ge comp arator in puts v cr 0 v dd -0.3 v comm on mo de reje ction ratio cmrr -50 db res p onse time t rs - 30 100 ns comp arator e nable to outp u t valid time t en - 1 5 us input leakage current, comp arator i il -10 0 10 ua 0< v in N79E825A/824a/823a/822a data sheet - 124 - 29 package dimensions 29.1 20-pin sso p 0 0.002 0.197 0.291 7.80 0 7.40 8 8.20 5.30 b e d c 6.90 5.00 a1 a2 a 5.60 7.50 7.20 2.00 1.85 8 0.323 0.307 0.073 0.079 0.220 0.272 0.295 0.283 0.209 min. dimension in inch symbol dimension in mm min. nom max. max. nom 0.05 e l l1 y 0.009 0.015 0.004 0.010 0.021 0.030 0.050 0.004 0.22 0.38 0.09 0.25 0.65 0.0256 0.55 0.75 1.25 0.10 h e 0.95 0.037 1.75 1.65 0.065 0.069 1 20 d e e y b a1 a2 a seating plane dteail a l l1 detail a seating plane e h 10 11 b figure 29 -1: 20 - p in ssop N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 125 - revision a02 29.2 20-pin sop l o c e h a1 a e b d seating plane y 0.25 gauge plane e 1 20 11 10 7.60 0.32 0.51 0.30 e c b a1 7.40 0.23 0.33 0.10 0.299 0.013 0.020 0.012 0.291 0.009 0.013 0.004 max. dimension in mm 2.65 a symbol min. 2.35 dimension in inch 0.104 min. 0.093 max. control demensions are in milmeters . 1.27 0.10 10.65 l t y h 08 0.40 10.00 e 1.27 bsc 0.050 0.004 0.419 0 0.016 0.394 8 0.050 bsc e d 12.60 13.00 0.496 0.512 N79E825A/824a/823a/822a data sheet - 12 6 - 29.3 20-pin dip 1.63 1.47 0.064 0.058 symbol min nom max max nom min dimension in inch dimension in mm a b c d e a l s a a 1 2 e 0.060 1.52 0.175 4.45 0.010 0.125 0.016 0.130 0.018 0.135 0.022 3.18 0.41 0.25 3.30 0.46 3.43 0.56 0.008 0.120 0.375 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.255 0.250 0.245 6.48 6.35 6.22 9.53 7.62 7.37 7.87 0.300 0.290 0.310 2.29 2.54 2.79 0.090 0.100 0.110 b 1 1 e e 1 1.026 1.040 20.06 26.42 01 5 0.075 1.91 0.355 0.335 8.51 9.02 15 0 seating plane a e 2 a c e base plane 1 a 1 e l a s 1 e d 1 b b 20 11 0 11 figure 29-2: 20l pdip 300mil N79E825A/824a/823a/822a data sheet pub lica tio n relea s e da te: aug 0 5 , 2 010 - 127 - revision a02 30 revision history versio n date pag e descri ptio n a1 dec. 03, 2009 - initial issued a2 aug. 05, 2010 page 124 modify ssop20 package. important notice nuv oton products are ne ither inten de d nor w a rra n t ed fo r usag e in s y stems or equipment, an y malfunc tion or failure of w h i c h ma y c a use loss o f human life, bodily injur y or sev ere pr operty damage. su ch applicatio ns are deem ed, ?insec ur e usag e?. insecure us age includes , but is not limited to: e q uipment for surgical implementa tion, atomic energ y contr ol instrumen t s, airplane or space sh i p instrumen t s, the con t ro l or operatio n of d y namic, brake or sa fe t y s y stems designed for v e hicular use, traffic signa l instruments, all t y pes of safe t y de v i ces, and other a pp lications inte nded to s up port or su sta i n life. all insecure usag e shall be made at c ustomer?s ri sk, and in th e ev ent that third par t ies la y claims to nu v oton as a result of c ustomer?s insec ure us age, c ustomer s ha ll indemnif y the damages and liabilities thus incurred b y nu v o ton. |
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