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december 2012 doc id 023945 rev 1 1/28 AN4207 application note getting started with stm32f37x/ 38x sdadc (sigma-delta adc) introduction the stm32f37x series of microcontrollers combines a 32-bit arm cortex-m4 core with a dsp and fpu instructions running at 72 mhz with advanced analog peripherals. this series introduces the combination of a cortex-m4 core with a precise 16-bit sigma- delta adc. this document outlines the main features of the sdadc and shows how the sdadc can be used in various application cases. by way of example, four application cases are presented in this document: 1. temperature measurement using pt100 2. pressure measurement using mpx2102a 3. wave recorder 4. electrocardiogram (ecg) acquisition to help you get started quickly, the four application cases are implemented in c language and are available as part of the stm32f37x dsp and standard peripherals library package stm32f37x_dsp_stdperiph_lib and the stm32373c-eval demonstration firmware package stm32373c-eval_fw please note that this document is not intended to replace the sigma-delta analog to digital converter (sdadc) section in the stm32f37xx/stm32f38xx reference manual rm0313. all values given in this document are guidance only. please refer to the related datasheet to get guaranteed and up-to-date values. table 1. applicable products type part numbers microcontrollers stm32f37x, stm32f38x www.st.com
contents AN4207 2/28 doc id 023945 rev 1 contents 1 basics of sigma-delta converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 overview of 16-bit sdadc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1.1 clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1.2 input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1.3 sdadc voltage references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.4 calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.5 matching impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.6 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 sigma-delta (sd) vs. successive approximation register (sar) analog-to-digi tal converters . . . . . . . . . . . . . . . . . . . . . 17 4 application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 temperature measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 pressure measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3 wave recorder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.4 electrocardiogram (ecg) acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.5 power meter application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AN4207 list of tables doc id 023945 rev 1 3/28 list of tables table 1. applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. voltage step sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. typical sdadc input channel input impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4. sdadc vs. sar adc feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5. temperature sensor voltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 table 6. pressure sensor voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
list of figures AN4207 4/28 doc id 023945 rev 1 list of figures figure 1. block diagram of a sigma-delta analog to digital converter . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. input signal range in differential mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. typical connection of differential sensor to differential channels . . . . . . . . . . . . . . . . . . . . . 8 figure 4. input signal range in single ended offset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. input signal range in single ended zero reference mode . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. offset error in sdadc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7. gain error in sdadc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 8. gain calibration using the accurate reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 9. sdadc software calibration sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 10. equivalent input circuit for input channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 11. adc architecture vs. resolution and sampling rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 12. block diagram of voice recorder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 13. flowchart of wave recorder application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 14. block diagram of the electrocardiogram (ecg) acquisition application . . . . . . . . . . . . . . . 24 figure 15. flowchart of ecg acquisition application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 figure 16. three phase power meter application using stm32f37x/38x devices . . . . . . . . . . . . . . . 26
AN4207 basics of sigma-delta converters doc id 023945 rev 1 5/28 1 basics of sigma-delta converters sigma-delta converters, also known as oversampling converters, consist of two basic circuits: a modulator and a digital filter ( figure 1 ). in the modulator, the input signal is added to the negative feedback signal from the digital to analog converter (dac). the signal?s difference, after passing through the integrating circuit, reaches the input of the comparator (1-bit adc), where it is compared to the reference voltage (the comparator works as a 1-bit quantizer). the input signal from the comparator (1-bit adc) controls the 1-bit converter and reaches the input of the digital filter, which decreases flowability and transforms the 1-bit stream into 16-bit words. the used filter topology that ensures the low-pass stage is sinc3. figure 1. block diagram of a sigma- delta analog to digital converter 1-bit adc 1-bit dac digital filter & decimator vin 1-bit stream msv31135v1 16-bit data
overview of 16-bit sdadc AN4207 6/28 doc id 023945 rev 1 2 overview of 16-bit sdadc 2.1 main features stm32f37x/38x devices have three embedded sigma-delta analog to digital converters (sdadc). they can be synchronized together and each has the following main features: effective number of bits (enob) equal to 14 bits 5 differential input pairs, or 9 single-ended inputs, or a combination high-performance data throughput: ? 16.6 ksps input sampling rate when multiplexing between different channels ? 50 ksps input sampling rate for single-channel operation programmable gain: x0.5, x1, x2, x4, x8, x16 and x32 selectable reference voltage: v ddsd , 1.22 v, 1.8 v and v ref 2.1.1 clock selection the sdadc clock is supplied by sdadcclk which divides the system clock (sysclk) by a selectable prescaler: 2, 4, 6, 8, 10, 12, 14, 16, 20, 24, 28, 32, 36, 40, 44 and 48. the typical operating frequency of sdadc is 6 mhz in fast mode and 1.5 mhz in slow mode. example : if sysclk is set to 72 mhz, the sdadc di vider should be set to sysclk/typical frequency: fast speed mode: prescaler = 72 mhz / 6 mhz = 12 low speed mode: prescaler = 72 mhz / 1.5 mhz = 48 2.1.2 input modes the sdadc has three possible input modes, that can be combined. differential mode: single ended offset mode single ended zero reference mode differential mode it is recommended to use differential mode when the sensors being used produce very small signals that are very susceptible to nois e. this is especially the case when using thermocouple and bridge type sensors (pressure sensors). in differential mode, the sdadc converts the difference between sdadcx_ainyp and sdadcx_ainym. the result can be either positive or negative depending on which input is at higher voltage. note: the sdadc can not measure negative voltages and the input voltage on each channel must stay within the electrical limits of the device. the input range is [-vref/(2*gain), + vref/(2*gain)] and the conversion value is in the range [- 32767, +32767]
AN4207 overview of 16-bit sdadc doc id 023945 rev 1 7/28 example: for a 1.22v reference voltage and a gain set to 1, the input range is +/- 0.61v the formula is: vin = sdadcx_ainyp - sdadcx_ainym = readdata * vref/(2 x gain x 32767) with readdata is two?s complement read data from the sdadc data register (sdadcx_jdatar or sdadcx_rdatar) figure 2. input signal range in differential mode figure 3 shows how to connect a bridge type sensor to the 16-bit sdadc. as shown below both positive (sdadcx_ainyp ) and negative (sdadcx_ainym) inputs are connected to sensor outputs. sdadcx_ainyp - sdadcx_ainym + vref/(2xgain) - vref/(2xgain) msv31128v1
overview of 16-bit sdadc AN4207 8/28 doc id 023945 rev 1 figure 3. typical connection of differential sensor to differential channels single ended offset mode in single ended offset mode, conversions are performed by connecting the negative input to 0 v internally, leaving the corresponding pin for the negative input (sdadcx_ainym) free to be used for other purposes. the signal to be measured is applied to the positive input sdadcx_ainyp. this mode of operation is similar to differential mode, except that the output data is only from 0 to +32767, and not from ?32767 to +32767, therefore half the dynamic range is lost, consequently the snr is degraded. the formula is: vin = sdadcx_ainyp = readdata * vref/(2 x gain x 32767) with readdata is two?s complement read data from sdadc data register (sdadcx_jdatar or sdadcx_rdatar) vref sdadcx_inyp sdadcx_inym sdadc_vref+ sdadc_vref- vref stm32f37x msv31129v1
AN4207 overview of 16-bit sdadc doc id 023945 rev 1 9/28 figure 4. input signal range in single ended offset mode single ended zero reference mode the signal is applied to the positive input sdadcx_ainyp, and the negative input is set to the signal reference (normally 0 v). this mode injects an input common mode of half scale to the adc thus maintaining the dynamic range the same as in differential mode (-32767 to +32767). in this mode, the injected common mode is dependent on gain variations. the formula is: vin = sdadcx_ainyp = (readdata + 32767) * vref/(gain x 65535) with readdata is two?s complement read data from sdadc data register (sdadcx_jdatar or sdadcx_rdatar) sdadcx_ainyp vref/(2xgain) msv31130v1
overview of 16-bit sdadc AN4207 10/28 doc id 023945 rev 1 figure 5. input signal range in single ended zero reference mode note: when channel p (with p is even) is used in differential mode, the channel p+1 is automatically used as minus input (sdadcx_a inym) and therefore channel p+1 can not be used in single ended mode (zero reference mode or offset mode). when channel 4 is configured in differential mode channel 5 is automatically used as minus input and therefore channel 5 can not be used either in single ended offset mode or in single ended zero reference mode. 2.1.3 sdadc voltage references the sdadc reference voltage is selectable among four sources: 1. vrefint1: a 1.2v embedded reference voltage 2. vrefint2: a 1.8v embedded reference voltage 3. vddsd: the sdadc analog supply voltage. it ranges from 2.2 v to 3.6 v 4. vrefsd+: the external sdadc reference voltage. it ranges from 1.1 v to vddsd the table below shows the voltage weights per bit (step size) using three possible references. sdadcx_ainyp vref/gain msv31131v1 table 2. voltage step sizes vrefsd+ v/bit vreint1: 1.2 18.46 vreint2: 1.8 27.69 3.3v 50.35
AN4207 overview of 16-bit sdadc doc id 023945 rev 1 11/28 2.1.4 calibration in order to get the best performance from the sdadc two parameters should be calibrated. these parameters are offset and gain. offset calibration the offset error is a constant value that is added to the ideal conversion value. figure 6 illustrates the offset error. the sdadc embedded in stm32f37x/38x devices provides automatic offset calibration without adding external components. its principle can be summarized in the following steps: 1. short internally both channel inputs (positive and negative) 2. perform conversion and store result in internal register (configuration register) 3. subtract automatically the calibration value from conversion value during standard conversion. note: it is recommended to run calibration at least once after sdadc configuration figure 6. offset error in sdadc gain calibration another error source is the ga in error. as illustrated in figure 7 the gain error is the deviation of the sdadc?s transfer function from the ideal straight line. it is due to the built-in programmable amplifier. according to the device datasheet the typical analog gain error is -2.7% which means there can be 884 counts (at maximum voltage) due to gain error. so reducing the gain error is mandatory when performing accurate measurements. analog input negative offset 1 2 digital value positive offset null offset msv31132v1
overview of 16-bit sdadc AN4207 12/28 doc id 023945 rev 1 figure 7. gain error in sdadc two types of gain are implemented in the sdadc: analog gain: x1/2, x1, x2, x4, x8 digital gain: x16 and x32. only the analog gains are considered in gain calibration. gain calibration requires an external accurate reference and it is performed by applying the accurate reference voltage (accref) at the sdadc input and getting the sdadc output. the gain is computed as following: accref/(output x vref/65535) the computed gain can be stored in non-volatile memory (flash memory) and used during acquisition phase note: before running gain calibration it is mandatory to run offset calibration. analog input digital value 1 positive gain error 2 negative gain error 3 null gain error msv31133v1
AN4207 overview of 16-bit sdadc doc id 023945 rev 1 13/28 figure 8. gain calibration using the accurate reference voltage sdadcx_inyp sdadc_vref+ sdadc_vref- vref stm32f37x sensor accurate reference i/o control 1 2 1 2 acquisition phase gain calibration phase msv31134v1
overview of 16-bit sdadc AN4207 14/28 doc id 023945 rev 1 software procedure for offset and gain calibration the flowchart below shows a typical sdadc application using both offset and gain calibration. figure 9. sdadc software calibration sequence input voltage acquisition configure sdadc (gain, conversion mode, channel) run offset calibration convert the accurate reference calculate the exact gain value store the exact gain value in non-volatile memory or back- up registers acquire the sdadc input (sensor outpout) calculate the input voltage using the exact gain value end stop conversion? msv31136v1
AN4207 overview of 16-bit sdadc doc id 023945 rev 1 15/28 2.1.5 matching impedance the impedance of the analog signal source, or series resistance (r ain ), between the source and the mcu pin may lead to a voltage drop across it because of the current flowing into the pin. in sdadc, the channel input impedance depends on: 1. sdadc clock 2. analog gain (0.5 - 8) the figure below shows the equivalent input circuit for input channel where r in is the input impedance of sdadc analog input and can be calculated using the formula below. figure 10. equivalent input circuit for input channel table 3. typical sdadc input channel input impedance frequency gain r in 1.5 mhz 0.5 540 k ? 6 mhz 0.5 135 k ? 6 mhz 8 47 k ? r in 1 2f clk c ?? ------------ ------------ = sdadcx_ainxp chclk chclkz chclkz chclk c = 0.543 pf + 0.152 pf * gain c = 0.543 pf + 0.152 pf * gain sdadcx_ainxm r ain : the impedance of the analog signal source v ain : the signal source r ain v ain msv31137v1
overview of 16-bit sdadc AN4207 16/28 doc id 023945 rev 1 2.1.6 low power modes the 16-bit sdadc combines both high resolution and low power consumption making it suitable for battery-powered products. if the sdadc is left powered-up continuously, it consumes 1.2 ma maximum (typically 800 a). the sdadc has three main modes for reducing power consumption: 1. slow mode: in this mode, the sdadc consumes 600 a maximum but the sampling rate is limited to 12.5 ksps maximum 2. standby mode: in this mode, the sdadc consumes a maximum of about 200 a but a stabilization time of 300 sdadc clock cycles (50 s @ 6 mhz) is required each time it exits from standby mode. 3. power down mode: in this mode, the sdadc consumes a maximum of about 2.5 a but a stabilization time of 600 sdadc clock cycles (100 s @ 6 mhz) is required each time it exits from standby mode.
AN4207 sigma-delta (sd) vs. successive approximation register (sar) analog-to-digital convert- doc id 023945 rev 1 17/28 3 sigma-delta (sd) vs. successive approximation register (sar) analog-to-digital converters analog to digital converters come in different architectures to be able to address the needs of different applications. the main types available in the market are: successive approximat ion register (sar) adc: successive-approximation-register (sar) analog-to-digital converters (adcs) are frequently used in embedded systems, with sample rates of less than 5 megasamples per second (msps). their resolution ranges from 8 to 16 bits. this type of adc is used in industrial control applications. sigma-delta adc (sdadc): sigma-delta analog-to-digital converters (adcs) are used in lower speed applications requiring high resolution. the resolution may attain 24 bits by oversampling but the sampling rate is limited to only a few ksps. flash adc: flash analog-to-digital converters, are the fastest type of analog to a digital converter. they are suitable for applications requiring a very high sampling rate. however, flash converters have low resolution (12-bits ). this type of adc is used in oscilloscopes. the figure 11 gives an overview of the different adc architectures, comparing their resolution and sampling rate. figure 11. adc architecture vs . resolution and sampling rate the stm32f37x/38x devices have two types of embedded adcs: 12-bit sar adc and 16- bit sdadc. the ta bl e 4 summarizes the differences between the two types of adc. 24 16 8 12 resolution (bits) sample rate (sample/s) 100 k 5 m 5 g sigma delta sar flash msv31138v1
sigma-delta (sd) vs. successive approximation register (sar) analog-to-digital converters 18/28 doc id 023945 rev 1 table 4. sdadc vs. sar adc feature comparison feature sdadc sar adc max sampling rate 50 ksps (1) 1. the sampling rate is 50 ksps when selecting a single channel and 16.6 ksps when multiplexing between different channels. 1 msps resolution 16 bits 12 bits input mode single-ended differential single-ended embedded gains 0.5x to 32x no number of channels 5 differential input pairs or 9 single-ended inputs 16 single-ended inputs number of instances 3 with synchro capability 1 automatic offset calibration yes yes analog watchdog no yes trigger sources for regular conversion ?software ? start of conversion of another sdadc ? software ? embedded timers ? external events trigger sources for injected conversion ?software ? embedded timers ? external events ? start of conversion of another sdadc ? software ? embedded timers ? external events input range [v ref- , v ref+ ] reference voltage 1.22 v 1.8 v vddsd vrefsd+ v ref+ input impedance (2) 2. for sdadc, the input impedance depends on the selected gain and the selected operating frequency (1.5 mhz or 6 mhz). for sar adc, the input impedance depends on used sampling frequency (0.05 - 1 mhz) and sampling capacitor (8pf). 47 k ? to 540 k ? 125 k ? to 2500 k ?
AN4207 application examples doc id 023945 rev 1 19/28 4 application examples this section presents how the 16-bit sdadc embedded in stm32f37x/38x devices can be used in application examples such as temperature measurement, pressure measurement, three-phase power meter, voice recorder... 4.1 temperature measurement this purpose of this application is to show how to use the 16-bit resolution sigma-delta analog-to-digital converter to perform accurate temperature measurement using the pt100 sensor connected to pe7 in the stm32373c-eval evaluation board. the application source code is av ailable in are available in the project\stm32f37x_stdperiph_examples\sdadc folder in the stm32f37x dsp and standard peripherals library package stm32f37x_dsp_stdperiph_lib . a current source circuit available on the stm32373c-eval board is used to provide a fixed 1 ma current (when v dd = 3.3 v) to the temperature sensor pt100 which is connected to sdadc1 channel 3p (pe7) through a reference resistor 1k8 labeled r33. the sdadc is configured in single-ended offset mode. the input range is from 0 v to v ref /(2*gain). in this application, the sdadc internal gain is set to 8 so the range is from 0 v to v ref /16. the external reference v ref (set to 3.3v on stm32373c-eval) is used as reference for sdadc using jp17 so the measurement ranges between 0 v and v ref /16 = 0.20625v. the conversion is performed in continuous mode with interrupts enabled on end of regular conversion. the temperature is computed using the formula below: rpt100 = 100 + 0.385 * t ? t = (rpt100 - 100) / 0.385 vpt100 = rpt100 * ipt100 = rpt100 * vdd_ana / 2 * rref ? rpt100 = vpt100 * 1800 * 2 / vdd_ana ? t = ((vpt100 * 1800 * 2 / vdd_ana) - 100) / 0.385 where: rpt100 is the resistance of the pt100 sensor vpt100 is the voltage measured on pt100 sensor ipt100 is ~ 1ma current crossing the pt100 sensor vdd_ana is the analog voltage rref is the reference resistor 1k8 labeled r33 on stm32373c-eval
application examples AN4207 20/28 doc id 023945 rev 1 the temperature measurement is performed in two steps: 1. temperature sensor calibration: this phase is performed with jp18 fitted in 2-3(ref) position. a 100 ohm resistor is connected to pe7 which is connected to vref through the reference resistor. the sdadc converter measures the analog voltage applied on pe7 and then computes the correction coefficient. this calibrates the gain. the pt100 is not connected in this phase. 2. temperature measurement: this phase is performed with jp18 fitted in 1-2 (pt100) position. the pt100 sensor is connected to pe7 which is connected to vref through the reference resistor. the sdadc converter measures the analog voltage applied on pe7 and then computes the temperature which is given by the following formula: temperaturept100 = (((((coeffcorrection * (avrgregularconvdata/sdadc_gain) * reference_resistor * 2) / sdadcresol) - resistance_zerodegre) / resistance_coefficient); where: avrgregularconvdata is the average value of 256 samples sdadc_gain is the internal sdadc gain . in this example it is set to 8 coeffcorrection is the correction coefficient computed in phase 1. reference_resistor is the reference resistor 1k8 labeled r33 on stm32373c- eval sdadcresol is the sigma delta converter: 2e16-1 resistance_zerodegre is the resistance of pt100 at 0 c resistance_coefficient is the coefficient of pt100 sensor table 5. temperature sensor voltage range v dd = 3.3v temperature resistance ( ? ) voltage (mv) rref = 1.8 k 0 100 91.667 20 107.7 98.725 50 119.2 109.2667
AN4207 application examples doc id 023945 rev 1 21/28 4.2 pressure measurement this application is intended to show how to use the 16-bit sigma-delta analog-to-digital converter to perform pressure measurement using the absolute pressure sensor mpx2102a mounted on the stm32373c-eval evaluation board. the application source co de is available in the project\stm32f37x_stdperiph_examples\sdadc folder in the stm32f37x dsp and standard peripherals library package stm32f37x_dsp_stdperiph_lib . on the stm32373c-eval board, the mpx2102a sensor is connected to sdadc1 channel 8p (pe8) and channel 8n (pe9). the mpx2102a sensitivity when powered by 3.3 v is 3.3 v * 40 mv / 10 v = 13.2 mv/1000 mb = 13.2 microv/mb. to increase the sensitivity an external 45.1 gain is applied, using the tvs632 operational amplifier installed on the stm32373c-eval. the same operational amplifier is used to shift-down the input voltage by 3.3 v/10 = 0.33 v note: refer to stm32373c-eval user manual for more details about how the mpx2102a is connected to pe8 and pe9 the sdadc channel 8 is configured in differential mode. the external reference vref (set to 3.3 v on stm32373c-eval) is used as reference for sdadc. the conversion is triggered by the tim19 timer with interrupt enabled on end of injected conversion. the input voltage is calculated using the formula below: inputvoltage = (injectedconvdata * (sdadc_vref / (sdadc_resol * sdadc_gain))) + offset_voltage; where: injectedconvdata: the digital value read from sdadc data register sdadc_vref: is the sigma delta converter voltage reference: set externally to 3.3v sdadc_resol: is the sigma delta converter resolution: 2e16-1 sdadc_gain: is the internal sdadc gain. in this example it is set to 4 offset_voltage: the offset voltage added by the operational amplifier tvs632 (approximately 3.3 v/10 = 0.33 v) and the pressure is calculat ed using the formula below: pressuremb = ((1000000 * inputvoltage) / (mpx2102_sensitivity * externgain)); table 6. pressure sensor voltage range pressure (hpa) differential voltage on sensor outputs differential voltage on sdadc inputs v dd = 3.3v 800 10.56 mv 146.256 mv 1000 13.2 mv 265.32 mv 1200 15.84 mv 384.384 mv
application examples AN4207 22/28 doc id 023945 rev 1 4.3 wave recorder this application shows how to use the 16-bit sigma-delta analog-to-digital converter to record the human voice using the electric condenser microphone installed on the stm32373c-eval evaluation board. the application source co de is available in the project\stm32373c-eval\src\waverecorder.c file in the stm32373c-eval demonstration firmware package stm32373c-eval_fw a microphone is connected to sdadc1 channel 6 (pb0) through an audio amplifier/filter. the sdadc is configured in single-ended ze ro reference mode and voice recording is triggered by tim13 at a sampling rate of 8 khz. the wave recorder application uses a ping-pong buffer: one buffer is actively being written in the microsd memory card while the second buffer is filled with the new samples. writing access to the microsd memeory card uses the open source file system fatfs. figure 12 shows the block diagram of the voice recorder application. figure 12. block diagram of voice recorder the flowchart of this application is given in figure 13 . msv31139v1 1st buffer 2nd buffer 16-bit ? sdadc tim13 audio aop sram spi cortex m4 cpu wth fpu/ mpu 72 mhz stm32f37x
AN4207 application examples doc id 023945 rev 1 23/28 figure 13. flowchart of wave recorder application tim4 irq write selected buffer in microsd clear tim4 interrupt tim13 irq switch selected buffer generate tim4 interrupt clear tim13 interrupt write sdadc sample in selected buffer is selected buffer full? wave recorder create a wave file on microsd init sdadc init tim13 used as trigger stop recording: disable sdadc, disable tim13 close the wave file exit application stop recording ? msv31140v1
application examples AN4207 24/28 doc id 023945 rev 1 4.4 electrocardiogram (ecg) acquisition this application shows how to use the 16-bit sigma-delta analog-to-digital converter to acquire a human ecg using two ecg electrodes ts1 and ts2 installed on the stm32373c-eval evaluation board. the application source co de is available in the project\stm32373c-eval\src\applications.c file in the stm32373c-eval demonstration firmware package stm32373c-eval_fw two ecg electrodes ts1 and ts2 are connected to sdadc1 channel 0 (pe12) through an ecg amplifier/filter. the sdadc is configured in single-ended zero reference mode and conversion is triggered by the tim3 timer at a sampling rate of 480 hz. the ecg acquisition application uses a ping-pong bu ffer: one buffer is actively being filtered (using a bandpass filter) and then displayed on the lcd while the second buffer is filled with the new ecg samples. note: ecg samples are filter ed using the arm dsp library figure 14 below shows the block diagram of the electrocardiogram acquisition application. figure 14. block diagram of the electroc ardiogram (ecg) acquisition application msv31141v1 1st buffer 2nd buffer 16-bit ? sdadc tim13 480/sec ecg aop sram spi cortex m4 cpu wth fpu/ mpu 72 mhz stm32f37x dma
AN4207 application examples doc id 023945 rev 1 25/28 the flowchart of this application is given in the figure below. figure 15. flowchart of ecg acquisition application dma half/ complete transfer irq set buffer pointer at 2nd half set buffer pointer at 1st half clear dma half/ complete transfer interrupt write sdadc sample in selected buffer ecg acquisition init sdadc, tim3 used as trigger, dma init sdadc init tim13 used as trigger filter the sdadc samples using a bandpass fir filter display filtered samples on lcd reset buffer pointer exit application disable acquisition: disable sdadc, disable tim3 stop acquisition? is half transfer flag set ? buffer pointer reset? msv31142v1
application examples AN4207 26/28 doc id 023945 rev 1 4.5 power meter application the analog to digital converter is the most important part of a power meter application and the sdadc embedded in stm32f37x/38x devices meets the requirements of this type of application. typically a class b power meter requires 1.5% current measurement accuracy which means a 14-bit effective number of bits (enob) adc. for the voltage measurement there are no strict requirements and therefore the sar adc can be used for voltage measurement synchronized with the sdadc that is used for measuring the current. another constraining parameter of the analog to digital converter is the sampling rate. for power meter applications, a sampling rate of up to 12.8 ksps is sufficient for harmonic spectrum analysis. as shown in figure 16 , in the power meter application the phase measurement consists of measuring voltages: va, vb and vc in single-ended mode using the sar adc while currents (ia, ib and ic) are converted in differential mode using the sdadc. all are triggered by the same timer (for example tim19). figure 16. three phase power meter application using stm32f37x/38x devices msv31143v1 phase a phase b phase c neutral current sensor 1 current sensor 2 current sensor 3 ic ib ia resistor divider resistor divider resistor divider va vb vc sdadc3_ain0p sdadc3_ain0m sdadc2_ain0p sdadc2_ain0m sdadc1_ain0p sdadc1_ain0m adc_in0 adc_in1 adc_in2 stm32f37x
AN4207 revision history doc id 023945 rev 1 27/28 5 revision history table 7. document revision history date revision changes 13-dec-2012 1 initial release.
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