? semiconductor components industries, llc, 2015 may, 2015 ? rev. 0 1 publication order number: ntmfs5c404nlt/d ntmfs5c404nlt power mosfet 40 v, 0.75 m , 352 a, single n ? channel features ? small footprint (5x6 mm) for compact design ? low r ds(on) to minimize conduction losses ? low q g and capacitance to minimize driver losses ? ntmfs5c404nl twf ? wettable flank option for enhanced optical inspection ? these devices are pb ? free and are rohs compliant maximum ratings (t j = 25 c unless otherwise noted) parameter symbol value unit drain ? to ? source voltage v dss 40 v gate ? to ? source voltage v gs 20 v continuous drain current r jc (notes 1, 3) steady state t c = 25 c i d 352 a t c = 100 c 249 power dissipation r jc (note 1) t c = 25 c p d 200 w t c = 100 c 100 continuous drain current r ja (notes 1, 2, 3) steady state t a = 25 c i d 49 a t a = 100 c 35 power dissipation r ja (notes 1 & 2) t a = 25 c p d 3.9 w t a = 100 c 1.9 pulsed drain current t a = 25 c, t p = 10 s i dm 900 a operating junction and storage temperature t j , t stg ? 55 to + 175 c source current (body diode) i s 191 a single pulse drain ? to ? source avalanche energy (i l(pk) = 38 a) e as 907 mj lead temperature for soldering purposes (1/8 from case for 10 s) t l 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. thermal resistance maximum ratings parameter symbol value unit junction ? to ? case ? steady state r jc 0.75 c/w junction ? to ? ambient ? steady state (note 2) r ja 39 1. the entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. surface ? mounted on fr4 board using a 650 mm 2 , 2 oz. cu pad. 3. maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. marking diagram www. onsemi.com xxxxxx aywzz v (br)dss r ds(on) max i d max 40 v 0.75 m @ 10 v 352 a 1.0 m @ 4.5 v g (4) s (1,2,3) n ? channel mosfet d (5,6) s s s g d d d d dfn5 (so ? 8fl) case 488aa style 1 1 see detailed ordering, marking and shipping information on page 5 of this data sheet. ordering information xxxxxx = 5c404l xxxxxx = (ntmfs5c404nlt) or xxxxxx = 404lwf xxxxxx = (ntmfs5c404nltwf) a = assembly location y = year w = work week zz = lot traceability
ntmfs5c404nlt www. onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise specified) parameter symbol test condition min typ max unit off characteristics drain ? to ? source breakdown voltage v (br)dss v gs = 0 v, i d = 250 a 40 v drain ? to ? source breakdown voltage temperature coefficient v (br)dss / t j 21.6 mv/ c zero gate voltage drain current i dss v gs = 0 v, v ds = 40 v t j = 25 c 10 a t j = 125 c 250 gate ? to ? source leakage current i gss v ds = 0 v, v gs = 20 v 100 na on characteristics (note 4) gate threshold voltage v gs(th) v gs = v ds , i d = 250 a 1.2 2.0 v threshold temperature coefficient v gs(th) /t j ? 6.2 mv/ c drain ? to ? source on resistance r ds(on) v gs = 10 v i d = 50 a 0.56 0.75 m v gs = 4.5 v i d = 50 a 0.85 1.0 forward transconductance g fs v ds =15 v, i d = 50 a 270 s charges, capacitances & gate resistance input capacitance c iss v gs = 0 v, f = 1 mhz, v ds = 25 v 12168 pf output capacitance c oss 4538 reverse transfer capacitance c rss 79.8 total gate charge q g(tot) v gs = 4.5 v, v ds = 20 v; i d = 50 a 81 nc total gate charge q g(tot) v gs = 10 v, v ds = 20 v; i d = 50 a 181 threshold gate charge q g(th) v gs = 4.5 v, v ds = 20 v; i d = 50 a 8.5 gate ? to ? source charge q gs 27.8 gate ? to ? drain charge q gd 23.8 plateau voltage v gp 2.7 v switching characteristics (note 5) turn ? on delay time t d(on) v gs = 4.5 v, v ds = 20 v, i d = 50 a, r g = 1.0 24 ns rise time t r 135 turn ? off delay time t d(off) 87 fall time t f 157 drain ? source diode characteristics forward diode voltage v sd v gs = 0 v, i s = 50 a t j = 25 c 0.7 1.2 v t j = 125 c 0.61 reverse recovery time t rr v gs = 0 v, dis/dt = 100 a/ s, i s = 50 a 97.4 ns charge time t a 46.5 discharge time t b 50.9 reverse recovery charge q rr 190 nc product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 4. pulse test: pulse width 300 s, duty cycle 2%. 5. switching characteristics are independent of operating junction temperatures.
ntmfs5c404nlt www. onsemi.com 3 typical characteristics figure 1. on ? region characteristics figure 2. transfer characteristics v ds , drain ? to ? source voltage (v) v gs , gate ? to ? source voltage (v) 3.0 1.5 1.0 0.5 0 0 40 80 120 160 200 3.0 2.5 2.0 1.5 1.0 0.5 0 0 100 200 300 400 700 figure 3. on ? resistance vs. gate ? to ? source voltage figure 4. on ? resistance vs. drain current and gate voltage v gs , gate voltage (v) i d , drain current (a) 10 9 8 7 6 5 4 3 0.0004 0.0006 0.0008 0.0012 0.0014 210 290 170 90 50 10 0.0002 0.0004 0.0008 0.0010 figure 5. on ? resistance variation with temperature figure 6. drain ? to ? source leakage current vs. voltage t j , junction temperature ( c) v ds , drain ? to ? source voltage (v) 150 125 100 75 25 0 ? 25 ? 50 0.7 0.9 1.1 1.3 1.5 1.7 1.9 40 35 30 25 15 5 10 10k i d , drain current (a) i d , drain current (a) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , normalized drain ? to ? source resistance ( ) i dss , leakage (na) 2.8 v 3.0 v 10 v to 3.2 v 3.5 t j = 125 c t j = 25 c t j = ? 55 c t j = 25 c i d = 50 a t j = 25 c v gs = 4.5 v v gs = 10 v v gs = 10 v i d = 50 a 50 175 t j = 125 c t j = 85 c 240 280 500 600 800 2.1 2.0 2.5 0.0010 0.0005 0.0007 0.0009 0.0013 0.0015 0.0011 0.0006 0.5 100 1k 100k 1m 10 20 t j = 150 c 4.0 130 250
ntmfs5c404nlt www. onsemi.com 4 typical characteristics figure 7. capacitance variation figure 8. gate ? to ? source and drain ? to ? source voltage vs. total charge v ds , drain ? to ? source voltage (v) q g , total gate charge (nc) 40 30 20 10 0 0 1k 3k 4k 2k 10k 12k 180 140 100 80 40 20 0 0 2 4 6 8 10 figure 9. resistive switching time variation vs. gate resistance figure 10. diode forward voltage vs. current r g , gate resistance ( ) v sd , source ? to ? drain voltage (v) 100 10 1 10 100 1000 10,000 0.9 0.8 1.0 0.7 0.6 0.5 0.4 0.3 1 21 41 figure 11. safe operating area figure 12. i peak vs. time in avalanche v ds (v) time in avalanche (s) 100 10 1 0.1 1 10 100 1000 1 10 c, capacitance (pf) v gs , gate ? to ? source voltage (v) t, time (ns) i s , source current (a) i ds (a) i peak (a) v gs = 0 v t j = 25 c f = 1 mhz c iss c oss c rss v ds , drain ? to ? source voltage (v) 0 10 15 20 25 30 5 v ds = 20 v t j = 25 c i d = 50 a q t q gs q gd v gs = 4.5 v v dd = 20 v i d = 50 a t d(off) t d(on) t f t r t j = 150 c t j = 25 c t j = ? 55 c 11 31 t j(initial) = 100 c t j(initial) = 25 c 1e ? 04 1e ? 02 r ds(on) limit thermal limit package limit dc 0.01 ms 0.1 ms 1 ms 10 ms t c = 25 c v gs 10 v 5k 6k 7k 8k 11k 13k 1e ? 03 1000 35 25 15 5 9k 14k 60 120 t j = 125 c 6 16 26 36 46 100 160
ntmfs5c404nlt www. onsemi.com 5 figure 13. thermal characteristics pulse time (sec) 0.01 0.001 1 0.0001 0.1 0.00001 10 0.000001 0.01 0.1 1 10 100 r ja (t) ( c/w) 100 1000 single pulse 50% duty cycle 20% 10% 5% 2% 1% ntmfs5c404nlt 650 mm 2 , 2 oz., cu single layer pad device ordering information device marking package shipping ? ntmfs5c404nltt1g 5c404l dfn5 (pb ? free) 1500 / tape & reel NTMFS5C404NLTWFT1G 404lwf dfn5 (pb ? free, wettable flanks) 1500 / tape & reel ntmfs5c404nltt3g 5c404l dfn5 (pb ? free) 5000 / tape & reel ntmfs5c404nltwft3g 404lwf dfn5 (pb ? free, wettable flanks) 5000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ntmfs5c404nlt www. onsemi.com 6 package dimensions m 3.00 3.40 0 ??? 3.80 12 dfn5 5x6, 1.27p (so ? 8fl) case 488aa issue k notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeter. 3. dimension d1 and e1 do not include mold flash protrusions or gate burrs. 1234 top view side view bottom view d1 e1 d e 2 2 b a 0.20 c 0.20 c 2 x 2 x dim min nom millimeters a 0.90 1.00 a1 0.00 ??? b 0.33 0.41 c 0.23 0.28 d 5.15 d1 4.70 4.90 d2 3.80 4.00 e 6.15 e1 5.70 5.90 e2 3.45 3.65 e 1.27 bsc g 0.51 0.61 k 1.20 1.35 l 0.51 0.61 l1 0.125 ref a 0.10 c 0.10 c detail a 14 l1 e/2 8x d2 g e2 k b a 0.10 b c 0.05 c l detail a a1 e 3 x c 4 x c seating plane max 1.10 0.05 0.51 0.33 5.10 4.20 6.10 3.85 0.71 1.50 0.71 style 1: pin 1. source 2. source 3. source 4. gate 5. drain m *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 1.270 2x 0.750 1.000 0.905 0.475 4.530 1.530 4.560 0.495 3.200 1.330 0.965 2x 2x 3x 4x 4x pin 5 (exposed pad) 5.00 5.30 6.00 6.30 on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warrant y, representation or guarantee regarding the suitability of it s products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ntmfs5c404nlt/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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