? semiconductor components industries, llc, 2009 july, 2009 ? rev. 5 1 publication order number: NTLJD3115P/d NTLJD3115P power mosfet ? 20 v, ? 4.1 a, cool dual p ? channel, 2x2 mm wdfn package features ? wdfn package provides exposed drain pad for excellent thermal conduction ? 2x2 mm footprint same as sc ? 88 ? lowest r ds(on) solution in 2x2 mm package ? 1.8 v r ds(on) rating for operation at low voltage gate drive logic level ? low profile (< 0.8 mm) for easy fit in thin environments ? bidirectional current flow with common source configuration ? this is a pb ? free device applications ? optimized for battery and load management applications in portable equipment ? li ? ion battery charging and protection circuits ? high side load switch maximum ratings (t j = 25 c unless otherwise noted) parameter symbol value unit drain ? to ? source voltage v dss ? 20 v gate ? to ? source voltage v gs 8.0 v continuous drain current (note 1) steady state t a = 25 c i d ? 3.3 a t a = 85 c ? 2.4 t 5 s t a = 25 c ? 4.1 power dissipation (note 1) steady state t a = 25 c p d 1.5 w t 5 s 2.3 continuous drain current (note 2) steady state t a = 25 c i d ? 2.3 a t a = 85 c ? 1.6 power dissipation (note 2) t a = 25 c p d 0.71 w pulsed drain current t p = 10 s i dm ? 20 a operating junction and storage temperature t j , t stg ? 55 to 150 c source current (body diode) (note 2) i s ? 1.9 a lead temperature for soldering purposes (1/8 from case for 10 s) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. surface mounted on fr4 board using 1 in sq pad size (cu area = 1.127 in sq [2 oz] including traces). 2. surface mounted on fr4 board using the minimum recommended pad size of 30 mm 2 , 2 oz cu. http://onsemi.com ? 20 v 135 m @ ? 2.5 v 100 m @ ? 4.5 v r ds(on) max ? 4.1 a i d max (note 1) v (br)dss 200 m @ ? 1.8 v g1 s1 p ? channel mosfet d1 jd = specific device code m = date code = pb ? free package (note: microdot may be in either location) jdm 1 2 3 6 5 4 wdfn6 case 506an marking diagram device package shipping ? ordering information NTLJD3115Pt1g wdfn6 (pb ? free) 3000/tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. d2 d1 pin 1 g2 s2 p ? channel mosfet d2 1 2 3 6 5 4 s1 g1 d2 d1 g2 s2 (top view) pin connections d1 d2 NTLJD3115Ptag wdfn6 (pb ? free) 3000/tape & reel
NTLJD3115P http://onsemi.com 2 thermal resistance ratings parameter symbol max unit single operation (self ? heated) junction ? to ? ambient ? steady state (note 3) r ja 83 c/w junction ? to ? ambient ? steady state min pad (note 4) r ja 177 junction ? to ? ambient ? t 5 s (note 3) r ja 54 dual operation (equally heated) junction ? to ? ambient ? steady state (note 3) r ja 58 c/w junction ? to ? ambient ? steady state min pad (note 4) r ja 133 junction ? to ? ambient ? t 5 s (note 3) r ja 40 3. surface mounted on fr4 board using 1 in sq pad size (cu area = 1.127 in sq [2 oz] including traces). 4. surface mounted on fr4 board using the minimum recommended pad size (30 mm 2 , 2 oz cu).
NTLJD3115P http://onsemi.com 3 mosfet electrical characteristics (t j = 25 c unless otherwise noted) parameter symbol test conditions min typ max unit off characteristics drain ? to ? source breakdown voltage v (br)dss v gs = 0 v, i d = ? 250 a ? 20 v drain ? to ? source breakdown voltage temperature coefficient v (br)dss /t j i d = ? 250 a, ref to 25 c 9.95 mv/ c zero gate voltage drain current i dss v ds = ? 16 v, v gs = 0 v t j = 25 c ? 1.0 a t j = 85 c ? 10 gate ? to ? source leakage current i gss v ds = 0 v, v gs = 8.0 v 100 na on characteristics (note 5) gate threshold voltage v gs(th) v gs = v ds , i d = ? 250 a ? 0.4 ? 0.7 ? 1.0 v negative gate threshold temperature coefficient v gs(th) /t j 2.44 mv/ c drain ? to ? source on ? resistance r ds(on) v gs = ? 4.5, i d = ? 2.0 a 75 100 m v gs = ? 2.5, i d = ? 2.0 a 101 135 v gs = ? 1.8, i d = ? 1.6 a 150 200 forward transconductance g fs v ds = ? 5.0 v, i d = ? 2.0 a 6.0 s charges, capacitances and gate resistance input capacitance c iss v gs = 0 v, f = 1.0 mhz, v ds = ? 10 v 531 pf output capacitance c oss 91 reverse transfer capacitance c rss 56 total gate charge q g(tot) v gs = ? 4.5 v, v ds = ? 10 v, i d = ? 2.0 a 5.5 6.2 nc threshold gate charge q g(th) 0.7 gate ? to ? source charge q gs 1.0 gate ? to ? drain charge q gd 1.4 gate resistance r g 8.8 switching characteristics (note 6) turn ? on delay time t d(on) v gs = ? 4.5 v, v dd = ? 5.0 v, i d = ? 1.0 a, r g = 6.0 6.0 ns rise time t r 11 turn ? off delay time t d(off) 21 fall time t f 8.0 turn ? on delay time t d(on) v gs = ? 4.5 v, v dd = ? 10 v, i d = ? 2.0 a, r g = 2.0 6.0 ns rise time t r 12 turn ? off delay time t d(off) 19 fall time t f 6.0 drain ? source diode characteristics forward recovery voltage v sd v gs = 0 v, is = ? 1.0 a t j = 25 c ? 0.75 ? 1.0 v t j = 125 c ? 0.64 reverse recovery time t rr v gs = 0 v, d isd /d t = 100 a/ s, i s = ? 1.0 a 12.6 ns charge time t a 7.0 discharge time t b 5.6 reverse recovery time q rr 5.0 nc 5. pulse test: pulse width 300 s, duty cycle 2%. 6. switching characteristics are independent of operating junction temperatures.
NTLJD3115P http://onsemi.com 4 typical performance curves (t j = 25 c unless otherwise noted) 12 0.15 5 1.4 1.6 1.2 0.8 0.6 10000 0 4.5 2 1 ? v ds , drain ? to ? source voltage (volts) ? i d , drain current (amps) 0 ? v gs , gate ? to ? source voltage (volts) figure 1. on ? region characteristics figure 2. transfer characteristics ? i d , drain current (amps) 1.0 2.0 1.5 figure 3. on ? resistance versus drain current ? i d , drain current (amps) figure 4. on ? resistance versus drain current and gate voltage ? i d , drain current (amps) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , drain ? to ? source resistance ( ) figure 5. on ? resistance variation with temperature t j , junction temperature ( c) figure 6. drain ? to ? source leakage current versus voltage ? v ds , drain ? to ? source voltage (volts) r ds(on) , drain ? to ? source resistance (normalized) ? i dss , leakage (na) ? 50 50 25 0 ? 25 75 125 100 1 212 10 4 3 1 2 v ds 10 v t j = 25 c t j = ? 55 c t j = 125 c v gs = 0 v i d = ? 2.2 a v gs = ? 4.5 v 3 t j = 100 c t j = 150 c 2 0 1.5 t j = 25 c 20 v gs = ? 1.9 v to ? 6 v ? 1.5 v 3 1000 4 4 0 4 t j = 25 c 150 10 2.5 ? 1.4 v ? 1.3 v ? 1.2 v t j = 25 c v gs = ? 4.5 v t j = ? 55 c t j = 100 c 0 v gs = ? 4.5 v v gs = ? 2.5 v 6 8 14 16 18 2 0.5 2.5 3 5 3.5 ? 1.6 v ? 1.7 v 1 3 5 0.05 100 2.5 1.5 0.5 0.5 1.5 2.5 3.5 4.5 ? 1.8 v 0.1 0.05 0.1 0.04 0.07 0.06 0.08 0.09 4 1.0
NTLJD3115P http://onsemi.com 5 typical performance curves (t j = 25 c unless otherwise noted) 5 5 15 20 gate ? to ? source or drain ? to ? source voltage (volts) c, capacitance (pf) figure 7. capacitance variation 800 0 v gs v ds 1000 400 010 v ds = 0 v t j = 25 c c oss c rss 1200 c iss figure 8. gate ? to ? source and drain ? to ? source voltage versus total charge figure 9. resistive switching time variation versus gate resistance r g , gate resistance (ohms) 1 10 100 1000 1 t, time (ns) 100 t r t d(off) t d(on) t f 10 v dd = ? 15 v i d = ? 2.2 a v gs = ? 4.5 v 2.5 0 0 ? v sd , source ? to ? drain voltage (volts) v gs = 0 v figure 10. diode forward voltage versus current 1.0 1 0.6 2 figure 11. maximum rated forward biased safe operating area t j = 25 c -v gs , gate-to-source voltage (volts) 0 3 0 q g , total gate charge (nc) 5 4 4 3 i d = ? 2.2 a t j = 25 c v gs q gs q gd qt 2 1 5 8 0 20 12 4 -v ds , drain-to-source voltage (volts) v ds 16 3 0.8 0.4 0.2 ? i s , source current (amps) 600 200 1.5 0.5 t j = 150 c 6 2 1 0.1 0.7 0.9 0.5 0.3 0.1 1 100 ? v ds , drain ? to ? source voltage (volts) 1 100 r ds(on) limit thermal limit package limit 10 10 t c = 25 c t j = 150 c single pulse 1 ms 100 s 10 ms dc 10 s 0.1 0.01 ? i d , drain current (amps) *see note 2 on page 1 v gs = 0 v
NTLJD3115P http://onsemi.com 6 typical performance curves (t j = 25 c unless otherwise noted) figure 12. thermal response t, time (s) 1 1000 0.1 0.2 0.02 d = 0.5 0.05 0.01 single pulse d curves apply for power pulse train shown read time at t 1 t j(pk) ? t a = p (pk) r ja (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 100 1000 10 0.1 0.001 0.0001 0.000001 0.1 100 10 1 0.01 0.00001 *see note 2 on page 1 effective transient thermal resistance
NTLJD3115P http://onsemi.com 7 package dimensions wdfn6, 2x2 case 506an ? 01 issue d notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. seating plane d e 0.10 c a3 a a1 0.10 c dim a min max millimeters 0.70 0.80 a1 0.00 0.05 a3 0.20 ref b 0.25 0.35 d 2.00 bsc d2 0.57 0.67 0.90 1.10 e 2.00 bsc 0.25 ref e2 e 0.65 bsc k 0.20 0.30 l 0.15 bsc f pin one reference 0.08 c 0.10 c note 4 a 0.10 c note 3 l e d2 e2 b b 3 6 6x 1 k 4 0.05 c d2 f mounting footprint bottom view soldermask defined dimensions: millimeters l1 detail a l optional constructions ?? ??? ??? --- 0.10 l1 a 0.10 cb a 0.10 cb 6x 0.47 2.30 1.10 0.77 2x 1.74 0.65 pitch 6x 0.35 1 package outline on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. NTLJD3115P/d cool is a trademark of semiconductor components industries, llc (scillc). publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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