p p j d14 p 10a jul y 21 ,201 5 - rev.00 page 1 10 0 v p - c hannel enhancement mode mosfet v oltage - 10 0 v c urrent - 14 a to - 252 f eatures ? r ds(on) , v gs @ - 10v,i d @ - 7 a < 14 0 m ? r ds(on) , v gs @ - 4.5 v,i d @ - 3 a< 17 0 m ? high switching speed ? impro ved dv/dt capability ? low gate charge ? low reverse transfer capacitance ? lead free in compliance with eu rohs 2011/65/eu directive . ? green molding compound as p er iec61249 std. (halogen free) m echanical data ? case: to - 252 package ? terminals: solderable per mil - std - 750, method 2026 ? approx. weight: 0.0104 ounces, 0.297 grams m aximum r atings and t hermal c haracteristics (t a =25 o c unless otherwise noted) parameter symbol limit units drain - source voltage v ds - 10 0 v gate - source voltage v gs + 2 0 v continuou s drain current t c =25 o c i d - 14 a t c = 100 o c - 9 pulsed drain current (note 1 ) t c =25 o c i dm - 4 0 power dissipation t c =25 o c p d 6 0 w t c = 100 o c 24 continuous drain current t a =25 o c i d - 2.5 a t a = 70 o c - 2.0 a power dissipation t a =25 o c p d 2.0 w power dissipation t a = 70 o c 1.3 single pulse avalanche energy (note 6 ) e as 20 mj operating junction and storage temperature range t j ,t stg - 55~1 50 o c typical thermal resistance (note 4,5 ) junction to case r jc o c /w j unction to ambient r ja 62.5 ? limited only by maximum junction temperature
p p j d14 p 10a jul y 21 ,201 5 - rev.00 page 2 e lectrical c haracteristics (t a =25 o c unless otherwise noted) parameter symbol test condition min. typ. max. units static drain - source breakdown voltage bv dss v gs =0v,i d = - 250ua - 10 0 - - v gate threshold voltage v gs(th) v ds =v gs ,i d = - 250ua - 1.0 - 2.0 - 3.0 v drain - source on - state resistance r ds(on) v gs = - 10v,i d = - 7 a - 1 15 140 m gs = - 4.5 v,i d = - 3 a - 1 3 0 17 0 zero gate voltage drain current i dss v ds = - 10 0 v,v gs =0v - - - 1 .0 ua gate - source leakage current i gss v gs = + 2 0 v,v ds =0v - - + 100 na dynamic (note 5 ) total gate charge q g v ds = - 5 0 v, i d = - 7 a, v gs = - 10 v (note 1,2 ) - 40.7 - nc gate - source charge q gs - 7.8 - gate - drain charge q gd - 6.4 - input capacitance ciss v ds = - 30 v, v gs =0v, f=1.0mhz - 2298 - pf output capacitance coss - 136 - reverse transfer capacitance crss - 92 - turn - on delay time td (on) v d s = - 3 0 v, id= - 1a , v gs = - 10v , r g = 6.2 (note 1,2 ) - 28 - ns turn - on rise time t r - 12 - turn - off delay time td (off) - 151 - turn - off fall time t f - 46 - drain - source diode maximum continuous drain - source diode forward current i s --- - - - 14 a reverse recovery time v sd i s = - 1 a,v gs =0v - - 0. 8 - 1.2 v notes : 1. pulse width < 300us, duty cycle < 2% 2. essentially independent of operating temperature typical characteristics 3. repetitive rating, pulse width limited by junction temperature tj(max)=150c. ratings are based on low frequency and duty cycles to keep initial t j =25c. 4. the maximum current rating is package limited 5. r ? ja is the sum of the junction - to - case and case - to - ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. m ount ed on a 1 inch 2 with 2oz. square pad of copper 6. l= 0.1 mh, i as = - 20 a, v gs = - 1 0v , v d s = - 25 v, r g =25 ohm, starting t j =25 o c 7. guaranteed by design, not subject to product ion testing.
p p j d14 p 10a jul y 21 ,201 5 - rev.00 page 3 t ypical characteristic curves fig.1 on - region characteristics fig. 2 transfer characteristics fig. 3 on - resistance vs. drain current fig. 4 o n - resistance vs. junction temperature fig. 5 on - resistance variation with vgs. fig. 6 body d i ode characteristics
p p j d14 p 10a jul y 21 ,201 5 - rev.00 page 4 t ypical characteristic curves fig. 7 gate - charge characteristics fig. 8 breakdown voltage variation vs. temperature fig. 9 threshold voltage variation with temperature . fig. 10 capacitance vs. drain - source voltage . fig. 11 maximum safe operating area
p p j d14 p 10a jul y 21 ,201 5 - rev.00 page 5 t ypical characteristic curves fig. 12 normalized thermal transient impedance
p p j d14 p 10a jul y 21 ,201 5 - rev.00 page 6 packaging infor mation . to - 252 dimension u nit: mm
p p j d14 p 10a jul y 21 ,201 5 - rev.00 page 7 part no packing code version moun ting pad layout part n o packing code package type packing type marking ver sion pjd14 p10a_l2_00001 to - 252 3,000pcs / 13
p p j d14 p 10a jul y 21 ,201 5 - rev.00 page 8 disclaimer
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