all 8051/52 resources: ! 8k bytes downloadable code ram. ! 256 bytes internal data ram. ! timers 0, 1, and 2. ! ports 0, 1, 2, and 3. ! all 8051 instructions. ! all 8051-equivalent pins. ! download code ram while reset. ! execute code when released. p - 5 1 po bo x 3 00 0, sa n g reg ori o c a 9 40 74 ? inf o@ co ntr olc hip s.c om te l: 6 50 -72 6-3 00 0 ? fa x: 65 0-7 26 -30 03 ? w ww .co ntr olc hip s.c om eisa/pc-104 interface: ! 45 eisa signals supported. ! uses one of 11 irq pins. ! software selectable irq 3?15. ! 20 isa address pins. ! 8 isa data bus pins. ! hardware or software reset. ! select segment addr 0 and a400 to ec00. ! uses 16k bytes of system memory space, normally in an upper memory block. special features: ! 4k byte dual port ram shared by host and P-51. ! dual data pointer. ! six new P-51 control registers mapped into dual port ram. ! square root function. ! debug capability. ! breakpoint and single-step. ! software interrupt generation. ! 3.3v 100-pin qfp . ! 5v i/o tolerant. ! 51 mhz operation cybernetic micro systems per iphe ral 8 051 sys tem on a c hip P-51 features the P-51 "peripheral 8051" is a new concept: an 8051 with built-in (e)isa or pc-104 interface and supporting subsystems. these include downloadable code ram, dual port ram, and all eleven irqs to the host. unlike classical 8051s, the P-51 naturally and easily interfaces to a host through simple standard buses, and its microsecond timing can provide real-time response to windows applications. p e r i p h e r a l 8 0 5 1 w i t h e i s a i n t e r f a c e p 3 . 6 p 3 . 7 c e o u t a l e c l k o u t b a 0 b a 1 b a 2 x t a l 2 x t a l 1 g n d g n d g n d b a 3 s d 0 s d 1 s d 2 s d 3 s d 4 s d 5 s d 6 s d 7 a l i i o c h r d y v d d v d d p 0 . 0 p 0 . 1 p 0 . 2 p 0 . 3 g n d p 0 . 4 p 0 . 5 p 0 . 6 p 0 . 7 p 2 . 0 p 2 . 1 p 2 . 2 p 2 . 3 p 2 . 4 p 2 . 5 p 2 . 6 p 2 . 7 g n d p 3 . 0 p 3 . 1 p 3 . 2 p 3 . 3 p 3 . 4 p 3 . 5 v d d p 1 . 7 p 1 . 6 p 1 . 5 p 1 . 4 p 1 . 3 p 1 . 2 p 1 . 1 p 1 . 0 b c l k r f r s h g n d g n d g n d i r q 1 5 i r q 1 4 i r q 1 2 i r q 1 1 i r q 1 0 i r q 9 i r q 7 i r q 6 i r q 5 i r q 4 i r q 3 r s t d r v s a 0 0 s a 0 1 s a 0 2 s a 0 3 s a 0 4 s a 0 5 s a 0 6 s a 0 7 s a 0 8 s a 0 9 s a 1 0 s a 1 1 s a 1 2 s a 1 3 s a 1 4 s a 1 5 s a 1 6 s a 1 7 s a 1 8 s a 1 9 m e m w m e m r c e v d d 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 7 5 7 4 7 3 7 2 7 1 7 0 6 9 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 1 23 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 20apr2000 4kx8 dual port ram 8kx8 code ram 256 x8 ram sfr dptr pc ale irq p -5 1 eisa p 0 p 1 p 2 p 3 address data control irq pc/104 8051 cpu P-51 architecture
think of the P-51 as the ultimate peripheral. y ou?ve used programmable timers, counters, interrupt controllers, and other special purpose peripherals. now the P-51 allows you to directly connect a general purpose 8051 computer, with all its hardware and software resources, to almost any bus: isa, pc/104, or micro-controller. y ou can drive a P-51 directly from an 8051, 386ex, or z80. via the P-51 chip select pin you can even hang multiple P-51s on a single bus. in this example a standard 8051 uses p0, p2, and control strobes to control a P-51, effectively doubling 8051 resources. the internal dual port ram serves as a mailbox for communicating between the two and also can be used as 4k ram data for a standard 8051. the standard 8051 can download code to the p51 while holding it in reset, then release the p51 to run the code. think of the possibilities! ( e ) i s a o r p c / 1 0 4 base pgad dr 3.3v 3 . 3 v t t l p o r t s ( 5 v o l t t o l e r a n t ) ale p0 p1 p2 p3 irq x86 hos t proc esso r data (8) addr (20) po bo x 3 00 0, sa n g reg ori o c a 9 40 74 ? inf o@ co ntr olc hip s.c om te l: 6 50 -72 6-3 00 0 ? fa x: 65 0-7 26 -30 03 ? w ww .co ntr olc hip s.c om cybernetic micro systems 20apr2000 p - 5 1 in the case of the 20-bit address presented by the eisa bus, the high order bits are compared to the base page address pins, and the P-51 is enabled when addresses match, thereby allowing the P-51 to be located at a specific range in x86 address space. by writing to a P-51 control register, the x86 can select (and enable) an irq signal (from irq3 to irq15). performs any action that is appropriate, then breakpoint and single stepping releases the P-51 by clearing a ?wait? bit in a dual port ram-mapped control register. the the P-51 supports breakpoints and single host can set a single-step bit in the control stepping. when the P-51 encounters a register, which causes the P-51 to interrupt breakpoint in the code, the P-51 copies its the host after every instruction execution. program counter into dual port ram, the combination of break and step provides interrupts the host with a breakpoint interrupt, features that would require an in-circuit and then waits for the host. the host emulator in a standard 8051 P-51 peripheral to an x86 P-51 peripheral to an 8051 p0 p1 p2 p3 inte rru pt 80 51 p2 p0 res et ale add /data add r hos t uc
d j j g e a b f c 1 0 0 p i n q u a d f l a t p k g ( g u l l - l e a d s ) g n d g n d g n d g n d g n d g n d g n d g n d v d d v d d v d d v d d a 1 4 . 0 m m + 0 . 4 b 1 2 . 0 + 0 . 1 c 1 . 4 t y p 1 . 7 m a x d 0 . 5 e 0 . 1 8 f 1 2 . 1 8 g 1 . 0 t y p j 0 . 5 + 0 . 2 j j h g 1 0 0 p i n s q u a r e q u a d f l a t p k g p c b p a d l a y o u t m m a 1 7 . 5 2 b 1 4 . 4 8 c 1 2 . 2 3 d 0 . 5 0 e 1 . 5 2 f 1 . 1 2 5 g 1 2 . 0 0 h 1 6 . 0 0 j 2 . 0 0 p a d 1 . 5 2 x 0 . 2 3 i n c h a 0 . 6 9 0 b 0 . 5 6 9 c 0 . 4 8 1 d 0 . 0 1 9 6 9 e 0 . 0 5 9 8 f 0 . 0 4 4 3 g 0 . 4 7 2 h 0 . 6 3 0 j 0 . 0 7 9 p a d 0 . 0 6 0 x 0 . 0 0 9 e a b c e f f d electrical specifications absolute maximum ratings: ambient t emperature under bias .. 0oc to 70oc storage t emperature.....................?55oc to +125oc vdd supply voltage.......................?0.3v to +4.0v voltage on any i/o pin from gnd..?0.3v to +6.0v power dissipation..........................500 mw dc and operating characteristics: t emperature range....................... 0oc to 70oc vdd supply voltage.......................+3.0v to +3.6v c r y s t a l o s c i l l a t o r 1 - 6 0 m h z + 3 . 3 v p - 5 1 x t a l 1 x t a l 2 c r y s t a l o s c i l l a t o r c i r c u i t 1 m w 0 - 2 0 0 w x t a l < 2 6 m h z 5 - 3 0 p f 5 - 3 0 p f x t a l 1 x t a l 2 p - 5 1 f u n d a m e n t a l c r y s t a l c i r c u i t 1 m w 0 - 2 0 0 w x t a l > 2 6 m h z 5 - 3 0 p f 5 - 3 0 p f 0 . 0 1 u f 3 . 3 u h x t a l 1 x t a l 2 p - 5 1 t h i r d o v e r t o n e c r y s t a l c i r c u i t clock circuits an external clock oscillator between 1 and 60 mhz is used on xtal1, and must use the same vdd voltage as the P-51. the frequency range for the crystal circuit is 4 to 51 mhz. the circuitry differs for fundamental vs. third- overtone crystals. the boundary between the two types is approx 26 mhz (consult crystal manufacturer specs). like standard 8051 devices, the internal P-51 serial baud rates assume an 11.059 mhz clock and multiples thereof. po bo x 3 00 0, sa n g reg ori o c a 9 40 74 ? inf o@ co ntr olc hip s.c om te l: 6 50 -72 6-3 00 0 ? fa x: 65 0-7 26 -30 03 ? w ww .co ntr olc hip s.c om cybernetic micro systems 20apr2000 physical specifications p - 5 1 sym parameter min typ max unit remarks icc pwr supply current 46 80 ma 60 mhz 20 40 ma 40 mhz 16 35 ma 11 mhz vih input high voltage 2.0 5.5 v 5 volt tolerant inputs, ttl compatible vil input low voltage -0.2 0.8 v ttl compatible iih input high current -10 +10 ua vin = vdd iil input low current -10 +10 ua vin = gnd voh output high voltage 2.4 v ioh = -4 ma vol output low voltage 0.4 v iol = 4 ma 0.4 v iol = 8 ma on iochrdy ioz tri-state leakage current 10 +10 ua vin = gnd to vdd ipu pull-up current 22 66 160 ua vin = gnd, r ~ 50k w fcy crystal frequency 4 51 mhz see clock circuits fos oscillator frequency 1 60 mhz see clock circuits a peripheral device the P-51 name is a reminder that this device is a peripheral 8051 processor, not a standalone processor . the name P-51 focuses on this unique aspect of the device: a peripheral 8051 requires a host to which it is peripheral.
P-51 demonstration circuit b01 b02b03 b04 b05 b06 b07 b08 b09 b10 b11 b12b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b25 b26 b27 b28 b29 b30 b31 gnd rstdrv +5v irq9 -5v drq2 -12v srdy/ +12v gnd smemw/ smemr/ iow/ ior/ dack3/ drq3 dack1/ drq1 rfrsh/ sysclk irq7 irq6 irq5 irq4 irq3 dack2/ tc bale +5v osc gnd d01 d02d03 d04 d05 d06 d07 d08 d09 d10 d11 d12d13 d14 d15 d16 d17 d18 memcs16/ iocs16 irq10 irq11 irq12 irq15 irq14 dack0/ drq0 dack5/ drq5 dack6/ drq6 dack7/ drq7 +5v master/ gnd isa bus - pc/104 signals isa bus - pc/104 signals a01 a02a03 a04 a05 a06 a07 a08 a09 a10 a11 a12a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 i/ochk/ sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 iochrdy aen sa19 sa18 sa17 sa16 sa15 sa14 sa13 sa12 sa11 sa10 sa09 sa08 sa07 sa06 sa05 sa04 sa03 sa02 sa01 sa00 1 1019 17 2 15 4 13 6 11 8 20 3 18 5 16 7 14 9 12 1 10050 51 53 54 55 56 57 58 59 60 61 52 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 47 48 11 10 20 21 22 23 24 25 19 18 17 15 16 vdd vddvdd vdd ali sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 iochrdy sa19 sa18 sa17 sa16 sa15 sa14 sa13 sa12 sa11 sa10 sa09 sa08 sa07 sa06 sa05 sa04 sa03 sa02 sa01 sa00 resetdrv memw memr refresh bclk irq9 irq7 irq6 irq5 irq4 irq3 irq10 irq11 irq12 irq15 irq14 9 8 7 6 5 4 3 2 9998 97 96 94 93 92 91 90 89 88 87 86 85 84 83 81 80 79 78 77 76 75 74 73 72 71 67 66 70 69 68 62 49 12 13 14 63 64 65 82 95 p1.0 p1.1p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 ceout ale clkout xtal2 xtal1 ba0 ba1 ba2 ba3 ce vss vss vss vss vss vss vssvss cs-5201-373 volt age regulator vin gnd vout 1n4002 74hct244 hlmp-6600 leds +5v +3.3v 22uf 47uf +3.3v 0.1uf crystal oscillator 1-60 mhz addr switch P-51 cybernetic micro systems 12 may 2000 www.controlchips.com +5v 0.1uf +3.3v 0.22uf 0.22uf 470pf 470pf c01 c02c03 c04 c05 c06 c07 c08 c09 c10 c11 c12c13 c14 c15 c16 c17 c18 sbhe/ la23 la22 la21 la20 la19 la18 la17 memr/ memw/ sd08 sd09 sd10 sd11 sd12 sd13 sd14 sd15 po bo x 3 00 0, sa n g reg ori o c a 9 40 74 ? inf o@ co ntr olc hip s.c om te l: 6 50 -72 6-3 00 0 ? fa x: 65 0-7 26 -30 03 ? w ww .co ntr olc hip s.c om cybernetic micro systems 12may2000 p - 5 1
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