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f edl610q359 - 01 issue date : j ul 31 , 201 5 ML610Q359 /ml610q360 8 - bit microcontroller with voice output function 1 / 30 general description equipped with a 8 - bit cpu nx - u8/100, the ML610Q359 is a high - performance 8 - bit cmos microcontroller that integrates a wide variety of peripherals such as, 12 - bit a/d converter, timer, synchronous serial port, uart, and voice output fun ction . the nx - u8/100 cpu is capable of executing instructions efficiently on a one - instruction - per - clock - pulse basis through parallel processing by the 3 - stage pipeline d architecture . in addition, it has an on - chip debugging function, which allows softw are debugging/rewriting with the lsi mounted on the board. features ? cpu ? 8 - bit risc cpu (cpu name : nx - u8/100) ? instruction system : 16- bit instructions ? instruction set: transfer, arithmetic operations, comparison, logic operation s, multiplication / di vision , bit manipulations , bi t logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on ? on - chip debug function ? minimum instruction execution time approx 30.5 s ( at 32.768 khz system clock ) approx 0.125 s ( at 8mhz system clock ) dv dd = 2.2 to 3.6v approx 0.250 s ( at 4mhz system clock ) dv dd = 2.0 to 3.6v ? internal memory ? has 160 - kbyte flash rom ( 80k 16 - bit) built in. ( 544 byte of test domain that it cannot be used is included ) ? has 3 - kbyte flash rom built in. ( area in which self rewriting is possible .512byte 6 ) ? has 2 - k b yte ram ( 2 0 48 8 bits) built in. ? has 16 - m b it p2rom built in. (only ml610q360) ? interrupt controller ? 2 non - maskable interrupt sources (internal source: 1, external source: 1) ? 25 maskable interrupt so urces (internal source: 1 9 , external source: 6 ) ? time base counter ? low - speed time base counter 1 ch annel ? high - speed time base counter 1 ch annel ? watchdog timer ? generates a non - maskable interrupt upon the first overflow and a system reset occu rs upon the second ? free running ? overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s) ? timer s ? 8 bits 8ch (16 - bit configuration available)
f edl610q359 - 01 ML610Q359 /ml610q360 2 / 30 ? voice output function ? voice synthesis method: 4 - bit adpcm2 / non - linear pcm / straight 8 - bit pcm / straight 16- bit pcm ? sampling frequency: 8/16/32 khz; 10.7/21.3 khz; 6.4/12.8/25.6 khz ? d/a converter ? 12- bit d/a converter ? speaker amplifier output power ? 0.5 w(at 3 .0 v) ? thermal detection circuit ? disconnection detection circuit ? synchr onous serial port ? 2ch ? master / slave selectable ? lsb first /msb first selectable ? 8 - bit length /16 - bit length selectable ? uart ? half - duplex 2ch or half - duplex 1ch + f ull - duplex 1ch ? txd / rxd ? bit length, parity/no parity, odd parity/even parity, 1 stop bit /2 stop bits ? positive logic / negative logic selectable ? built - in baud rate generator ? successive approximation type a/d converter ? 12- bit a/d converter ? input: 4ch (ch0 - 2: external input ch3: a r egulator output (v ddr ) or a temperatur e sensor output (tempo) ? conversion time: 2 0 s per channel at 8 mhz av dd R 2.5v ? conversion time: 2 8 s per channel at 8 mhz av dd R 2.2v ? t emperature sensor ? measuring range : ? 40 c to +85 c ? regulator output (v ddr ) ? 1.5v 50mv(at ? 40 c to +85 c and w hen a v ddr pin is no - load ) ? 1.5v / 0v / hiz selectable ? general - purpose ports ? non - maskable interrupt input port 1ch ? input - only port 7 ch ? output - only port 3ch (including secondary functions) ? input/output 29 ch (including secondary functions) ? s upply voltage supervisor circuit ? j udgment accuracy : 1.5 % (typ.) ? j udgment voltage: a binary to selection is possible ? this function can be used as s upply voltage supervisor reset.
f edl610q359 - 01 ML610Q359 /ml610q360 3 / 30 ? reset ? reset through the rese t _n pin ? power - on reset generati on when powered on ? reset by the watchdog timer (wdt) overflow ? reset when oscillation stop of the low - speed clock is detected ? v oltage level supervisor reset ? clock ? low - speed clock (this lsi can not guarantee the ope ration withoug low - speed clock) crystal oscillation (32.768 khz) ? high - speed clock built - in oscillation ( 8 .192 mhz) , external clock ? power management ? halt mode: instruction execution by cpu is suspended ( peripheral circuits are in operating states ) . ? stop mode: stop of low - speed oscillation and high - speed oscillation ( operations of cpu and peripheral circuits are stopped. ) ? clock gear: the frequency of high - speed system clock can be changed by software (1/1 , 1/2 , 1/4 , or 1/8 of the oscillation clock ) ? block control function: operation of an intact functional block circuit is powerd down. (register reset and clock stop) ? shipment ? 64- pin tqfp ML610Q359 - xxx tb ( blank product: ML610Q359 - nnntb ) ml610q360 - xxxtb (blank product: ml610q360 - nnntb) xxx: rom code number ? guaranteed operating range ? operating temperature: ? 40 c to 85 c (for ML610Q359) : ? 10 c to 65 c (p2rom movment of ml610q360) ? operating voltage: dv dd = 2.0v to 3.6v, spv dd = 2.2v to 3.6v, av dd = 2.2v to 3.6v
f edl610q359 - 01 ML610Q359 /ml610q360 4 / 30 block diagram block diagram of ML610Q359 * : secondary or tertiary or f ourthly function * 1 : it is the point with the difference in ML610Q359 and ml610q360 figure 1 block diagram of ml 610q 3 5 9 program memory flash 160k byte ram 2048byte interrupt controller cpu (nx - u8/100) timing controller ea sp instruction decoder bus controller instruction register tbc int 4 int 8 8bit timer 8 gpio nmi p20 to p22 int 7 p50 t o p57 * 1 data - bus test 0 reset_n osc power v ddl reset & test alu epsw1 3 psw elr1 3 lr ecsr1 3 dsr/csr pc greg 0 15 dv dd dv ss outclk* uart rxd0*, txd0* int 3 lsclk* p40 t o p47 on - chip ice p00 t o p0 5 ssio sck0* sin0* 1 sout0* int 2 wdt int 12bit - adc ain0 to ain 2 av dd av ss 1 int voicecnt sg aout speaker amp spp spm sg spv dd spv ss spin svs temperature sensor int 1 rxd1* txd1* p10 v ddx rxd2* txd2* v ddr vddr av dd av ss test1_n sck1* sin1* sout1* p30 to p37 xt1 xt0 p 6 0 t o p 63
f edl610q359 - 01 ML610Q359 /ml610q360 5 / 30 block diagram of ml610q3 60 * : secondary or tertiary or f our thly function * 1 : it is the point with the difference in ML610Q359 and ml610q360 figure 2 block diagram of ml 610q360 program memory flash 160 kbyte ram 2048b yte interrupt controller cpu (nx - u8/100) timing controller ea sp instruction decoder bus controller instruction register tbc int 4 int 8 8bit timer 8 gpio nmi p20 to p22 int 7 p50 t o p5 3 * data - bus test 0 reset_n osc power v ddl reset & test alu epsw1 3 psw elr1 3 lr ecsr1 3 dsr/csr pc greg 0 15 dv dd dv ss outclk* uart rxd0* , txd0* int 3 lsclk* p40 to p4 7 on - chip ice p0 0 to p05 ssio sck0* sin0* sout0* int 2 wdt int 12bit - adc ain0 to ain av dd av ss 1 int voicecnt sg aout speaker amp spp spm sg spv dd spv ss sp in svs temperature sensor int 1 rxd1* txd1* p10 v ddx rxd2* txd2* v ddr vddr av dd av ss test 1_n xt1 xt0 p 6 0 t o p 63 p 3 0 t o p 3 7 dv dd dv ss * 1 pvpp port * * 1 p5 4 ( s i n1 ) * * 1 p55( sck 1 ) * * 1 p56(so ut1 ) * 1 p57 p s o psck ps i p csb * 1 16mbit p2rom testo3 to testo6 *1
f edl610q359 - 01 ML610Q359 /ml610q360 6 / 30 pin configuration ml610q3 5 9 t qfp package product * : it is the point wi th the difference in ML610Q359 and ml610q360 ( nc) : no connection figure 3 pin configuration of ml 610q3 5 9 package product p55 * spm p33 p62 spp v ddl dv dd dv ss v ddx xt0 xt1 test0 test1_n reset_n p34 p35 p36 p37 v ddr ain0 ain1 ain2 av dd av ss p56 * p40 p41 p42 p43 testo2 p44 p45 p46 p47 p50 p51 p52 p53 p10 p63 nmi p20 p01 p02 p03 sg aout spin spv dd spv ss p21 dv ss p00 p22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 * p54 * p57 * (nc) p60 p61 p30 p31 p32 p04 p05
f edl610q359 - 01 ML610Q359 /ml610q360 7 / 30 ml610q360 tqfp package product * : it is the point with the difference in ML610Q359 and m l610q360 figure 4 pin configuration of ml 610q3 60 package product testo4 * spm p33 p62 spp v ddl dv dd dv ss v ddx xt0 xt1 test0 test1_n reset_n p 34 p35 p36 p37 v ddr ain0 ain1 ain2 av dd av ss testo5 * p40 p41 p42 p43 testo2 p44 p45 p46 p47 p50 p51 p52 p53 p10 p63 nmi p20 p01 p02 p03 sg aout spin spv dd spv ss p21 dv ss p00 p22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 * test o6 p60 p61 p30 p31 p32 p05 p04 * testo3 * pvpp
f edl610q359 - 01 ML610Q359 /ml610q360 8 / 30 list of pins p in no primary function secondary function tertiary function q359 q360 pin name i/o description pin name i/o description pin name i/o description 13,55 13,55 d v ss ? negative power supply pin ? ? ? ? ? ? 12 12 d v dd ? positive power supply pin ? ? ? ? ? ? 11 11 v ddl ? power supply for internal logic (internally generated) ? ? ? ? ? ? 14 14 v ddx ? power supply pin for oscillation (internally generated) 27 27 v ddr ? reference voltage output of 1.5v ? ? ? ? ? ? 64 64 sp v ss ? negative power supply pin for built - in speaker amplifier ? ? ? ? ? ? 63 63 sp v dd ? positive power supply pin for built - in speaker amplifier ? ? ? ? ? ? 32 32 av ss ? negative power supply pin for successive - approximation type adc /op - amp ? ? ? ? ? ? 31 31 av dd ? positive power supply pin for successive - approximation type adc /op - amp ? ? ? ? ? ? ? 8 pvpp ? high voltage power supply pin of data to building p2rom ? ? ? ? ? ? 3 3 test 0 i/o inp ut/output pin for testing ? ? ? ? ? ? 4 4 test 1_n i input pin for testing ? ? ? ? ? ? 39 39 testo2 ? o utput pin for testing ? ? ? ? ? ? 5 5 reset_n i reset input pin ? ? ? ? ? ? 16 16 xt0 i low - speed clock oscillation pin ? ? ? ? ? ? 15 15 xt1 o low - s peed clock oscillation pin ? ? ? ? ? ? 61 61 aout o line output ? ? ? ? ? ? 62 62 spin i analog input to the built - in speaker amplifier ? ? ? ? ? ? 60 60 sg o reference power supply pin of the built - in speaker amplifier ? ? ? ? ? ? 2 2 spp o positive o utput pin of the built - in speaker amplifier ? ? ? ? ? ? 1 1 spm o negative output pin of the built - in speaker amplifier ? ? ? ? ? ? 28 28 ain0 i successive - approximation type adc input ? ? ? ? ? ? 29 29 ain1 i successive - approximation type adc input ? ? ? ? ? ? 30 30 ain2 i successive - approximation type adc input ? ? ? ? ? ?
f edl610q359 - 01 ML610Q359 /ml610q360 9 / 30 pin no primary function secondary function tertiary function fourthly function q359 q360 pin name i/o description pin name i/o description pin name i/o description pin name i/o description 51 51 nmi i i nput port, non- maskable interrupt ? ? ? ? ? ? ? ? ? 56 56 p0 0 /exi 0 i i nput port / external ? ? ? ? ? ? ? ? ? 57 57 p0 1/exi1 i i nput port / external ? ? ? ? ? ? ? ? ? 58 58 p0 2/exi2 / rxd0 / rxd2 i i npu t port / external interrupt / uart0 data input / uart 2 data input ? ? ? ? ? ? ? ? ? 59 59 p0 3/exi3 / rxd1 i input port / external interrupt / uart 1 data input ? ? ? ? ? ? ? ? ? 17 17 p0 4/exi4/ t02p0ck i input port / external interrupt / timer 0,2 externa l clock input ? ? ? ? ? ? ? ? ? 18 18 p0 5/exi5/ t13p0ck i input port / external interrupt / timer 1,3 external clock input ? ? ? ? ? ? ? ? ? 48 48 p10 i input port osc0 i high - speed oscillation ? ? ? ? ? ? 52 52 p20 / led0 o output port / led drive lsc lk o low - speed clock output ? ? ? ? ? ? 53 53 p21 / led1 o output port / led drive outclk o high - speed clock output ? ? ? ? ? ? 54 54 p2 2/ led2 o output port / led drive ? ? ? ? ? ? ? ? ? 19 19 p3 0 i/o input/output port ? ? ? ? ? ? ? ? ? 20 20 p3 1 i/o i nput/output port ? ? ? ? ? ? ? ? ? 21 21 p3 2 i/o input/output port ? ? ? ? ? ? ? ? ? 22 22 p3 3 i/o input/output port ? ? ? ? ? ? ? ? ? 23 23 p34 i/o input/output port ? ? ? ? ? ? ? ? ? 24 24 p35 i/o input/output port ? ? ? ? ? ? ? ? ? 25 25 p36 i/o in put/output port ? ? ? ? ? ? ? ? ?
f edl610q359 - 01 ML610Q359 /ml610q360 10/ 30 pin no primary function secondary function tertiary function fourthly function q359 q360 pin name i/o description pin name i/o description pin name i/o description pin name i/o description 35 35 p40 i/o input/outpu t port ? ? ? sin0 i ssio0 data input ? ? ? 36 36 p41 i/o input/output port ? ? ? sck0 i/o ssio0 synchronous clock input/output ? ? ? 37 37 p42 i/o input/output port rxd0 i uart0 data input sout0 o ssio0 data output rxd 2 i uart 2 data input 38 38 p43 i/o input/output port txd0 o uart0 data output ? ? ? txd 2 o uart 2 data output 40 40 p4 4 i/o input/output port ? ? ? sin 0 i ssio0 data input ? ? ? 41 41 p4 5 i/o input/output port ? ? ? sck 0 i/o ssio0 synchronous clock input/output ? ? ? 42 42 p4 6 i/o input/o utput port ? ? ? sout 0 o ssio0 data output ? ? ? 43 43 p4 7 i/o input/output port ? ? ? ? ? ? ? ? ? 44 44 p50 i/o input/output port ? ? ? sin 1 i ssio 1 data input ? ? ? 45 45 p51 i/o input/output port ? ? ? sck 1 i/o ssio 1 synchronous clock input/output ? ? ? 46 46 p52 i/o input/output port rxd 1 i uart 1 data input sout 1 o ssio 1 data output ? ? ? 47 47 p53 i/o input/output port txd 1 o uart 1 data output ? ? ? txd 2 o uart 2 data output 6 ? p54/ test o3 i/o input/output port ? ? ? sin 1 i ssio 1 data input ? ? ? 33 ? p55/ test o4 i/o input/output port ? ? ? sck 1 i/o ssio 1 synchronous clock input/output ? ? ? 34 ? p56/ test o5 i/o input/output port ? ? ? sout 1 o ssio 1 data output ? ? ? 7 ? p57/ test o6 i/o input/output port ? ? ? ? ? ? ? ? ? 9 9 p6 0 i/o input/out put port ? ? ? ? ? ? ? ? ? 10 10 p6 1 i/o input/output port ? ? ? ? ? ? ? ? ? 49 49 p6 2 i/o input/output port ? ? ? ? ? ? ? ? ? 50 50 p6 3 i/o input/output port ? ? ? ? ? ? ? ? ? note: the function which has not been chosen is lost when it is chosen any of a secondary function, the tertiary function, and the f ourthly function they are . however, when using it as an input, it is possible to read input data with a port - n data register.
f edl610q359 - 01 ML610Q359 /ml610q360 11 / 30 complement: it is only ml610q360. ML610Q359 does not correspond. p54 - p5 7 are connected with built - in p2 rom inside the chip, and each function exists. an external terminator name is set to testo3 - testo6. please make the external terminator open. the content of contact with p2 rom is shown below. the terminator of built - in p2 ro m explanation pso serial data output it connects with p54/sin1( tertiary functional use) inside. psck serial clock input it connects with p55/sck1( tertiary functional use) inside. psi serial data input it connects with p56/sout1( tertiary functional use) inside. pcsb chip select input it connects with p57(primary functional use) inside.
f edl610q359 - 01 ML610Q359 /ml610q360 1 2 / 30 pin description pin name i/o description primary/ secondary logic power supply dv ss ? negative power supply pin ? ? dv dd ? positive power supply pin ? ? v ddl ? positive power supply pin for internal logic (internally generat ed) connect capacitors (c l ) (see measuring circuit 1) between this pin and d v ss . ? ? v ddx ? power supply pin for oscillation ( internally generated ) . capacitors c x ( see measuring circuit 1) are connected between this pin and d v ss . ? ? v ddr ? reference vol tage output . capacitors c r ( see measuring circuit 1) are connected between this pin and d v ss . ? ? spv ss ? negative power supply pin for built - in speaker amplifier ? ? spv dd ? positive power supply pin for built - in speaker amplifier ? ? av ss ? negative po wer supply pin for successive - approximation type adc/op - amp ? ? av dd ? positive power supply pin for successive - approximation type adc/op- amp ? ? pvpp high voltage power supply pin of the data write to building p2rom into. besides, fix at the v ss level. ? ? test test0 i/o input/output pin for testing. has a pull - down resistor built in. ? positive test1_n i input pin for testing. has a pull - up resistor built in. ? negative testo2 ? o utput pin for testing ? ? system reset_n i reset input pin . when t his pin is set to a ? l ? level, the device is placed in system reset mode and the internal circuit is initialized . if after that this pin is set to a ? h ? level, program execution starts . this pin has a pull - up resistor built in. ? negative xt0 i ? positiv e xt1 o ? negative osc0 i secondary positive lsclk o low - speed clock output. this function is allocated to the secondary function of the p20 pin. secondary ? outclk o high - speed clock output. this function is allocated to the secondary function of th e p21 pin. secondary ? general - purpose input port p00 to p05 i general - purpose input ports. primary positive p10 i general - purpose input/output ports. provided with a secondary function for each port. cannot be used as ports if their secondary function s are used. primary positive
f edl610q359 - 01 ML610Q359 /ml610q360 13/ 30 pin name i/o description primary/ secondary/ tertiary / fourthly logic general - output input port p20 to p22 o general - purpose output ports. provided with a secondary function for each port. cannot be used as ports if their secondary functions are used. primary positive general - purpose input/output port p30 to p37 i/o general - purpose input/output ports. provided with a secondary function for each port. cannot be used as ports if their secondary functions are used. primary positive p40 to p47 p50 to p57 p60 to p63 uart txd0 o uart0 data output pin. allocated to the secondary function of the p43 pin. secondary positive rxd0 i uart0 data input pin. allocated to the primary function of the p02 pin and the seco ndary function of the p42 pin. secondary positive txd1 o uart1 data output pin. allocated to the secondary function of the p53 pin. secondary positive rxd1 i uart1 data input pin. allocated to the primary function of the p03 pin and the secondary functio n of the p52 pin. secondary positive txd2 o uart0 data output pin. allocated to the f ourthly function of the p43 pin and the f ourthly function of the p53 pin. fourthly positive rxd2 i uart0 data input pin. allocated to the primary function of the p02 pin and the f ourthly function of the p42 pin. fourthly positive synchronous serial (ssio) sin0 i synchronous serial data input pin. allocated to the tertiary function of the p40 pin and the tertiary function of the p44 pin. tertiary positive sck0 i/o syn chronous serial clock input/output pin. allocated to the tertiary function of the p41 pin and the tertiary function of the p45 pin. tertiary ? sout0 o synchronous serial data output pin. allocated to the tertiary function of the p42 pin and the tertiary function of the p46 pin. tertiary positive sin1 i synchronous serial data input pin. allocated to the tertiary function of the p50 pin and the tertiary function of the p54 pin . tertiary positive sck1 i/o synchronous serial clock input/output pin. alloca ted to the tertiary function of the p51 pin and the tertiary function of the p55 pin. tertiary ? sout1 o synchronous serial data output pin. allocated to the tertiary function of the p52 pin and the tertiary function of the p56 pin. tertiary positive ex ternal interrupt nmi i external non - maskable interrupt input pin. the interrupt occurs on both the rising and falling edges. primary positive/ negative exi0 ? exi5 i external maskable interrupt input pins. it is possible, for each bit, to specify whether t he interrupt is enabled and select the interrupt edge by software. allocated to the primary function of the p00 ? p05 pins. primary positive/ negative
f edl610q359 - 01 ML610Q359 /ml610q360 14/ 30 pin name i/o description primary/ secondary/ tertiary / fourthly logic led drive led0 ? led2 o pins for led driving. allocated to the primary function of the p20 to p22 pins. primary positive/ negative voice output function aout o line output pin. the case of built - in speaker amplifier use , connect capacitors (c aosp ) between this pin and the spin pin. ? ? spin i analog input pin of the internal speaker amplifier. ? ? sg o reference voltage output p in of the internal speaker amplifier. ? ? spp o positive output pin of the internal speaker amplifier. ? ? spm o negative output pin of the internal speaker amplifier. ? ? successive - approximation type a/d converter ain0 ? ain2 i analog inputs to ch0 ? c h2 of the successive - approximation type a/d converter. ? ?
f edl610q359 - 01 ML610Q359 /ml610q360 15/ 30 termination of unuse d pins how to t erminate u nused p ins pin recommended pin termination reset_n open test0 open test1_n open testo2 open a v dd connect to d v dd avss connect to d vss ain0 to ain2 open spvdd connect to d vdd sp v ss connect to d v ss pvpp open aout open spin open sg open spp o pen spm open p0 0 to p0 5 connect to d v dd or d v ss p10 connect to d v dd or d v ss p20 to p22 open p30 to p37 open p4 0 to p 47 open p 5 0 to p 57 open testo3 to testo6 open p60 to p63 open vddr open note: for unused input ports or unused input/output port s, if the corresponding pins are configured as high - impedance inputs and left open, the supply current may become excessively large. therefore, it is recommended to configure those pins as either inputs with a pull - down resistor/pull - up resistor or outputs .
f edl610q359 - 01 ML610Q359 /ml610q360 16/ 30 electrical character istics absolute maximum ratings ( d v ss = av ss = spv ss = 0v) parameter symbol condition rating unit power supply voltage 1 d v dd ta = 25c ? 0.3 to + 7 . 0 v power supply voltage 2 av dd ta = 25c ? 0.3 to + 7 . 0 v power supply voltage 3 spv dd ta = 25c ? 0.3 to + 7 . 0 v power supply voltage 4 v ddl ta = 25c ? 0.3 to + 3 .6 v power supply voltage 5 v ddx ta = 25c ? 0.3 to + 3.6 v power supply voltage 6 v ddr ta = 25c ? 0.3 to + 3.6 v power supply voltage 7 testo2 ta = 25c ? 0.3 to + 9 .5 v input voltage v in ta = 25c ? 0.3 to d v dd +0.3 v output voltage v out ta = 25c ? 0.3 to d v dd +0.3 v output current 1 i out1 port 3, 4 , 5, 6 ta = 25c ? 12 to +11 ma output current 2 i out2 port 2 , ta = 25c ? 12 to + 60 ma power dissipation pd ML610Q359 ta = 25c 472 mw ml610q360 562 mw storage temperature t stg D ? 55 to +150 c recommended operating conditions ( d v ss = av ss = spv ss = 0v) parameter symbol condition range unit operating temperature t op D ? 40 to + 85 c operating voltage d v dd D 2. 0 to 3.6 v spv dd D 2. 2 to 3.6 av dd D 2.2 to 3.6 operating f requency ( cpu) f op dv dd =2.2v to 3.6v 3.8 k to 8.4 m hz dv dd =2. 0 v to 3.6v 3.8k to 4.2m low speed clock oscillation frequency f xtl D 32.768k hz low speed clock oscillation capacitor externally connected to low speed clock oscillation pin c dl mc - 146 (ep son toyocom) 14 pf c gl 14 capacitor externally connected to v ddl pin c l D 10 30% f capacitor externally connected to v ddx pin c x D 0.1 30% f capacitor externally connected to v ddr pin c r D 1 30% f capacitor externally connected to aout pin ? spi n pin c aosp D 0.022 30% f capacitor externally connected to sg pin c sg D 0.1 30% f
f edl610q359 - 01 ML610Q359 /ml610q360 17/ 30 flash memory operating conditions ( d v ss = av ss = spv ss = 0v) parameter symbol condition range unit operating temperature t op at write/erase -2 0 to + 7 5 c operating voltage d v dd at write/ erase 2.2 to 3.6 v maximum rewrite count c ep d data area ( 1024 b ) 6000 times c ep p program area 100 data retention period y dr D 1 0 years dc characteristics (1 of 5) ( dv dd = av dd = sp v dd = 2. 0 to 3.6 v, d v ss = av ss = spv ss = 0v, ta = ? 40 to +85 c , unless otherw ise specified) parameter symbol condition min. typ. max. unit measuring circuit high - speed oscillation start time t xt h D D 1 3 ms 1 low - speed crystal oscillation start time t xtl D D D 2 s high - speed oscillator frequency f hpll lsclk=32.768khz typ - 2.5% 8.192m typ +2.5% hz reset pulse width p rst D 100 D D s reset noise rejection pulse width p nrst D D D 0. 3 time from power - on reset to power -up t por D D D 10 ms reset reset_n reset by reset_n pin dv dd 0.9 v dd 0.1 v dd t por power - on reset p rst vil1 vil1
f edl610q359 - 01 ML610Q359 /ml610q360 18/ 30 dc characteristics (2 of 5) ( dv dd = av dd = sp v dd = 2. 3 to 3 .6 v, d v ss = av ss = spv ss = 0v, ta = ? 40 to +85 c , unless otherwise specified ) parameter symbol condition min. typ. max. unit measuring circuit line amplifier output voltage range v ad at 10k load for dv ss sp v dd 1/6 ? sp v dd 5/6 v 1 sg output voltage v sg D 0.95 sp v dd /2 sp v dd /2 1.05 sp v dd /2 v sg output resistance r sg D 57 96 135 k ? spm , spp output load resistance r lsp D 8 D D ? speaker amplifier output power p spo1 spv dd = 3.0 v , f = 1khz , rspo = 8 ? , thd 1 7 % at spin input ? 0. 5 ? w output offset vo ltage between spm and spp with no signal present v of spv dd =3.0v, spin ? spm , g ain = +6db with a load of 8 ? ? 3 0 ? + 3 0 mv
f edl610q359 - 01 ML610Q359 /ml610q360 19/ 30 dc characteristics (3 of 5) ( dv dd = av dd = sp v dd = 2. 0 to 3.6 v, d v ss = av ss = spv ss = 0v, ta = ? 40 to +85 c , unless otherwise specified) pa rameter symbol condition min. typ. max. unit meas uring circuit supply current 1 idd1 cpu : in stop state. low - speed/high- speed oscillation: stopped ta Q + 5 0 c D 0.5 2. 5 a 1 ta Q +85 c D 0.5 8 supply current 2 idd2 cpu : in halt state (ltbc , wdt : operating *2 ) high - speed oscillation:stopped ta Q + 5 0 c D 1 .7 3. 5 ta Q +85 c D 1 .7 10 supply current 3 idd3 cpu : running at 32.768 khz * 1 high - spe ed oscillation: stopped D 16 25 supply current 4 idd4 cpu : running at 8 .192 m hz high - speed oscillation:stopped d v dd = spv dd = 3.0v D 4 .5 1 0 ma * 1 : case when the cpu operating rate is 100% (with no halt state) * 2 : significant bits of blkcon0 to blkcon 4 registers are all ?1 ?. supply - voltage supervisor circuit ( dv dd = av dd = sp v dd = 2. 0 to 3.6 v, d v ss = av ss = spv ss = 0v, ta = ? 40 to +85 c , unless otherwise specified) parameter symbol condition min. typ. max. unit meas uring circuit vls judging voltage v svs1 ta = 25 c d v dd falling typ. - 1.5 % 2.05 typ. +1.5 % v 1 d v dd rising 2.13 v svs2 ta = 25 c d v dd falling typ. - 1.5 % 2.25 typ. +1.5 % d v dd rising 2.33 vl s self - consumption current i svs D D 10 D a temperature sensor ( dv dd = av dd = sp v dd = 2. 0 to 3.6 v, d v ss = av ss = spv ss = 0v, ta = ? 40 to +85 c , unless otherwise specified) parameter symbol condition min. typ. max. unit meas uring circuit tempo output voltage v tempo ta = 25 c 0.95 1.3 1.6 v 1 tempo temperature inclination S tempo ta= - 40 to +25 D - 3.9 D mv/ ta=+25 to +85 D - 4.1 D regulator output ( dv dd = av dd = sp v dd = 2. 0 to 3.6 v, d v ss = av ss = spv ss = 0v, ta = ? 40 to +85 c , unless otherwise specified) parameter symbol condition min. typ. max. u nit meas uring circuit v ddr output voltage v ddr n o load 1.45 1.5 1.55 v 1 dc characteristics (4 of 5) ( dv dd = av dd = sp v dd = 2. 0 to 3.6 v, d v ss = av ss = spv ss = 0v, ta = ? 40 to +85 c , unless otherwise specified) parameter symbol condition min. typ. max. unit meas uring circuit
f edl610q359 - 01 ML610Q359 /ml610q360 20/ 30 output voltage 1 (p20 to p2 2 ) (p3 0 to p37 ) (p40 to p4 7 ) (p5 0 to p5 7 ) (p 60 to p 63 ) voh1 ioh1 = ? 0.5ma d v dd ? 0.5 D D v 2 vol1 iol1 = +0.5ma D D 0.5 output voltage 2 ( p20 to p22) vol2 when led drive mode is selected iol2=+ 20 ma d v dd R 2. 5 v D D 0.5 ` (p20 to p2 2 ) (p3 0 to p37 ) (p40 to p4 7 ) (p5 0 to p5 7 ) (p 60 to p 63 ) iooh voh = d v dd (in hig h - impedance state) D D 1 a 3 iool vol = d v ss (in high - impedance state) ? 1 D D input current 1 (reset_n) ( test1 _n) iih1 vih1 = d v dd 0 D ? 1 a 4 iil1 vil1 = d v ss ? 1 500 ? 300 ? 20 input current 2 (nmi) (p0 0 to p0 5 ) (p1 0) (p3 0 to p37 ) (p40 to p4 7 ) (p5 0 to p5 7 ) (p60 to p 63) iih2 vih2 = d v dd ( when pulled down) 2 30 2 5 0 iil2 vil2 = d v ss ( when pulled up) ? 2 5 0 ? 30 ? 2 iih2z vih2 = d v dd (in high - impedance state) D D 1 iil2z vil2 = d v ss (in high - impedance state) -1 D D input current 3 ( test0 ) iih 3 vih 3 = d v dd 20 300 1500 iil 3 vil 3 = d v ss -1 D D
f edl610q359 - 01 ML610Q359 /ml610q360 21/ 30 dc characteristics (5 of 5) ( dv dd = av dd = sp v dd = 2. 0 to 3.6 v, d v ss = av ss = spv ss = 0v, ta = ? 40 to +85 c , unless otherwise specified) parameter symbol condition min. typ. max. unit measuring circuit inpu t voltage 1 ( reset _n) (test0) ( test 1_n) (nmi) (p0 0 to p0 5 ) (p1 0) (p3 0 to p37 ) (p40 to p 4 7 ) (p5 0 to p 5 7 ) (p60 to p 63) vih 1 D 0. 7 d v dd D d v dd v 5 vil 1 D 0 D 0. 3 d v dd hysteresis width ( reset _n) ( test0 ) (test1_n) (nmi) (p0 0 to p0 5 ) (p1 0) (p3 0 to p37) (p40 to p 4 7 ) (p5 0 to p 5 7 ) (p60 to p 63) ? vt D 0.0 5 d v dd D 0. 4 d v dd input pin capacitance (nmi) (p0 0 to p0 5 ) (p1 0) (p3 0 to p 37) (p40 to p 4 7 ) (p5 0 to p 5 7 ) (p 60 to p 63 ) cin f = 10khz v rms = 50mv ta = 25 c D D 10 pf D hysteresis width ? v t input signal internal signal v dd v ss v ss v ddl
f edl610q359 - 01 ML610Q359 /ml610q360 22/ 30 measuring circuits measuring circuit 1 measuring circuit 2 input pins v dv dd dv ss v ddl av ss spv ss vih vil output pins *1: input logi c circuit to determine the specified measuring conditions. *2: measured at the specified output pins. ( * 2 ) ( * 1) av dd spv dd v ddx a dv dd av dd v ddx c x c r sg c sg v ss av ss spv ss c v 10 f c l 10 f c x 0.1 f c r 1 f c sg 0.1 f c gl 1 4 pf c dl 1 4 pf cptiming c v spv dd v ddr v ddl c l 32.768khz crystal c g l c dl xt0 xt1
f edl610q359 - 01 ML610Q359 /ml610q360 23/ 30 measuring circuit 3 measuring circuit 4 measuring c ircuit 5 input pins dv dd v ddl spv ss vih vil output pins *1: input logic circuit to determine the specified measuring conditions. ( * 1) v ddx dv ss av ss av dd spv dd waveform monitoring input pins a dv dd v ddl spv ss output pins * 3 : measured at the specified in put pins. ( * 3 ) v ddx dv ss av ss av dd spv dd input pins a dv dd dv ss v ddl av ss spv ss vih vil output pins *1: input logic circuit to determine the specifie d measuring conditions. *2: measured at the specified output pins. ( * 2 ) av dd spv dd v ddx ( * 1)
f edl610q359 - 01 ML610Q359 /ml610q360 24/ 30 ac characteristics ( external interrupt ) ( dv dd = av dd = sp v dd = 2. 0 to 3.6 v, d v ss = av ss = spv ss = 0v, ta = ? 40 to +85 c , unless otherwise specified) parameter symbol condition min. typ. max. unit external interrupt disable perio d t nul interrupt: enabled ( mie = 1 ), cpu : nop operation 2.5 sysclk D 3.5 sysclk s t nul p0 0 ? p0 5 ( rising - edge interrupt ) p0 0 ? p0 5 ( falling- edge interrupt ) nmi, p0 0 ? p0 5 ( both - edge interrupt ) t nul t nul
f edl610q359 - 01 ML610Q359 /ml610q360 25/ 30 ac characteristics (synchronous serial port) ( dv dd = av dd = sp v dd = 2. 0 to 3.6 v, d v ss = av ss = spv ss = 0v, ta = ? 40 to +85 c , unless otherwise specified ) parameter symbol condition min. typ. max. unit sck input cycle (slave mode) t scyc high - speed oscillation stopped 10 D D s during high - speed oscillation 500 D D n s sck output cycle (master mode) t scyc D D sck ( * 1) D s sck input pulse width (slave m ode) t sw high - speed oscillation stopped 4 D D s during high - speed oscillation 200 D D ns sck output pulse width (master mode) t sw D sck ( * 1) 0.4 sck ( * 1) 0.5 sck ( * 1) 0.6 s sout output delay time (slave mode) t sd D D D 180 ns sout output delay time (master mode) t sd D D D 80 ns sin input setup time (slave mode) t ss D 50 D D ns sin input hold time t sh D 50 D D ns *1: clock period selected by s 0 ck3 ? 0 of the serial port 0 mode register ( s io0 mod 1 ) t sd sck0* sin0* sout0 *: indicates the t ertiary function of the corresponding port. t sd t ss t sh t sw t sw t scyc
f edl610q359 - 01 ML610Q359 /ml610q360 26/ 30 electrical chara cteristics of successive approximation type a/d converter ( d v dd = spv dd =2. 0 to 3.6 v, av dd =2.2 to 3.6 v, d v ss = av ss = spv ss = 0v, ta = ? 40 to +85 c , unless otherwise specified) parameter symbol condition min. typ. max. unit resolution n D D D 12 bit integral non - linearity error idl 2. 7 v Q v ref Q 3.6 v ? 4 D +4 lsb 2. 2 v Q v ref Q 2.7 v ? 6 D +6 differential non - linearity error d nl 2. 7 v Q v ref Q 3.6 v ? 3 D +3 2. 2 v Q v ref Q 2.7 v ? 5 D +5 zero - scale error v off D ? 6 D +6 full - scale error fse D ? 6 D +6 input impedance z i D D D 5k conversion time t conv sack=0 (hsclk= 3 m to 4.2 mhz) 2.2 Q av dd D 224 D /ch sack=1 (hsclk= 3 m to 8.4mhz) 2.5 Q av dd D 1 60 D : period of high - speed clock (hsclk) a dv dd av dd v ddl dv ss av ss analog input reference voltage 10 f - ri Q 5k ain0 to ain2 1 f 0.47 f + 1 f v ddx 0.1 f
f edl610q359 - 01 ML610Q359 /ml610q360 27/ 30 power - on/shutdown sequence ? when the power rise time is 10 ms or l ess ? when the power rise time is more than 10 ms when dv dd becomes less than 2.0v , pleas e set dv dd to 0v, and repeat a p ower - on s equence. please supply voltage to av dd simultaneous with dv dd or after dv dd rises. upon power - on upon shutdown 0v dv dd upon power -on upon shutdown 0v reset_n 10 ms (min.) 90% vil 0v dv dd
f edl610q359 - 01 ML610Q359 /ml610q360 28/ 30 package dimensions notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mou nting, contact rohm's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). the heat resistance (example) of this lsi is shown below. heat resistance ( ja) changes with the size and the number of layers of a substrate . condition example 1 eia/jesd51 example 2 pcb w/l/t = 76.2 / 114.5 / 1.6 mm w/l/t = 50 / 50 / 1.6 mm pcb layer 2layers 2layers cu thickness 40(um) 30(um) cu density 60% / 60% (two - sided) 80% / 60% (two - sided) air cooling conditions calm 0m/sec calm 0m/sec heat resistance ja 41.3[ /w] 46.1[ /w] power consumption of chip pmax at outp utpower 0.5w (3.6v) 0.472[w] (ML610Q359) 0.562[w] (ml610q360) tjmax of this lsi is 125 . tjmax is expressed with the following formulas. tjmax = tamax + ja pmax (u nit : mm)
f edl610q359 - 01 ML610Q359 /ml610q360 29/ 30 revision history document no. date page description previous edition current edition f edl610 q 3 59 -0 1 ju l 31 , 20 1 5 ? ? final edition 1
f edl610q359 - 01 ML610Q359 /ml610q360 30/ 30 notes 1) the information contained herein is subject to change without notice. 2) although lapis semiconductor is continuously working to improve product reliability and quality, semiconducto rs can break down and malfunction due to various factors. therefore, in order to prevent personal injury or fire arising from failur e, please take safety measures such as complying with the derating characteristics, implementing redundant and fire prevent ion designs, and utilizing backups and fail - safe procedures. lapis semiconductor shall have no responsibility for any damages arising out of the use of our products beyond the rating specified by lapis semiconductor. 3) examples of application circuits, circ uit constants and any other information contained herein are provided only to illustrate the standard usage and operations of the products.the peripheral conditions must be taken into account when designing circuits for mass production. 4) the technical info rmation specified herein is intended only to show the typical functions of the products and examples of application circuits for the products. no license, expressly or implied, is granted hereby under any intellectual property rights or other rights of la pis semiconductor or any third party with respect to the information contained in this document; therefore lapis semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights owned by third parties, arising out of the use of such technical information. 5) the products are intended for use in general electronic equipment (i.e. av/oa devices, communication, consumer systems, gaming/entertainment sets) as well as the applications indicated in this document. 6) the products specified in this document are not designed to be radiation tolerant. 7) for use of our products in applications requiring a high degree of reliability (as exemplified below), please contact and consult with a lapis semiconductor representative: transportation equipm ent (i.e. cars, ships, trains), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems. 8) do not use our products in applications requiring extremely hi gh reliability, such as aerospace equipment, nuclear power control systems, and submarine repeaters. 9) lapis semiconductor shall have no responsibility for any damages or injury arising from non - compliance with the recommended usage conditions and specific ations contained herein. 10) lapis semiconductor has used reasonable care to ensure the accuracy of the information contained in this document. however, lapis semiconductor does not warrant that such information is error - free and lapis semiconductor shall ha ve no responsibility for any damages arising from any inaccuracy or misprint of such information. 11) please use the products in accordance with any applicable environmental laws and regulations, such as the rohs directive. for more details, including rohs co mpatibility, please contact a rohm sales office. lapis semiconductor shall have no responsibility for any damages or losses resulting non - compliance with any applicable laws or regulations. 12) when providing our products and technologies contained in this do cument to other countries, you must abide by the procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the us export administration regulations and the foreign exchange and foreign trade act. 13) this document, in part or in whole, may not be reprinted or reproduced without prior consent of lapis semiconductor. copyright 20 15 lapis semiconductor co., ltd. 2 - 4 - 8 shinyokohama, kouhoku - ku, yokohama 222 - 8575, japan http://www.lapis - semi.com/en/

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