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1 3v, 1g-bit nand flash memory mx30lf1g18ac p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
2 contents 1. fea tures ........................................................................................................................................ 5 2. general descriptions ............................................................................................................. 6 figure 1. logic diagram ....................... .................................................................................................. 6 2-1. ordering informa tion ................................................................................................... 7 3. pin configura tions ................................................................................................................... 8 3-1. pin descriptions ............................................................................................................. 10 4. block diagram .......................................................................................................................... 12 5. schema tic cell layout and address assignment ...................................................... 13 table 1. address allocation .................................................................................................................. 13 6. device opera tions ................................................................................................................... 14 6-1. address input/command input/data input ... ..................................................................... 14 figure 2. ac waveforms for command / address / data latch timing ....................... ........................ 14 figure 3. ac waveforms for address input cycle ................................................................................ 14 figure 4. ac waveforms for command input cycle ............................................................................ 15 figure 5. ac waveforms for data input cycle ..................................................................................... 15 6-2. page read ............................................................................................................................ 16 figure 6. ac waveforms for read cycle ............................................................................................. 16 figure 7. ac waveforms for read operation (intercepted by ce#) ....................... ............................. 17 figure 8. ac waveforms for read operation (with ce# don't care) ................................................... 18 figure 9-1. ac waveforms for sequential data out cycle (after read) ....................... ....................... 18 figure 9-2. ac waveforms for sequential data out cycle (after read) - edo mode ......................... 19 figure 10. ac waveforms for random data output ............................................................................ 20 6-3. cache read sequential ....................................................................................................... 21 figure 11-1. ac waveforms for cache read sequential ..................................................................... 22 6-4. cache read random ........................................................................................................... 23 figure 11-2. ac waveforms for cache read random ....................... ................................................. 24 6-5. page program ...................................................................................................................... 25 figure 12. ac waveforms for program operation after command 80h .............................................. 25 figure 13. ac waveforms for random data in (for page program) ....................... ............................ 26 figure 14. ac waveforms for program operation with ce# don't care .............................................. 27 6-6. cache program .................................................................................................................... 28 figure 15-1. ac waveforms for cache program ................................................................................. 29 figure 15-2. ac waveforms for sequence of cache program ....................... .................................... 30 p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
3 6-7. block erase .......................................................................................................................... 31 figure 16. ac waveforms for erase operation ....................... ............................................................. 31 6-8. id read ................................................................................................................................. 32 table 2. id codes read out by id read command 90h .................................................................... 32 table 3. the defnition of byte2-byte4 of id table ............................................................................... 33 figure 17-1. ac waveforms for id read operation ............................................................................. 34 figure 17-2. ac waveforms for id read (onfi identifer) operation ....................... ........................... 34 6-9. status read .......................................................................................................................... 35 table 4. status output .......................................................................................................................... 35 figure 18. bit assignment (hex data) ....................... .......................................................................... 36 figure 19. ac waveforms for status read operation ....................... .................................................. 36 6-10. block protection status read ............................................................................................ 37 table 5. block-protection status output .............................................................................................. 37 table 6. address cycle defnition of block ....................... .................................................................... 37 figure 20. ac waveforms for block protection status read ............................................................... 38 6-11. reset ... .................................................................................................................................. 39 figure 21. ac waveforms for reset operation .................................................................................... 39 6-12. parameter page read (onfi) .............................................................................................. 40 figure 22. ac waveforms for parameter page read (onfi) operation ............................................. 40 figure 23. ac waveforms for parameter page read (onfi) random operation (for 05h-e0h) ....... 41 table 7. parameter page (onfi) ......................................................................................................... 42 6-13. unique id read (onfi) ........................................................................................................ 44 figure 24. ac waveforms for unique id read operation .................................................................... 44 figure 25. ac waveforms for unique id read operation (for 05h-e0h) ............................................. 45 6-14. feature set operation (onfi) ............................................................................................. 46 table 8-1. defnition of feature address .............................................................................................. 46 table 8-2. sub-feature parameter table of feature address - 90h (array operation mode) .............. 46 table 8-3. sub-feature parameter table of feature address - a0h (block protection operation) (note 1) ......... 46 6-14-1.set feature (onfi) .................................................................................................................. 47 figure 26. ac waveforms for set feature (onfi) operation ............................................................. 47 6-14-2.get feature (onfi) .................................................................................................................. 48 figure 27. ac waveforms for get feature (onfi) operation ....................... ....................................... 48 6-14-3.secure otp (one-time-programmable) feature ................................................................. 49 figure 28. ac waveforms for otp data read .................................................................................... 49 figure 29. ac waveforms for otp data read with random data output .......................................... 50 figure 30. ac waveforms for otp data program ............................................................................... 51 figure 31. ac waveforms for otp data program with random data input ........................................ 52 figure 32. ac waveforms for otp protection operation .................................................................... 53 6-14-4.block protection ..................................................................................................................... 54 table 9. defnition of protection bits ....................... ............................................................................. 54 figure 33. pt pin and block protection mode operation ....................... ............................................ 55 p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
4 7. p arameters ................................................................................................................................ 56 7-1. absolute maximum ra tings ........................................................................................ 56 figure 34. maximum negative overshoot waveform .......................................................................... 56 figure 35. maximum positive overshoot waveform ....................... ..................................................... 56 table 10. operating range .................................................................................................................. 57 table 11. dc characteristics ....................... ......................................................................................... 57 table 12. capacitance .......................................................................................................................... 58 table 13. ac testing conditions .......................................................................................................... 58 table 14. program and erase characteristics ...................................................................................... 58 table 15. ac characteristics ....................... ......................................................................................... 59 8. opera tion modes: logic and command tables ............................................................ 60 table 16. logic table ........................................................................................................................... 60 table 17. hex command table ........................................................................................................... 61 8-1. r/b#: t ermination for the ready/busy# pin (r/b#) ........................................................ 62 figure 36. r/b# pin timing information ............................................................................................... 63 8-2. power on/off sequence ...................................................................................................... 64 figure 37. power on/off sequence .................................................................................................... 64 8-2-1.wp# signal .............................................................................................................................. 65 figure 38-1. enable programming of wp# signal ............................................................................... 65 figure 38- 2. disable programming of wp# signal .................................................................................. 65 figure 38- 3. enable erasing of wp# signal ......................................................................................... 65 figure 38- 4. disable erasing of wp# signal ........................................................................................ 65 9. softw are algorithm .............................................................................................................. 66 9-1. invalid blocks (bad blocks) ............................................................................................... 66 figure 39. bad blocks ....................... ................................................................................................... 66 table 18. valid blocks .......................................................................................................................... 66 9-2. bad block t est flow ............................................................................................................ 67 figure 40. bad block test flow ............................................................................................................ 67 9-3. failure phenomena for read/program/erase operations ............................................... 67 table 19. failure modes ....................... ................................................................................................ 67 9-4. program ................................................................................................................................ 68 figure 41. failure modes ..................................................................................................................... 68 figure 42. program flow chart ............................................................................................................ 68 9-5. erase ... .................................................................................................................................. 68 figure 43. erase flow chart ................................................................................................................ 69 figure 44. read flow chart ....................... .......................................................................................... 69 10. package information ............................................................................................................. 70 11. revision hist ory ...................................................................................................................... 72 p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
5 3v, 1gb nand flash memory 1. features ? 1g-bit slc nand flash v 3djhvlhewh orfnvlh..ewh ? onfi 1.0 compliant ? multiplexed command/address/data ? user redundancy - 64-byte attached to each page ? fast read access - latency of array to register 25us - sequential read 20ns ? cache read support ? page program operation - page program time 300us( typ.) ? cache program support ? block erase operation - orfnhudvhwlphpvws ? single voltage operation: 99 ? low power dissipation - max. 30ma active current (read/program/erase) ? sleep mode - 50ua (max) standby current ? hardware data protection: wp# pin ? block protection 373urwhfwlrsldfwlyhkljkdwsrzhur which protects the entire chip. the pin has an lqwhuqdohdnsoogrq - temporary protection/un-protection function (enabling by pt pin) - solid protection (enabling by pt pin) ? device status indicators 5hdgxv5sl - status register ? chip enable don't care - simplify system interface ? unique id read support (onfi) ? secure otp support ? high reliability - endurance typical 100 cycles (with 4-bit ecc per (51216) byte) 'dwd5hwhwlrhduv ? w ide temperature operating range -40 c 3dfndjh 1) 48-tsop(i) (12mm x 20mm) 2) 63-ball 9mmx1 1mm 9) oosdfndjhgghlfhvduh5r6rpsoldqwdqg halogen-free. p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
6 figure 1. logic diagram ce# cle ale we# wp# re# io7 - io0 r/b# 1gb pt 2. general descriptions the mx30lf1g18ac is a 1gb slc nand flash memory device. its standard nand flash features and reliable quality of typical p/e cycles 100k (with ecc), which makes it most suitable for embedded system the product family requires 4-bit ecc per (512+16)b. the mx30lf1g18ac is typically accessed in pages of 2,112 bytes for read and program operations. mx30lf1g18ac array is organized as thousands of blocks, which is composed by 64 pages of (2,048+64) 2,112 mx30lf1g18ac enables first-byte read-access latency of 25us and se - quential read of 20ns and the latency time of next sequential page will be shorten from tr to trcbsy . the mx30lf1g18ac power consumption is 30ma during all modes of operations (read/program/erase), p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
7 2-1. ordering information part name description operating temperature: i: industrial (-40c to 85c) package type: t: 48tsop xk: 0.8mm ball pitch, 0.45mm ball size and 1.0mm height of vfbga package: rohs compliant & halogen-free generation : c mx 30 l f 1g 18a c - t i xx classification: f = slc + large block density: 1g=1g-bit voltage: l = 2.7v to 3.6v type: 30 = nand flash brand: mx option code: 18a=4-bit ecc requirement with standard feature, x8, mode a mode a: number of die number of ce# = 1, number of r/b# = 1 reserve part number density organization vcc range package temperature grade mx30lf1g18ac-ti MX30LF1G18AC-XKI 63-vfbga p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
8 3. pin configurations 48-tsop nc nc nc nc nc r/b# re# ce# nc v cc v ss nc nc cle ale we# wp# nc nc nc nc nc nc nc v ss 1 nc nc nc io7 io6 io5 io4 nc v cc 1 pt v cc v ss nc v cc 1 nc io3 io2 io1 io0 nc nc nc v ss 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 note 1. these pins might not be connected internally . however, it is recommended to connect these pins to power(or ground) as designated for onfi compatibility . p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
9 63-ball 9mmx11mm vfbga 3 wp# vcc 1 nc nc nc nc vss 1 nc nc nc nc a b c d e f g h j k l m 2 nc nc nc 8 r/b# nc nc nc nc nc vcc io7 vss 10 nc nc nc nc 9 nc nc nc nc 5 vss cle nc nc pt nc nc io3 7 we# nc nc vss 1 nc nc io5 i/o6 6 ce# nc nc nc nc nc vcc io4 4 ale re# nc nc vcc 1 i/o0 io1 io2 note 1. these pins might not be connected internally; however , it is recommended to connect these pins to power (or ground) as designated for onfi compatibility . p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
10 3-1. pin descriptions symbol pin name io7 - io0 data i/o port ce# chip enable (active low) re# read enable (active low) we# write enable (active low) cle command latch enable ale address latch enable wp# write protect (active low) pt pt (protection) pin connecting to high for entire chip protected and enabling the block protection. a weak pull-down internally. r/b# ready/busy (open drain) vss ground vcc power supply for device operation nc not connected internally p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
11 pin functions the mx30lf1g18ac device is a sequential access memory that utilizes multiplexing input of command/address/data. i/o port: io7 - io0 the io7 to io0 pins are for address/command input and data output to/from the device. chip enable: ce# the device goes into low-power standby mode when ce# goes high during a read operation and not at busy stage. the ce# goes low to enable the device to be ready for standard operation. when the ce# goes high, the device is deselected. however, when the device is at busy stage, the device will not go to standby mode when ce# pin goes high. read enable: re# the re# (read enable) allows the data to be output by a trea time after the falling edge of re#. the internal address counter is automatically increased by one at the falling edge of re#. write enable: we# when the we# goes low, the address/data/ command are latched at the rising edge of we#. command latch enable: cle the cle controls the command input. when the cle goes high, the command data is latched at the rising edge of the we#. address latch enable: ale the ale controls the address input. when the ale goes high, the address is latched at the rising edge of we#. write protect: wp# the wp# signal keeps low and then the memory will not accept the program/erase operation. it is recom - mended to keep wp# pin low during power on/off sequence. please refer to figure 37. power on/off sequence . ready/busy: r/b# the r/b# is an open-drain output pin. the r/b# outputs the ready/busy status of read/program/ erase operation of the device. when the r/b# is at low, the device is busy for read or program or erase operation. when the r/b# is at high, the read/ program/erase operation is finished. please refer to 8-1. r/b#: termination for the ready/busy# pin (r/b#) for details. pt: protection when the pt pin is high at power on, the whole chip is protected even the wp# is at high; the un- protection procedure (through bp bits setting) is necessary before any program/erase operation. when the pt pin is connected to low or floating, the function of block protection is disabled. p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
12 4. block diagram cle ale ce# we# re# r/b# io port wp# control logic high voltage circuit address counter data buffer memory array x-dec page buffer y-dec io[7:0] pt p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
13 5. schematic cell layout and address assignment mx30lf1g18ac is composed by 64 pages of (2,048+64)-byte in two nand strings structure with 32 serial connected cells in each string. each page has an additional 64 bytes for ecc and other purposes. the device has an on-chip buffer of 2,112 bytes for data load and access. each 2k-byte page has the two area, one is the main area which is 2048-bytes and the other is spare area which is 64-byte. there are four address cycles for the address allocation, please refer to the table below . addresses io7 io6 io5 io4 io3 io2 io1 io0 column address - 1st cycle a7 a6 a5 a4 a3 a2 a1 a0 column address - 2nd cycle l l l l a11 a10 a9 a8 row address - 3rd cycle a19 a18 a17 a16 a15 a14 a13 a12 row address - 4th cycle a27 a26 a25 a24 a23 a22 a21 a20 table 1. address allocation p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
14 figure 2. ac waveforms for command / address / data latch timing tcs tcls tals tch tclh tds tdh we# cle ale ce# twp / / / io[7:0] figure 3. ac waveforms for address input cycle io[7:0] cle ale ce# we# tcls twc twc twc twp twh twp twh twp twh tals tds tdh tds tdh tds tdh tds tdh twp talh 1st address cycle 2nd address cycle 3rd address cycle 4th address cycle 6. device operations 6-1. address input/command input/data input address input bus operation is for address input to select the memory address. the command input bus operation is for giving command to the memory. the data input bus is for data input to the memory device. p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
15 figure 4. ac waveforms for command input cycle tcls tcs tclh tch twp tals talh tds tdh io[7:0] cle ale ce# we# figure 5. ac waveforms for data input cycle din0 din1 din2 dinn twp twh twp twh twp tals tds tds tdh tdh tds tdh tds tdh twp tch tclh twc io[7:0] cle ale ce# we# p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
16 figure 6. ac waveforms for read cycle io[7:0] cle ale ce# we# dout dout tcls tcs twc tclh tcls tclh talh tals tds tdh tds tdh tds tdh tds tdh twb talh tr trr trea busy trc toh re# r/b# tar tds tdh 00h 30h tds tdh 1st address cycle 2nd address cycle 3rd address cycle 4th address cycle 6-2. page read the mx30lf1g18ac array is accessed in page of 2,112 bytes. external reads begins after the r/b# pin goes to ready. the read operation may also be initiated by writing the 00h command and giving the address (column and row address) and being confirmed by the 30h command, the mx30lf1g18ac begins the internal read operation and the chip enters busy state. the data can be read out in sequence after the chip is ready. refer to figure 6. ac waveforms for read cycle . if the host side uses a sequential access time (trc) of less than 30ns, the data can be latched on the next falling edge of re# as the waveform of edo mode ( figure 9-2. ac waveforms for sequential data out cycle (after read) - edo mode ). to access the data in the same page randomly, a command of 05h may be written and only column address following and then confirmed by e0h command. p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
17 figure 7. ac waveforms for read operation (intercepted by ce#) io[7:0] cle ale ce# we# trc re# r/b# 00h dout 0 dout 1 twb tr 30h busy tar trr 1st address cycle 2nd address cycle 3rd address cycle 4th address cycle dout 2 dout 3 toh tchz p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
18 figure 8. ac waveforms for read operation (with ce# don't care) io[7:0] cle ale ce# we# data output (sequential) re# r/b# 00h start addr (4 cycles) 30h busy ce# don?t care note: the ce# "don't care" feature may simplify the system interface, which allows controller to directly download the code from flash device, and the ce# transitions will not stop the read operation during the latency time. io[7:0] ce# re# dout0 dout1 dout2 doutn t rp t reh t cea t rea t oh t chz t rc t rr t rhz t rp t reh t rp t rea t oh t rhz t rea t oh t rhz t rp t rhz t oh r/b# t coh figure 9-1. ac waveforms for sequential data out cycle (after read) p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
19 figure 9-2. ac waveforms for sequential data out cycle (after read) - edo mode rhz io[7:0] ce# re# dout0 dout1 dout2 doutn t rp t reh t cea t rea t rloh t chz t rc t rr t rhz t rp t reh t rp t rea t t t rea t t rhz t rp t oh r/b# t reh rloh rloh t coh p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
20 io[7:0] cle ale ce# we# dout m dout m+1 twb tr trc re# r/b# 00h 30h busy tar trr io[7:0] cle ale ce# we# dout n dout n+1 re# r/b# 05h e0h tclr 05h trhw repeat if needed twhr trea a a 1st address cycle 2nd address cycle 3rd address cycle 4th address cycle 1st address cycle 2nd address cycle figure 10. ac waveforms for random data output p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
21 6-3. cache read sequential the cache read sequential operation is for throughput enhancement by using the internal cache buffer. it allows the consecutive pages to be read-out without giving next page address, which reduces the latency time from tr to trcbsy between pages or blocks. while the data is read out on one page, the data of next page can be read into the cache buffer. after writing the 00h command, the column and row address should be given for the start page selection, and followed by the 30h command for address confirmation. after that, the cache read operation starts after a latency time tr and following a 31h command with the latency time of trcbsy , the data can be read- out sequentially from 1 st column address (a[11:0]=000h) without giving next page address input. the 31h command is necessary to confirm the next cache read sequential operation and followed by a trcbsy latency time before next page data is necessary. the cache read sequential command is also valid for the consecutive page cross block. the random data out (05h-e0h) command set is available to change the column address of the current page data in the cache register. the user can check the chip status by the following method: - r/b# pin ("0" means the data is not ready, "1" means the user can read the data) - status register (sr[6] functions the same as r/b# pin, sr[5] indicates the internal chip operation, "0" means the chip is in internal operation and "1" means the chip is idle.) status register can be checked after the read status command (70h) is issued. command 00h should be given to return to the cache read sequential operation. to confirm the last page to be read-out during the cache read sequential operation, a 3fh command is needed to replace the 31h command prior to the last data-out. p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
22 io[7:0] cle ale ce# we# page 1 twb trcbsy trc re# r/b# 00h 31h busy tar trr tclr dout 0 page 1 dout 1 page 1 dout 2111 twb 30h busy page 2 dout 1 page 2 dout 2111 page 3 trc 3fh tar trr tclr dout 0 page 3 dout 1 page 3 dout 2111 busy io[7:0] cle ale ce# we# re# r/b# a 1st address cycle 2nd address cycle 3rd address cycle 4th address cycle twb trcbsy page 1 dout 2111 page 2 twb trcbsy trc 31h tar trr tclr dout 0 busy a tr figure 11-1. ac waveforms for cache read sequential p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
23 6-4. cache read random the main difference from the cache read sequential operation is the cache read random operation may allow the random page to be read-out with cache operation not just for the consecutive page only. after writing the 00h command, the column and row address should be given for the start page selection, and followed by the 30h command for address confirmation. the column address is ignored in the cache read random operation. and then, the cache read random operation starts after a latency time tr and following a 00h command with the selected page address and following a 31h command, the data can be read-out sequentially from the 1 st column address (a[11:0] =000h) after the latency time of trcbsy. after the previous selected page data out, a new selected page address can be given by writing the 00h-31h command set again. the cache read random command is also valid for the consecutive page cross block. the random data out (05h-e0h) command set is available to change the column address of the current page data in the cache register. the user can check the chip status by the following method: - r/b# pin ("0" means the data is not ready, "1" means the user can read the data) - status register can be checked after the read status command (70h) is issued. (sr[6] behaves the same as r/b# pin, sr[5] indicates the internal chip operation, "0" means the chip is in internal operation and "1" means the chip is idle.) command 00h should be given to return to the cache read operation. to confirm the last page to be read-out during the cache read operation, a 3fh command is needed to replace the 31h command prior to the last data-out. p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
24 io[7:0] cle ale ce# we# page n trc re# r/b# 00h trr dout 0 page n dout 1 page n dout 2111 twb tr 30h busy io[7:0] cle ale ce# we# re# r/b# 00h twb trcbsy 31h busy tar tclr page n dout 1 page n dout 2111 page m trc trr dout 0 page m dout 1 page m dout 2111 00h twb trcbsy 31h busy tar tclr page n dout 0 a a 1st address cycle 2nd address cycle 3rd address cycle 4th address cycle 4th address cycle 4th address cycle 3rd address cycle 3rd address cycle 2nd address cycle 2nd address cycle 1st address cycle 1st address cycle page n address page m address page x address figure 11-2. ac waveforms for cache read random p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
25 6-5. page program the memory is programmed by page, which is 2,112 bytes. after program load command (80h) is issued and the row and column address is given, the data will be loaded into the chip sequentially . random data input command (85h) allows multi-data load in non-sequential address. after data load is complete, program confirm command (10h) is issued to start the page program operation. the page program operation in a block should start from the low address to high address. partial program in a page is allowed up to 4 times. however, the random data input mode for programming a page is allowed and number of times is not limited. the status of the program completion can be detected by r/b# pin or status register bit sr[6]. the program result is shown in the chip status bit (sr[0]). sr[0] = 1 indicates the page program is not successful and sr[0] = 0 means the program operation is successful. during the page program progressing, only the read status register command and reset command are accepted, others are ignored. figure 12. ac waveforms for program operation after command 80h io[7:0] cle ale ce# we# re# r/b# 80 h - din 0 din n tcls tcs tclh twc tals tds tdh talh 10 h 70h status output twb tprog talh 1st address cycle 2nd address cycle 3rd address cycle 4th address cycle tds/tdh p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
26 figure 13. ac waveforms for random data in (for page program) io[7:0] cle ale ce# we# din a din a+n twc tprog re# r/b# 80h 1st address cycle io[7:0] cle ale ce# we# 10h din b+m re# r/b# 85h din b repeat if needed tadl twc tadl 70h status io0 = 0; pass io0 = 1; fail twb a a 2nd address cycle 3rd address cycle 4th address cycle 1st address cycle 2nd address cycle note: random data in is also supported in cache program. p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
27 figure 14. ac waveforms for program operation with ce# don't care io[7:0] cle ale ce# we# data input 80h start add. (4 cycles) io[7:0] cle ale ce# we# data input 10h data input a a note: the ce# "don't care" feature may simplify the system interface, which allows the controller to directly write data into flash device, and the ce# transitions will not stop the program operation during the latency time. p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
28 6-6. cache program the cache program feature enhances the program performance by using the cache buf fer of 2,112-byte. the serial data can be input to the cache buffer while the previous data stored in the buffer are programming into the memory cell. cache program command sequence is almost the same as page program command sequence. only the program confirm command (10h) is replaced by cache program command (15h). after the cache program command (15h) is issued. the user can check the status by the following methods. - r/b# pin - cache status bit (sr[6] = 0 indicates the cache is busy; sr[6] = 1 means the cache is ready). the user can issue another cache program command sequence after the cache is ready. the user can always monitor the chip state by ready/busy status bit (sr[5]). the user can issues either program confirm command (10h) or cache program command (15h) for the last page if the user monitor the chip status by issuing read status command (70h). however, if the user only monitors the r/b# pin, the user needs to issue the program confirm command (10h) for the last page. the user can check the pass/fail status through p/f status bit (sr[0]) and cache p/f status bit (sr[1]). sr[1] represents pass/fail status of the previous page. sr[1] is updated when sr[6] change from 0 to 1 or chip is ready. sr[0] shows the pass/fail status of the current page. it is updated when sr[5] change from "0" to "1" or the end of the internal programming. for more details, please refer to the related waveforms. p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
29 figure 15-1. ac waveforms for cache program io[7:0] cle ale ce# we# din din twc tcbsy tadl re# r/b# 80h busy 15h twb io[7:0] cle ale ce# we# din din tprog tadl re# r/b# 80h busy 10h twb note 70h status output a a 1st address cycle 2nd address cycle 3rd address cycle 4th address cycle 1st address cycle 2nd address cycle 3rd address cycle 4th address cycle note: it indicates the last page input & program. p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
30 figure 15-2. ac waveforms for sequence of cache program io[7:0] busy - tcbsy r/b# 80h 15h note 2 din din 80h 15h din din 80h io[7:0] r/b# 80h 15h din din 80h 10h din din 70h a a 1st address cycle 2nd address cycle 3rd address cycle 4th address cycle 1st address cycle 2nd address cycle 3rd address cycle 4th address cycle 1st address cycle 2nd address cycle 3rd address cycle 4th address cycle 1st address cycle 2nd address cycle 3rd address cycle 4th address cycle busy - tcbsy busy - tcbsy busy - tprog note: tprog = page (last) programming time + page (last-1) programming time - input cycle time of command & address - data loading time of page (last) . p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
31 figure 16. ac waveforms for erase operation io[7:0] cle ale ce# we# re# r/b# 60h 70h stauts output tcls tcs tclh twc talh tals tds tdh tdh tds tds d0h twb terase block address 1 tdh block address 2 6-7. block erase the mx30lf1g18ac supports a block erase command. this command will erase a block of 64 pages asso - ciated with the most significant address bits. the completion of the erase operation can be detected by r/b# pin or status register bit (io6). recommend to check the status register bit io0 after the erase operation completes. during the erasing process, only the read status register command and reset command can be accepted, others are ignored. p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
32 6-8. id read the device contains id codes that identify the device type and the manufacturer. the id read command sequence includes one command byte (90h), one address byte (00h). the read id command 90h may provide the manufacturer id (c2h) of one-byte and device id (f1h) of one-byte, also byte2, byte3, and byte4 id code are followed. the device support onfi parameter page read, by sending the id read (90h) command and following one byte address (20h), the four-byte data returns the value of 4fh-4eh-46h-49h for the ascii code of "o"-"n"- "f"-"i" to identify the onfi parameter page. table 2. id codes read out by id read command 90h id codes e[9 byte0-manufacturer c2h byte1: device id f1h byte2 80h byte3 95h byte4 02h p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
33 table 3. the defnition of byte2-byte4 of id table terms description io7 io6 io5 io4 io3 io2 io1 io0 byte 2 die number 1 0 0 2 0 1 cell structure slc 0 0 # of concurrently programmed page 1 0 0 2 0 1 interleaved operations between multiple die not supported 0 cache program supported 1 byte 3 page size (exclude spare) 2b 0 1 spare area size (per 512b) 1 block size (exclude spare) 128b 0 1 organization x8 0 sequential read cycle time 25ns 0 0 20ns 1 0 byte 4 ecc level requirement elw( 1 0 #plane per ce 1 0 0 2 0 1 4 1 0 plane size 1gb 0 0 0 2gb 1 0 1 reserved 0 p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
34 figure 17-1. ac waveforms for id read operation 00h c2h (note) 90h (note) (note) cle io[7:0] ale ce# we# re# tcls talh tals tar tdh trea toh tchz tds tcs (note) twhr note : see also table 2. id codes read out by id read command 90h . )lxh&:dhirpvir,'5hdg21),,ghwlh2shdwlr 20h 4fh 49h 90h 4eh 46h cle io[7:0] ale ce# we# re# tcls talh tals tar tdh trea toh tchz tds tcs twhr p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
35 6-9. status read the mx30lf1g18ac provides a status register that outputs the device status by writing a command code 70h, and then the io pins output the status at the falling edge of ce# or re# which occurs last. even though when multiple flash devices are connecting in system and the r/b#pins are common-wired, the two lines of ce# and re# may be checked for individual devices status separately . the status read command 70h will keep the device at the status read mode unless next valid command is issued. the resulting information is outlined in table 4 as below. pin status related mode value sr[0] chip status page program, cache program (page n), block erase 0: passed 1: failed sr[1] cache program result cache program (page n-1) 0: passed 1: failed sr[2-4] not used sr[5] ready / busy (for p/e/r controller) cache program/cache read operation, other page program/block erase/read are same as io6 (note 1) 0: busy 1: ready sr[6] ready / busy page program, block erase, cache program, read, cache read (note 2) 0: busy 1: ready sr[7] write protect page program, block erase, cache program, read 0: protected 1: unprotected notes: 1. during the actual programming operation, the sr[5] is "0" value; however, when the internal operation is completed during the cache mode, the sr[5] returns to "1". 2. the sr[6] returns to "1" when the internal cache is available to receive new data. the sr[6] value is consistent with the r/b#. table 4. status output p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
36 figure 19. ac waveforms for status read operation cle 70h status output re# ce# we# io[7:0] tcls twhr twp tclr tds tdh tir trea tchz toh tcs tclh the following is an example of a hex data bit assignment: figure 18. bit assignment (hex data) 0 1 1 1 0 0 0 0 sr7 6 5 4 3 2 1 sr0 status read: 70h p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
37 6-10. block protection status read the block protection status read command (7ah) may check the protect/un-protect status of blocks. the status output is shown in table 5. block protection status output and the address cycle is referred to table 6. address cycle definition of block . table 5. block-protection status output block-protection status io[7:3] io2(pt#) io1(sp#) io0(sp) block is protected, and device is solid-protected x 0 0 1 block is protected, and device is not solid-protected x 0 1 0 block is un-protected, and device is solid-protected x 1 0 1 block is un-protected, and device is not solid-protected x 1 1 0 note: sp stands for solid-protected. once the sp bit sets as 1, the rest of the protection bits (bpx bits, invert bit, complementary bit) cannot be changed during the current power cycle. deohgghvv&foh'hlwlrriorfn address cycle io7 io6 io5 io4 io3 io2 io1 io0 block address 1 a19 a18 l l l l l l block address 2 a27 a26 a25 a24 a23 a22 a21 a20 p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
38 io[7:0] cle ale ce# we# twc re# r/b# 7ah block address 1 block address 2 status output wp# twhr figure 20. ac waveforms for block protection status read p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
39 6-11. reset the reset command ffh resets the read/program/erase operation and clear the status register to be e0h (when wp# is high). the reset command during the program/erase operation will result in the content of the selected locations(perform programming/erasing) might be partially programmed/erased. if the flash memory has already been set to reset stage with reset command, the additional new reset command is invalid. figure 21. ac waveforms for reset operation io[7:0] cle ale we# trst re# r/b# ffh twb ce# p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
40 6-12. parameter page read (onfi) the nand flash device support onfi parameter page read and the parameter can be read out by sending the command of ech and giving the address 00h. the nand device information may refer to the table of parameter page(onfi), there are three copies of 256-byte data and additional redundant parameter pages. once sending the ech command, the nand device will remain in the parameter page read mode until next valid command is sent. the random data out command set (05h-e0h) can be used to change the parameter location for the specific parameter data random read out. the status read command (70h) can be used to check the completion with a following read command (00h) to enable the data out. figure 22. ac waveforms for parameter page read (onfi) operation io[7:0] cle ale ce# we# parameter 0 twb tr trc re# r/b# ech 00h busy tar trr tclr dout 0 parameter 0 dout 1 parameter 0 dout 255 parameter 1 dout 0 p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
41 figure 23. ac waveforms for parameter page read (onfi) random operation (for 05h-e0h) io[7:0] cle ale ce# we# parameter 0 twb tr trc re# r/b# ech 00h busy tar trr tclr dout 0 parameter 0 dout 1 05h e0h repeat if needed twhr trea parameter m dout n parameter m dout n+1 1st address cycle 2nd address cycle p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
42 table 7. parameter page (onfi) revision information and features block byte# description data 0-3 parameter page signature 4fh, 4eh, 46h, 49h 4-5 revision number 02h, 00h 6-7 features supported 10h, 00h 8-9 optional commands supported 37h, 00h 10-31 reserved 00h manufacturer information block byte# description data 32-43 device manufacturer (12 ascii characters) 4dh,41h,43h,52h,4fh,4eh,49h,58h, 20h,20h,20h,20h 44-63 device model (20 ascii characters) mx30lf1g18ac 4dh,58h,33h,30h,4ch,46h,31h,47h, 31h,38h,41h,43h,20h,20h,20h,20h, 20h,20h,20h,20h, 64 jedec manufacturer id c2h 65-66 date code 00h, 00h 67-79 reserved 00h memory organization block byte# description data 80-83 number of data bytes per page 2048- byte 00h,08h,00h,00h 84-85 number of spare bytes per page 64-byte 40h,00h 86-89 number of data bytes per partial page 512-byte 00h,02h,00h,00h 90-91 number of spare bytes per partial page 16-byte 10h,00h 92-95 number of pages per block 40h,00h,00h,00h 96-99 number of blocks per logical unit 00h,04h,00h,00h 100 number of logical units (luns) 01h 101 number of address cycles 22h 102 number of bits per cell 01h 103-104 bad blocks maximum per lun 14h,00h 105-106 block endurance 01h, 05h 107 guarantee valid blocks at beginning of target 01h 108-109 block endurance for guaranteed valid blocks 01h, 03h 110 number of programs per page 04h 111 partrial programming attributes 00h 112 number of bits ecc correctability 04h 113 number of interleaved address bits 00h 114 interleaved operation attributes 00h 115-127 reserved 00h p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
43 electrical parameters block byte# description data 128 i/o pin capacitance 0ah 129-130 timing mode support 3fh,00h 131-132 program cache timing mode support 3fh,00h 133-134 tprog maximum page program time (us) 600us 58h,02h 135-136 tbers(terase) maximum block erase time (us) 3,500us ach,0dh 137-138 tr maximum page read time (us) 25us 19h,00h 139-140 tccs minimum change column setup time (ns) 60ns 3ch,00h 141-163 reserved 00h vendor blocks byte# description data 164-165 vendor specific revision number 00h 166-253 vendor specific 00h 254-255 integrity crc set at test (note) redundant parameter pages byte# description data 256-511 value of bytes 0-255 512-767 value of bytes 0-255 768+ additional redundant parameter pages note: the integrity crc (cycling redundancy check) field is used to verify that the contents of the parameters page were transferred correctly to the host. please refer to onfi 1.0 specifications for details. the crc shall be calculated using the following 16-bit generator polynomial: g(x) = x 16 + x 15 +x 2 + 1 p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
44 6-13. unique id read (onfi) the unique id is 32-byte and with 16 copies for back-up purpose. after writing the unique id read command (edh) and following the one address byte (00h), the host may read out the unique id data. the host need to xor the 1 st 16-byte unique data and the 2 nd 16-byte complement data to get the result, if the result is ff h, the unique id data is correct; otherwise, host need to repeat the xor with the next copy of unique id data. once sending the edh command, the nand device will remain in the unique id read mode until next valid command is sent. to change the data output location, it is recommended to use the random data out command set (05h-e0h). the status read command (70h) can be used to check the completion. t o continue the read operation, a following read command (00h) to re-enable the data out is necessary. figure 24. ac waveforms for unique id read operation io[7:0] cle ale ce# we# unique id 0 twb tr trc re# r/b# edh 00h busy tar trr tclr dout 0 unique id 0 dout 1 unique id 0 dout 31 unique id 1 dout 0 p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
45 figure 25. ac waveforms for unique id read operation (for 05h-e0h) io[7:0] cle ale ce# we# twb tr trc re# r/b# edh 00h busy tar trr tclr 05h 1st address cycle 2nd address cycle e0h repeat if needed twhr trea dout n dout n+1 unique id 0 dout 0 unique id 0 dout 1 unique id m unique id m p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
46 6-14. feature set operation (onfi) the feature set operation is to change the default power-on feature sets by using the set feature and get feature command and writing the specific parameter data (p1-p4) on the specific feature addresses. the nand device may remain the current feature set until next power cycle since the feature set data is volatile. however, the reset command (ffh) can not reset the current feature set. table 8-1. defnition of feature address feature address description 00h-8fh, 91h-ffh, reserved 90h array operation mode a0h block protection operation table 8-2. sub-feature parameter table of feature address - 90h (array operation mode) sub feature parameter definition io7 io6 io5 io4 io3 io2 io1 io0 values notes p1 array operation mode normal reserved (0) 0 0 0000 0000b 1 otp operation reserved (0) 0 0 1 0000 0001b otp protection reserved (0) 0 1 1 0000 0011b p2 reserved (0) 0000 0000b p3 reserved (0) 0000 0000b p4 reserved (0) 0000 0000b note 1. the value is clear to 00h at power cycle. table 8-3. sub-feature parameter table of feature address - a0h (block protection operation) (note 1) sub feature parameter definition io7 io6 io5 io4 io3 io2 io1 io0 values notes p1 block protection operation default mode 0 0 1 1 1 0 0 0 38h note 2 protection bit setting 0 0 bp2 bp1 bp0 invert complementary sp note 3 note 4 p2 reserved (0) p3 reserved (0) p4 reserved (0) notes: 1. if the pt pin is not connected to high, this sub-feature address a0h command is not valid. 2. the value is returned to 38h at power cycle. 3. the value is defined in the table 9. definition of protection bits . 4. the sp stands for solid-protection. once the sp bit sets as 1, the rest of protection bits cannot be changed during the current power cycle. p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
47 6-14-1. set feature (onfi) the set feature command is to change the power-on default feature set. after sending the set feature command (efh) and following specific feature and then input the p1-p4 parameter data to change the default power-on feature set. once sending the efh command, the nand device will remain in the set feature mode until next valid command is sent. the status read command (70h) may check the completion of the set feature. figure 26. ac waveforms for set feature (onfi) operation io[7:0] cle ale ce# we# din din twc tfeat tadl re# r/b# efh feature address busy twb din din p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
48 figure 27. ac waveforms for get feature (onfi) operation 6-14-2. get feature (onfi) the get feature command is to read sub-feature parameter. after sending the get feature command (eeh) and following specific feature, the host may read out the p1-p4 sub- feature parameter data. once sending the eeh command, the nand device will remain in the get feature mode until next valid command is sent. the status read command (70h) can be used to check the completion. t o continue the read operation, a following read command (00h) to re-enable the data out is necessary. please refer to the following waveform of get feature operation for details. io[7:0] cle ale ce# we# feature twb tfeat trc re# r/b# eeh feature address busy tar trr tclr dout 0 feature dout 1 feature dout 2 feature dout 3 p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
49 6-14-3. secure otp (one-time-programmable) feature there is an otp area which has thirty full pages (30 x 2,112-byte) guarantee to be good for system device serial number storage or other fixed code storage. the otp area is a non-erasable and one-time- programmable area, which is default to 1 and allows whole page or partial page program to be 0, once the otp protection mode is set, the otp area becomes read-only and cannot be programmed again. the otp operation is operated by the set feature/ get feature operation to access the otp operation mode and otp protection mode. to check the nand device is ready or busy in the otp operation mode, either checking the r/b# or writing the status read command (70h) may collect the status. to exit the otp operation or protect mode, it can be done by writing 00h to p1 at feature address 90h. otp read/program operation to enter the otp operation mode, it is by using the set feature command (efh) and followed by the feature address (90h) and then input the 01h to p1 and 00h to p2-p4 of sub-feature parameter data( please refer to table 8-2. sub-feature parameter table of feature address - 90h (array operation mode) and table 8-3. sub-feature parameter table of feature address - a0h (block protection operation) (note 1) ). after enter the otp operation mode, the normal read command (00h-30h) or page program( 80h-10h) command can be used to read the otp area or program it. the address of otp is located on the 02h-1fh of page address. besides the normal read command, the random data output command (05h-e0h) can be used for read otp data. however, the cache read command is not supported in the otp area. besides the normal page program command, the random data input command (85h) allows multi-data load in non-sequential address. after data load is completed, a program confirm command (10h) is issued to start the page program operation. the number of partial-page otp program is 8 per each otp page. figure 28. ac waveforms for otp data read io[7:0] cle ale ce# we# trc re# r/b# 00h otp page dout 0 dout 1 dout n 00h twb tr 30h busy tar trr tclr 1st address cycle 2nd address cycle p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
50 figure 29. ac waveforms for otp data read with random data output io[7:0] cle ale ce# we# dout m dout m+1 twb tr trc re# r/b# 00h 30h otp page 00h busy tar trr io[7:0] cle ale ce# we# dout n dout n+1 re# r/b# 05h e0h tclr 05h trhw repeat if needed twhr trea a a 1st address cycle 2nd address cycle 1st address cycle 2nd address cycle p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
51 figure 30. ac waveforms for otp data program io[7:0] cle ale ce# we# din din tprog tadl re# r/b# 80h busy 10h twb 70h status output 1st address cycle 2nd address cycle otp page 00h p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
52 figure 31. ac waveforms for otp data program with random data input io[7:0] cle ale ce# we# din din twc tadl re# r/b# 80h io[7:0] cle ale ce# we# din din tprog tadl re# r/b# 85h busy 10h twb 70h status output a 1st address cycle 2nd address cycle 1st address cycle 2nd address cycle otp page 00h a p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
53 otp protection operation to prevent the further otp data to be changed, the otp protection mode operation is necessary. to enter the otp protection mode, it can be done by using the set feature command (efh) and followed by the feature address (90h) and then input the 03h to p1 and 00h to p2-p4 of sub-feature parameter data (please refer to the table 8-2. sub-feature parameter table of feature address - 90h (array operation mode) and table 8-3. sub-feature parameter table of feature address - a0h (block protection operation) (note 1) ). and then the normal page program command (80h-10h) with the address 00h before the 10h command is required. the otp protection mode is operated by the whole otp area instead of individual otp page. once the otp protection mode is set, the otp area cannot be programmed or unprotected again. figure 32. ac waveforms for otp protection operation io[7:0] cle ale ce# we# re# r/b# 80 h - - 00h 00h tcls tcs tclh twc tals tds tdh talh 10 h 70h status output twb tprog note talh 2nd address cycle 1st address cycle dummy data input note: this address cycle can be any value since the otp protection protects the entire otp area instead of individual otp page. p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
54 6-14-4. block protection the block protect operation can protect the whole chip or selected blocks from erasing or programming. through the pt pin at power-on stage, it decides the block protection operation is enabled or disabled. at power-on, if the pt pin is connected to high, the block protection operation is enabled, all the blocks are default to be protected from programming/erasing even the wp# is disabled. if the pt pin is low, block protection operation is disabled. please refer to the figure 33. pt pin and block protection mode operation. when program or erase attempt at a protected block is happened, the r/b# keeps low for the time of tpbsy , and the status read command (70h) may get the 60h result. there are temporary protection/un-protection and solid protection features as below description. temporary protection/un-protection at power-on, if the pt pin is connected to high, all the blocks are default to be protected for the bpx protection bits are all 1. the set feature command with feature address a0h followed by the destined protection bits data is necessary to un-protect those selected blocks before those selected blocks to be updated. the wp# pin needs to connect to high before writing the set feature command for the block protection operation. after the selected blocks are un-protected, those un-protected blocks can be protected again by block protection procedure if required. solid protection the solid-protection feature can be set by writing the set feature command with address a0h and the sp solid- protection bit as 1, after that, the selected block is solid-protected and cannot be up-protected until next power cycle. 7deoh'hqlwlrqri3urwhfwlrqlwv bp2 bp1 bp0 invert complementary protection area 0 0 0 x x all unlocked 0 0 1 0 0 upper 1/64 locked 0 1 0 0 0 upper 1/32 locked 0 1 1 0 0 upper 1/16 locked 1 0 0 0 0 upper 1/8 locked 1 0 1 0 0 upper 1/4 locked 1 1 0 0 0 upper 1/2 locked 1 1 1 x x all locked (default) 0 0 1 1 0 lower 1/64 locked 0 1 0 1 0 lower 1/32 locked 0 1 1 1 0 lower 1/16 locked 1 0 0 1 0 lower 1/8 locked 1 0 1 1 0 lower 1/4 locked 1 1 0 1 0 lower 1/2 locked 0 0 1 0 1 lower 63/64 locked 0 1 0 0 1 lower 31/32 locked 0 1 1 0 1 lower 15/16 locked 1 0 0 0 1 lower 7/8 locked 1 0 1 0 1 lower 3/4 locked 1 1 0 0 1 block 0 0 0 1 1 1 upper 63/64 locked 0 1 0 1 1 upper 31/32 locked 0 1 1 1 1 upper 15/16 locked 1 0 0 1 1 upper 7/8 locked 1 0 1 1 1 upper 3/4 locked 1 1 0 1 1 block0 p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
55 power on wp# protection mode 1. wp# pin = low to protect whole chip 2. block protection mode disable block protection mode (pt) pt pin = low pt pin = high 1. blcok protection mode enable with bpx bit = 1 2. whole blocks are protected after power on temporary protection/ un-proteciton (by cmd) 1. set feature command (efh) sets bpx bit, invert bit and complementary bit value solid protection mode 1. set feature command with sp bit = 1 fixes current block protecion/un-protection status 2. only next power on cycle can disable solid protection mode sp bit = 1 block protection area (by cmd) figure 33. pt pin and block protection mode operation p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
56 figure 35. maximum positive overshoot waveform vss vss-2.0v 20ns 20ns 20ns vcc + 2.0v vcc 20ns 20ns 20ns figure 34. maximum negative overshoot waveform temperature under bias -50 q c to +125 c storage temperature -65 q c to +150 c all input voltages with respect to ground (note 2) -0.6v to 4.6v vcc supply voltage with respect to ground (note 2) -0.6v to 4.6v esd protection >2000v notes: 1. the reliability of devie may be imaired by exosing to extreme maximum rating onditions for long range of time. 2. permanent damage may be aused by the stresses higher than the absolute maximum ratings listed. 3. during voltage transitions, all ins may overshoot vss to -2.0v and v to 2.0v for eriods u to 20ns, as shon in figure 34. maximum negative overshoot waveform and figure 35. maximum positive overshoot waveform . 7. parameters 7-1. absolute maximum ratings p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
57 temperature vcc tolerance -40 c 9 2.7 - 3.6v table 11. dc characteristics table 10. operating range symbol parameter test conditions min. typical max. unit notes vil input low level -0.3 0.2vcc v vih input high level 0.8vcc 9 v vol output low voltage 2/ p9 vcc min. 0.2 v voh output high voltage 2 9 vcc min. vcc-0.2 v 6 vcc standby current (cmos) ( 99 3 9 10 50 ua 6 vcc standby current (ttl) ( 90lq 3 9 1 ma icc0 power on current (including por current) 50 ma icc1 vcc active current (sequential read) w50lq( 9/ 287 p 15 30 ma icc2 vcc active current (program) 15 30 ma icc3 vcc active current (erase) 15 30 ma ili qswohdndjhfuuhqw 91 wr90d ua ilo 2wswohdndjhfuuhqw 9287 wr9 max. ua ilo 5 2wswfuuhqwri5slq 92/ 9 8 10 ma p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
58 table 14. program and erase characteristics table 13. ac testing conditions testing conditions value unit input pulse level 0 to vcc v output load capacitance 1ttl+cl(50) pf input rise and fall time 5 ns input timing measurement reference levels vcc/2 v output timing measurement reference levels vcc/2 v symbol parameter min. typ. 0d[ unit note tprog page programming time 300 600 us tcbsy (program) dummy busy time for cache program 5 600 us trcbsy (read) dummy busy time for cache read 3.5 25 us tdbsy the busy time for two-plane program/erase operation 0.5 1 us tfeat the busy time for set feature/ get feature 1 us tobsy the busy time for otp program at otp protection mode 30 us tpbsy the busy time for program/erase at protected blocks 3 us nop number of partial program cycles in same page 4 cycles terase (block) block erase time 1 3.5 ms ta = +25 c, f = 1 mhz symbol parameter typ. 0d[ units conditions cin input capacitance 10 pf vin = 0 v cout output capacitance 10 pf vout = 0 v table 12. capacitance p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
59 symbol parameter min. typical max. unit note tcls cle setup time 10 ns 1 tclh cle hold time 5 ns 1 tcs ce# setup time 15 ns 1 tch ce# hold time 5 ns 1 twp write pulse width 10 ns 1 tals ale setup time 10 ns 1 talh ale hold time 5 ns 1 tds data setup time 7 ns 1 tdh data hold time 5 ns 1 twc write cycle time 20 ns twh we# high hold time 7 ns 1 tadl last address latched to data loading time during program operations 70 ns 1 tww wp# transition to we# high 100 ns 1 trr ready to re# falling edge 20 ns 1 trp read pulse width 10 ns 1 trc read cycle time 20 ns 1 trea re# access time (serial data access) 16 ns 1 tcea ce# access time 25 ns 1 trloh re#-low to data hold time (edo) 5 ns toh data output hold time 15 ns 1 trhz re#-high to output-high impedance 60 ns 1 tchz ce#-high to output-high impedance 50 ns 1 tcoh ce# high to output hold time 15 ns treh re# high hold time 7 ns 1 tir output high impedance to re# falling edge 0 ns 1 trhw re# high to we# low 60 ns 1 twhr we# high to re# low 60 ns 1 tr the data transfering from array to buffer 25 us 1 twb we# high to busy 100 ns 1 tclr cle low to re# low 10 ns 1 tar ale low to re# low 10 ns 1 trst device reset time (idle/ read/ program/ erase) 5/5/10/500 us 1 note 1 . onfi mode 5 compliant table 15. ac characteristics p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
60 8. operation modes: logic and command tables address input, command input and data input/output are managed by the cle, ale, ce#, we#, re# and wp# signals, as shown in table 16. logic table below. program, erase, read and reset are four major operations modes controlled by command sets, please refer to table 17. hex command table . notes: 1. h = vih; l = vil; x = vih or vil 2. wp# should be biased to cmos high or cmos low for stand-by. table 16. logic table mode ce# re# we# cle ale wp# address input (read mode) l h l h x address input (write mode) l h l h h command input (read mode) l h h l x command input (write mode) l h h l h data input l h l l h data output l h l l x during read (busy) x h h l l x during programming (busy) x x x x x h during erasing (busy) x x x x x h program/erase inhibit x x x x x l stand-by h x x x x 0v/vcc p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
61 caution: none of the undefined command inputs can be accepted except for the command set in the above table. first cycle second cycle acceptable while busy read mode 00h 30h random data input 85h - random data output 05h e0h cache read random 00h 31h cache read sequential 31h - cache read end 3fh - id read 90h - parameter page read (onfi) ech - unique id read (onfi) edh - set feature (onfi) efh - get feature (onfi) eeh - reset ffh - v page program 80h 10h cache program 80h 15h block erase 60h d0h status read 70h - v block protection status read 7ah - table 17. hex command table p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
62 8-1. r/b#: termination for the ready/busy# pin (r/b#) the r/b# is an open-drain output pin and a pull-up resistor is necessary to add on the r/b# pin. the r/b# outputs the ready/busy status of read/program/ erase operation of the device. when the r/b# is at low , the device is busy for read or program or erase operation. when the r/b# is at high, the read/program/erase operation is finished. rp value guidence the rise time of the r/b# signal depends on the combination of rp and capacitive loading of the r/b# circuit. it is approximately two times constants (tc) between the 10% and 90% points on the r/b# waveform. t c = r c where r = r p (resistance of pull-up resistor), and c = c l (total capacitive load) the fall time of the r/b# signal majorly depends on the output impedance of the r/b# signal and the total load capacitance. vcc (max.) - vol (max.) rp (min.) = i ol + il notes: 1. considering of the variation of device-by-device, the above data is for reference to decide the resistor value. 2. rp maximum value depends on the maximum permissible limit of tr . 3. il is the total sum of the input currents of all devices tied to the r/b pin. p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
63 figure 36. r/b# pin timing information @ vcc = 3.3 v, ta = 25c, c l =100pf rp (ohm) ibusy 1.6 0.55 0.41 2k 4k 6k 8k 0.4ma v ss v cc r/b# rp c l device v cc 0.83 @ vcc = 3.3 v, ta = 25c, c l =100pf rp (ohm) tc 800 600 200 400 2k 4k 6k 8k ns008 400ns 1ma ready state v oh tr tf v ol bu sy state v ol ~90% ~90% ~10% ~10% v cc v oh p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
64 8-2. power on/off sequence after the chip reaches the power on level (vth = vcc min.), the internal power on reset sequence will be triggered. during the internal power on reset period, no any external command is accepted. there are two ways to identify the termination of the internal power on reset sequence. please refer to figure 37. power on/off sequence . ? r/b# pin ? wait 1 ms during the power on and power off sequence, it is recommended to keep the wp# = low for internal data protection. figure 37. power on/off sequence vcc (min.) vcc wp# we# r /b# 1 ms (max.) 10us (max.) ce# p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
65 8-2-1. wp# signal wp# going low can cause program and erase operations automatically reset. the enabling & disabling of the both operations are as below: tww we# io[7:0] 80h 10h wp# tww we# io[7:0] 80h 10h wp# tww we# io[7:0] 60h d0h wp# tww we# io[7:0] 60h d0h wp# figure 38-1. enable programming of wp# signal figure 38- 2. disable programming of wp# signal figure 38- 3. enable erasing of wp# signal figure 38- 4. disable erasing of wp# signal p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
66 9. software algorithm 9-1. invalid blocks (bad blocks) the bad blocks are included in the device while it gets shipped. during the time of using the device, the additional bad blocks might be increasing; therefore, it is recommended to check the bad block marks and avoid using the bad blocks. furthermore, please read out the bad block information before any erase operation since it may be cleared by any erase operation. figure 39. bad blocks while the device is shipped, the value of all data bytes of the good blocks are ffh. the 1 st bytes of the 1 st and 2 nd page in the spare area for bad block will be 00h. the erase operation at the bad blocks is not recommended. after the device is installed in the system, the bad block checking is recommended. figure 40. bad block test flow shows the brief test flow by the system software managing the bad blocks while the bad blocks were found. when a block gets damaged, it should not be used any more. due to the blocks are isolated from bit-line by the selected gate, the performance of good blocks will not be impacted by bad ones. bad block bad block density min. typ. 0d[ unit remark valid (good) block number 1gb 1004 1024 block block 0 is guaranteed to be good at least 1k p/e cycle (with ecc). table 18. valid blocks p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
67 9-2. bad block test flow although the initial bad blocks are marked by the flash vendor, they could be inadvertently erased and destroyed by a user that does not pay attention to them. to prevent this from occurring, it is necessary to always know where any bad blocks are located. continually checking for bad block markers during normal use would be very time consuming, so it is highly recommended to initially locate all bad blocks and build a bad block table and reference it during normal nand flash use. this will prevent having the initial bad block markers erased by an unexpected program or erase operation. failure to keep track of bad blocks can be fatal for the application. for example, if boot code is programmed into a bad block, a boot up failure may occur. figure 40. bad block test flow shows the recommended flow for creating a bad block table. figure 40. bad block test flow start block no. = 0 create (or update) bad block table read 00h check block no. = 1023 end block no. = block no. + 1 no yes yes no (note1) 9-3. failure phenomena for read/program/erase operations the device may fail during a read, program or erase operation. the following possible failure modes should be considered when implementing a highly reliable system: table 19. failure modes failure mode detection and countermeasure sequence erase failure status read after erase block replacement programming failure status read after program block replacement read failure read failure ecc note 1: read 00h he is at the 1st byte of the 1st and 2nd ages of the blo sare area. p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
68 9-4. program it is feasible to reprogram the data into another page (page b) when an error occurred in page a by loading from an external buffer. then create a bad block table or by using another appropriate scheme to prevent further system accesses to page a. figure 41. failure modes 9-5. erase to prevent future accesses to this bad block, it is feasible to create a table within the system or by using another appropriate scheme when an error occurs in an erase operation. block another good block program error occurs in page a buffer memory page b figure 42. program flow chart start sr[6] = 1 ? sr[0] = 0 ? no command 80h set address write data write 10h read status register (or r/b# = 1 ?) program error yes no yes * program command flow program completed p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
69 figure 43. erase flow chart figure 44. read flow chart start verify ecc no command 00h set address read data out ecc generation reclaim the error page read completed yes command 30h sr[6] = 1 ? read status register (or r/b# = 1 ?) no yes ecc handling by the host controller start sr[6] = 1 ? sr[0] = 0 ? no * * command 60h set block address command d0h read status register (or r/b# = 1 ?) erase error yes no the failed blocks will be identified and given errors in status register bits for attempts on erasing them. erase completed yes p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
70 10. package information p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
71 title: package outline for 63-vfbga (9x11x1.0mm, ball-pitch: 0.8mm, ball-diameter: 0.45mm) p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
72 11. revision history rev. no. descriptions page date 0.01 1. corrected the value of byte#6-9 of onfi parameter page p42 sep/04/2014 2. revised the io3 of feature address 90h from "x" to "reserved (0)" p46 3. revised the typical spec of tcbsy from 3us to 5us and trcbsy p57 from 2us to 3.5us 0.02 1. revised title o f "advanced information" to "preliminary" all dec/30/2014 2. corrected tals timing waveform as ale high till we# high p25,53 3. added figure 33 pt pin and block protection mode operation p55 4. icc1/icc2 (typical) are improved from 20m a to 15ma p57 5. revised the b ad block mark from non-ffh to 00h, p66,67 also revised the page of bad block mark from 1st or 2nd page to 1st and 2nd page 1.0 1. removed "preliminary" title all feb/02/2015 1.1 1. added negative overshoot/positive overshoot waveforms p56 jun/30/2015 1.2 1. added the trst=5us for the device reset time from idle p59 ma y/27/2016 2. modification o f the power-on/off sequence: supplement the p64 ce# signal, supplement the we# single waveform with we#=0 without toggle during the power-on period. 3. modified word ing of "at least 1k p/e(with ecc) "on block#0 p66 p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac
73 m acronix i nternational c o., l td. http://www.macronix.com macronix international co., ltd. reserves the right to change product and specifcations without notice. ecept or custoied products which have een epress identiied in the appicae agreeent, macronis products are designed, deveoped, andor anuactured or ordinar usiness, industria, persona, andor househod appica - wlrqvrqodqgqrwiruvhlqdqdssolfdwlrqvlfpdgluhfworulqgluhfwofdvhghdwshuvrqdolqmuruvhhuh surshuwgdpdjhvqwhhhqw0dfurqlsurgfwvduhvhglqfrqwudglfwhgwrwhluwdujhwvdjhderhwhehuvdoo wdnhdqdqgdoodfwlrqvwrhqvuhvdlg0dfurqlvsurgfwtdolilhgirulwvdfwdovhlqdffrugdqfhlwwhdssolfdeoh laws and regulations; and macronix as well as its suppliers and/or distributors shall be released from any and all liabil - ity arisen therefrom. rsuljw0dfurqlqwhuqdwlrqdor/wgoouljwvuhvhuhglqfoglqjwhwudghpdunvdqgwudghqdph whuhrivfdv0dfurql0;0;/rjr0;/rjrqwhjudwhg6rowlrqv3urlghu 1lw1elw1llw0dfurql1lw h/lwh)odveulg190eulg)odv;wud5203lqhv./rjr(62126.60.lqjwhf0;6020dfurql ((0dfurql035lf glr 5lfrrn5lf79dqg)lw07hqdphvdqgeudqgvriwlugsduwuhihuuhgwhuhwrli any) are for identification purposes only. )ruwhfrqwdfwdqgrughulqirupdwlrqsohdvhlvlw0dfurqlvhevlwhdw wwspdfurqlfrp p/n: pm2133 rev. 1.2, may 27, 2016 mx30lf1g18ac

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