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touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c16a-3/BS86D20A-3 revision: v1.40 date: de ? e ?? e ? 0 ?? ? 01 ? de ? e ?? e ? 0 ?? ? 01 ?
rev. 1.40 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 3 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver table of contents eates cpu featu ? es ......................................................................................................................... ? pe ? iphe ? al featu ? es ................................................................................................................. 7 gene?al des??iption ........................................................................................ 8 sele?tion ta?le ................................................................................................. 8 blo?k diag?a? .................................................................................................. 9 pin assign?ent ........... ..................................................................................... 9 pin des??iption s ............................................................................................ 1? a?solute maxi?u? ratings .......................................................................... ?0 d.c. cha?a?te?isti?s ....................................................................................... ?1 a.c. cha?a?te?isti?s ....................................................................................... ?3 senso? os?illato? ele?t?i?al cha?a?te?isti?s ... ............................................ ?4 a/d conve?te? ele?t?i?al cha?a?te?isti?s ........... .......................................... ?? lcd ele?t?i?al cha?a?te?isti?s ..................................................................... ?7 powe?-on reset cha?a?te?isti?s ........... ........................................................ ?7 syste? a??hite?tu?e ...................................................................................... ?8 clo ? king and pipelining ......................................................................................................... ? 8 p ? og ? a ? counte ? ................................................................................................................... ? 9 sta ? k ..................................................................................................................................... 30 a ? ith ? eti ? and logi ? unit C alu ........................................................................................... 30 flash p?og?a? me?o?y ................................................................................. 31 st ? u ? tu ? e ................................................................................................................................ 31 spe ? ial ve ? to ? s ..................................................................................................................... 31 look-up ta ? le ............. ........................................................................................................... 3 ? ta ? le p ? og ? a ? exa ? ple ........................................................................................................ 3 ? in ci ?? uit p ? og ? a ?? ing C icp ............................................................................................... 33 on-chip de ? ug suppo ? t C ocds ......................................................................................... 34 ram data me?o?y ......................................................................................... 3? st ? u ? tu ? e ................................................................................................................................ 3 ? data me ? o ? y add ? essing ...................................................................................................... 3 ? gene ? al pu ? pose data me ? o ? y ............................................................................................ 3 ? spe ? ial pu ? pose data me ? o ? y ............................................................................................. 3 ? spe?ial fun?tion registe? des??iption ........................................................ 40 indi ? e ? t add ? essing registe ? s C iar0 ? iar1 ? iar ? ............................................................... 40 me ? o ? y pointe ? s C mp0 ? mp1l/mp1h ? mp ? l/mp ? h ........................................................... 40 a ?? u ? ulato ? C acc ............................................................................................................... 4 ? p ? og ? a ? counte ? low registe ? C pcl .................................................................................. 4 ? look-up ta ? le registe ? s C tblp ? tbhp ? tblh ..................................................................... 4 ? status registe ? C status .................................................................................................... 4 ?
rev. 1.40 ? de?e??e? 0?? ?01? rev. 1.40 3 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver eeprom data memory ........... ....................................................................... 44 eeprom data me ? o ? y st ? u ? tu ? e ........................................................................................ 44 eeprom registe ? s ............ .................................................................................................. 44 reading data f ? o ? the eeprom ........................................................................................ 4 ? w ? iting data to the eeprom ................................................................................................ 4 ? w ? ite p ? ote ? tion ..................................................................................................................... 4 ? eeprom inte ?? upt ............. ................................................................................................... 4 ? p ? og ? a ?? ing conside ? ations ............. ................................................................................... 47 oscillators .......... ............................................................................................ 48 os ? illato ? ove ? view ............. .................................................................................................. 48 system clock confgurations ................................................................................................ 48 inte ? nal rc os ? illato ? C hirc ............. .................................................................................. 48 inte ? nal 3 ? khz os ? illato ? C lirc ........................................................................................... 49 exte ? nal 3 ? .7 ? 8khz c ? ystal os ? illato ? C lxt ............. ........................................................... 49 operating modes and system clocks ......................................................... 51 syste ? clo ? ks ...................................................................................................................... ? 1 syste ? ope ? ation modes ...................................................................................................... ?? cont ? ol registe ? .................................................................................................................... ? 3 ope ? ating mode swit ? hing ................................................................................................... ? 4 stand ? y cu ?? ent conside ? ations ........................................................................................... ? 7 wake-up ................................................................................................................................ ? 8 p ? og ? a ?? ing conside ? ations ............. ................................................................................... ? 8 watchdog timer ........... .................................................................................. 59 wat ? hdog ti ? e ? clo ? k sou ?? e .............................................................................................. ? 9 wat ? hdog ti ? e ? cont ? ol registe ? ............. ............................................................................ ? 9 wat ? hdog ti ? e ? ope ? ation ................................................................................................... ? 0 reset and initialisation .................................................................................. 61 reset fun ? tions ............. ....................................................................................................... ? 1 reset initial conditions ......................................................................................................... ? 3 input/output ports ......................................................................................... 68 i/o registe ? list .................................................................................................................... ? 8 pull-high resisto ? s ................................................................................................................ ? 8 po ? t a wake-up ............. ........................................................................................................ ? 9 i/o po ? t cont ? ol registe ? s ..................................................................................................... ? 9 pin- ? e ? apping fun ? tion ............. ........................................................................................... ? 9 i/o pin st ? u ? tu ? es .................................................................................................................. 70 sou ?? e cu ?? ent sele ? tion ............. ......................................................................................... 71 p ? og ? a ?? ing conside ? ations ............. ................................................................................... 7 ? timer modules C tm .......... ............................................................................ 73 int ? odu ? tion ........................................................................................................................... 73 tm ope ? ation ............. ........................................................................................................... 73 tm clo ? k sou ?? e ............. ...................................................................................................... 73 tm inte ?? upts ......................................................................................................................... 74 tm exte ? nal pins ................................................................................................................... 74
rev. 1.40 4 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 ? de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver tm input/output pin cont ? ol registe ? ................................................................................... 7 ? p ? og ? a ?? ing conside ? ations ............. ................................................................................... 77 compact type tm C ctm 0 .......... .................................................................. 78 co ? pa ? t tm ope ? ation ......................................................................................................... 78 co ? pa ? t type tm registe ? des ?? iption ................................................................................ 78 co ? pa ? t type tm ope ? ating modes .................................................................................... 8 ? periodic type tm C ptm 1 & ptm2 ............................................................... 88 pe ? iodi ? tm ope ? ation ............. ............................................................................................. 88 pe ? iodi ? type tm registe ? des ?? iption ................................................................................. 89 pe ? iodi ? type tm ope ? ating modes ...................................................................................... 93 analog to digital converter .......... .............................................................. 102 a/d ove ? view ............. ......................................................................................................... 10 ? a/d conve ? te ? registe ? des ?? iption .................................................................................... 10 ? a/d conve ? te ? data registe ? s C adrl ? adrh ................................................................... 103 a/d conve ? te ? cont ? ol registe ? s C adcr0 ? adcr1 ? acerl ............................................. 103 a/d ope ? ation ..................................................................................................................... 10 ? a/d input pins ............. ........................................................................................................ 107 su ?? a ? y of a/d conve ? sion steps ............. ........................................................................ 108 p ? og ? a ?? ing conside ? ations ............. ................................................................................. 109 a/d t ? ansfe ? fun ? tion ............. ............................................................................................ 109 a/d p ? og ? a ?? ing exa ? ple s ................................................................................................ 110 touch key function ..................................................................................... 112 tou ? h key st ? u ? tu ? e ............................................................................................................. 11 ? touch key register defnition .............................................................................................. 11 ? tou ? h key ope ? ation ............................................................................................................ 117 tou ? h key inte ?? upt ............................................................................................................. 1 ? 0 p ? og ? a ?? ing conside ? ations ............. ................................................................................. 1 ? 0 serial interface module C sim ..................................................................... 121 spi inte ? fa ? e ....................................................................................................................... 1 ? 1 i ? c inte ? fa ? e ............ ............................................................................................................ 1 ? 7 uart interface ............................................................................................ 137 uart exte ? nal pin inte ? fa ? ing ............................................................................................ 137 uart data t ? ansfe ? s ? he ? e .............................................................................................. 138 uart status and cont ? ol registe ? s .................................................................................... 138 baud rate gene ? ato ? .......................................................................................................... 144 cal ? ulating the baud rate and e ?? o ? values ....................................................................... 144 uart setup and cont ? ol ..................................................................................................... 14 ? uart t ? ans ? itte ? ................................................................................................................ 14 ? uart re ? eive ? ............. ...................................................................................................... 148 managing re ? eive ? e ?? o ? s .................................................................................................. 149 uart module inte ?? upt st ? u ? tu ? e ........................................................................................ 1 ? 0 uart powe ? down and wake-up ....................................................................................... 1 ??
rev. 1.40 4 de?e??e? 0?? ?01? rev. 1.40 ? de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver interrupts ...................................................................................................... 153 inte ?? upt registe ? s ............................................................................................................... 1 ? 3 inte ?? upt ope ? ation .............................................................................................................. 1 ? 7 exte ? nal inte ?? upt ............. .................................................................................................... 1 ? 8 a/d conve ? te ? inte ?? upt ....................................................................................................... 1 ? 9 ti ? e base inte ?? upts ........................................................................................................... 1 ? 9 tm inte ?? upts ....................................................................................................................... 1 ? 0 eeprom inte ?? upt ............. ................................................................................................. 1 ? 1 lvd inte ?? upt ....................................................................................................................... 1 ? 1 tou ? h key inte ?? upt ............................................................................................................. 1 ? 1 se ? ial inte ? fa ? e module inte ?? upt ......................................................................................... 1 ? 1 uart inte ?? upt ............. ....................................................................................................... 1 ?? inte ?? upt wake-up fun ? tion ................................................................................................. 1 ?? p ? og ? a ?? ing conside ? ations ............. ................................................................................. 1 ?? scom and sseg function for lcd .......... ................................................. 163 lcd ope ? ation ............. ....................................................................................................... 1 ? 3 lcd bias cont ? ol ................................................................................................................ 1 ?? low voltage detector C lvd .......... ............................................................. 166 lvd registe ? ............. .......................................................................................................... 1 ?? lvd ope ? ation ..................................................................................................................... 1 ? 7 confguration options ................................................................................. 168 application circuit ....................................................................................... 168 instruction set .............................................................................................. 169 int ? odu ? tion ......................................................................................................................... 1 ? 9 inst ? u ? tion ti ? ing ................................................................................................................ 1 ? 9 moving and t ? ansfe ?? ing data ............................................................................................. 1 ? 9 a ? ith ? eti ? ope ? ations .......................................................................................................... 1 ? 9 logi ? al and rotate ope ? ation ............................................................................................. 170 b ? an ? hes and cont ? ol t ? ansfe ? ........................................................................................... 170 bit ope ? ations ..................................................................................................................... 170 ta ? le read ope ? ations ....................................................................................................... 170 othe ? ope ? ations ............. .................................................................................................... 170 instruction set summary .......... .................................................................. 171 ta ? le conventions ............................................................................................................... 171 extended inst ? u ? tion set ............. ........................................................................................ 173 instruction defnition ................................................................................... 175 ([whghg,vwuxfwlrhlwlr ........................................................................................... 184 package information ................................................................................... 191 ? 0-pin sop(300 ? il) outline di ? ensions ............................................................................ 19 ? ? 4-pin sop(300 ? il) outline di ? ensions ............................................................................ 193 ? 8 -pin sop( 300 ? il) outline di ? ensions ............................................................................ 194
rev. 1.40 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 7 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver features cpu features ? operating v oltage f sys = 8m hz: 2. 7v~5.5v f sys = 12m hz: 2.7v~5.5v f sys = 16m hz: 4.5v~5.5v ? up to 0.2 5 s instruction cycle with 16 mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? three oscillators high speed internal rc -- hirc: 8/12/16mhz low speed internal rc -- lirc: 32khz low speed external crystal -- lxt: 32768hz (for bs86c16a-3/BS86D20A-3 only) ? multi-mode operation: normal, slow, idle and sleep ? all instructions executed in one to three instruction cycles ? table read instructions ? 115 powerful instructions ? u p to 8 -level subroutine nesting ? bit manipulation instruction
rev. 1.40 ? de?e??e? 0?? ?01? rev. 1.40 7 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver peripheral features ? flash program memory: 2k 16~8k 16 ? ram data memory: 384 8~768 8 ? true eeprom memory: 648 ? fully integrated 12/16/20 touch key functions -- require no external components ? watchdog t imer function ? u p to 26 bidirectional i/o lines ? pmos source current adjustable ? software controlled 4-scom lines lcd driver with 1/3 bias ? one e xternal interrupt line shared with i/o pin ? multiple t imer module for time measure, input capture, compare match output, pwm output or single pulse output function ? dual t ime-base function s for generation of fxed time interrupt signals ? multi-channel 12-bit resolution a/d converter ? serial interfaces module C sim for spi or i 2 c ? uart interface ? low voltage reset function ? low voltage detect function ? flash program memory can be re-programmed up to 100,000 times ? flash program memory data retention > 10 years ? true eeprom data memory can be re-programmed up to 1,000,000 times ? true eeprom data memory data retention > 10 years ? package: 20/24/28-pin sop
rev. 1.40 8 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 9 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver general description these devices are a series of flash memory type 8-bit high performance risc architecture microcontrollers with fully integrated touch key functions. w ith all touch key functions provided internally and with the convenience of flash memory multi-programming features, these devices have all the features to of fer designers a reliable and easy means of implementing touch switches within their product applications. the touch key functions are fully integrated thus completely eliminating the need for external components. in a ddition t o t he fl ash pro gram me mory, ot her m emory i ncludes a n a rea of ram data memory as well as an area of true eeprom memory for storage of non-volatile data such as serial num bers, c alibration da ta e tc. ana log fe ature i ncludes a m ulti-channel 12- bit a/ d c onverter. protective features such as an internal w atchdog t imer, low v oltage reset and low v oltage detector functions coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. a full choice of internal, external high and low speed oscillators are provided including a fully integrated syst em osc illator whi ch re quire no e xternal c omponents for i ts i mplementation. t he ability t o opera te a nd swi tch dyna mically be tween a ra nge of opera ting m odes usi ng di fferent clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. easy communication with the outside world is provided using the fully integrated spi or i2c interface functions, while the inclusion of fexible i/o programming features, t imer modules and many other features further enhance device functionality and fexibility. a uar t module is contained within these devices. this interface can support applications such as da ta c ommunication ne tworks be tween m icrocontrollers, l ow-cost da ta l inks be tween pcs a nd peripheral devices, portable and battery operated device communication, etc. these touch key devices will find excellent use in a huge range of modern t ouch key product applications such as instrumentatio n, household appliances, electronic ally controlled tools to name but a few. selection table most fe atures a re c ommon t o these de vices , the m ain features distinguishing them are memory capacity, i/o count, lcd driver segment count, t ouch key count, stack capacity amd package types . the following table summarises the main features of each device. part no. v dd program memory data memory data eeprom i/o ext. int. a/d bs8 ? b1 ? a-3 ? .7v~ ? . ? v ? k1 ? 3848 ? 4 8 ?? 1 1 ? - ? it 8 bs8 ? c1 ? a-3 ? .7v~ ? . ? v 4k1 ? ? 1 ? 8 ? 4 8 ?? 1 1 ? - ? it 8 bs8 ? d ? 0a-3 ? .7v~ ? . ? v 8k1 ? 7 ? 8 8 ? 4 8 ?? 1 1 ? - ? it 8 part no. lcd driver timer module touch key interface (spi/i 2 c) uart time base stack package bs8 ? b1 ? a-3 1 ? 4 10- ? it ctm 1 10- ? it ptm ? 1 ? ? ? ? 0/ ? 4sop bs8 ? c1 ? a-3 ? 0 4 10- ? it ctm 1 10- ? it ptm ? 1 ? ? ? ? 4/ ? 8sop bs8 ? d ? 0a-3 ? 0 4 10- ? it ctm 1 10- ? it ptm ? ? 0 ? 8 ? 4/ ? 8sop
rev. 1.40 8 de?e??e? 0?? ?01? rev. 1.40 9 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver block diagram 8-bit risc mcu core timer modules flash program memory eeprom data memory flash/eeprom programming circuitry (icp/ocds) ram data memory time bases reset circuit lxt oscillator interrupt controller led driver lcd driver touch keys hirc/lirc oscillators uart sim (spi&i 2 c) i/o watchdog timer low voltage detect low voltage reset 12-bit a/d converter note: the lxt oscillator is only for the bs86c16a-3 and BS86D20A-3. pin assignment ?0 19 18 17 1? 1? 14 13 1? 11 1 ? 3 4 ? ? 7 8 9 10 pa3/sdi/sda/rx pa0/sdo/ptck1/scom?/icpda/ocdsda pa?/scs/ptp1i/sco m3/icpck/ocdsck pa7/sck/scl/tx vdd vss pa1/scom0 pa4/int/ctck0/scom1 pc?/ctp0b/sseg13/an? pc4/ptp1b/sseg1?/an4 pc3/sseg11/key1?/an3 pc?/sseg10/key11/an? pc1/sseg9/key10/an1 pc0/sseg8/key9/an0/vref pb?/ptck?/sseg?/key? pb4/[ptp?i]/sseg4/key? pb3/ptp?b/sseg3/key4 pb?/sseg?/key3 pb1/sseg1/key? pb0/sseg0/key1 bs86b12a-3/bs86bv12a 20 sop-a ?4 ?3 ?? ?1 ?0 19 18 17 1? 1? 14 13 1 ? 3 4 ? ? 7 8 9 10 11 1? pa3/sdi/sda/rx pa0/sdo/ptck1/scom?/icpda/ocdsda bs86b12a-3/bs86bv12a 24 sop-a pa?/scs/ptp1i/scom3/icpck/ocdsck pa7/sck/scl/tx vdd vss pa1/scom0 pa4/int/ctck0/scom1 pc7/ctp0/sseg1?/an7 pc?/ptp1/sseg14/an? pc?/ctp0b/sseg13/an? pc4/ptp1b/sseg1?/an4 pc3/sseg11/key1?/an3 pc?/sseg10/key11/an? pc1/sseg9/key10/an1 pc0/sseg8/key9/an0/vref pb7/ptp?i/sseg7/key8 pb?/ptp?/sseg?/key7 pb?/ptck?/sseg?/key? pb4/[ptp?i]/sseg4/key? pb3/ptp?b/sseg3/key4 pb?/sseg?/key3 pb1/sseg1/key? pb0/sseg0/key1
rev. 1.40 10 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 11 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver ?4 ?3 ?? ?1 ?0 19 18 17 1? 1? 14 13 1 ? 3 4 ? ? 7 8 9 10 11 1? pa 3/ sdi / sda / rx pa 0/ sdo / ptck 1/ scom ?/ icpda / ocdsda bs 86 c 16 a-3/ bs 86 cv 16 a-3 24 sop -a pa ?/ scs / ptp 1i/ scom 3/ icpck / ocdsck pa 7/ sck / scl / tx vdd vss pa 1/ scom 0 pa 4/ int / ctck 0/ scom 1 pc 7/ ctp 0/ sseg 1?/ key 1?/ an 7 pc ?/ ptp 1/ sseg 14 / key 1?/ an ? pc ?/ sseg 13/ key 14/ an ? pc 4/ sseg 1?/ key 13/ an 4 pc 3/ sseg 11/ key 1?/ an 3 pc ?/ sseg 10/ key 11/ an ? pc 1/ sseg 9/ key 10/ an 1 pc 0/ sseg 8/ key 9/ an 0/ vref pb 7/ ptp ?i/ sseg 7/ key 8 pb ?/ ptp ?/ sseg ?/ key 7 pb ?/ ptck ?/ sseg ?/ key ? pb 4/ sseg 4/ key ? pb 3/ sseg 3/ key 4 pb ?/ sseg ?/ key 3 pb 1/ sseg 1/ key ? pb 0/ sseg 0/ key 1 ?8 ?7 ?? ?? ?4 ?3 ?? ?1 ?0 19 18 17 1? 1? 1 ? 3 4 ? ? 7 8 9 10 11 1? 13 14 pa 3/ sdi / sda / rx pa 0/ sdo / ptck 1/ scom ?/ icpda / ocdsda bs 86c 16 a-3/ bs 86 cv 16 a-3 28 sop -a pa ?/ scs / ptp 1i/ scom 3/ icpck / ocdsck pa 7/ sck / scl / tx vdd vss pa 1/ scom 0 pa 4/ int / ctck 0/ scom 1 pc 7/ ctp 0/ sseg 1?/ key 1?/ an 7 pc ?/ ptp 1/ sseg 14/ key 1?/ an ? pc ?/ sseg 13/ key 14/ an ? pc 4/ sseg 1?/ key 13/ an 4 pc 3/ sseg 11/ key 1?/ an 3 pc ?/ sseg 10/ key 11/ an ? pc 1/ sseg 9/ key 10/ an 1 pc 0/ sseg 8/ key 9/ an 0/ vref pb 7/ ptp ?i/ sseg 7/ key 8 pb ?/ ptp ?/ sseg ?/ key 7 pb ?/ ptck ?/ sseg ?/ key ? pb 4/ sseg 4/ key ? pb 3/ sseg 3/ key 4 pb ?/ sseg ?/ key 3 pb 1/ sseg 1/ key ? pb 0/ sseg 0/ key 1 pd 1/ ctp 0b/ sseg 17/ xt ? pd 0/ ptp 1b/ sseg 1? / xt 1 pd ?/ sseg 18 pd 3/ ptp ?b/ sseg 19
rev. 1.40 10 de?e??e? 0?? ?01? rev. 1.40 11 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver ?4 ?3 ?? ?1 ?0 19 18 17 1? 1? 14 13 1 ? 3 4 ? ? 7 8 9 10 11 1? pa 3/ sdi / sda / rx pa 0/ sdo / ptck 1/ scom ?/ icpda / ocdsda bs 86d 20 a-3/ bs 86dv 20 a-3 24 sop -a pa ?/ scs / ptp 1i/ scom 3/ icpck / ocdsck pa 7/ sck / scl / tx vdd vss pa 1/ scom 0/ key ?0 pa 4/ int / ctck 0/ scom 1/ key 19 pc 7/ ctp 0/ sseg 1?/ key 18/ an 7 pc ?/ ptp 1/ sseg 14 / key 17/ an ? pc ?/ sseg 13/ key 1?/ an ? pc 4/ sseg 1?/ key 1?/ an 4 pc 3/ sseg 11 / key 14/ an 3 pc ?/ sseg 10 / key 13/ an ? pc 1/ sseg 9/ key 1?/ an 1 pc 0/ sseg 8/ key 11/ an 0/ vref pb 7/ ptp ?i/ sseg 7/ key8 pb ?/ ptp ?/ sseg ?/ key7 pb ?/ ptck ?/ sseg ?/ key? pb 4/ sseg 4/ key? pb 3/ sseg 3/ key4 pb ?/ sseg ?/ key3 pb 1/ sseg 1/ key? pb 0/ sseg 0/ key1 ?8 ?7 ?? ?? ?4 ?3 ?? ?1 ?0 19 18 17 1? 1? 1 ? 3 4 ? ? 7 8 9 10 11 1? 13 14 pa 3/ sdi / sda / rx pa 0/ sdo / ptck 1/ scom ?/ icpda / ocdsda bs 86d 20 a-3/ bs 86 dv 20 a-3 28 sop -a pa ?/ scs / ptp 1i/ scom 3/ icpck / ocdsck pa 7/ sck / scl / tx vdd vss pa 1/ scom 0/ key ?0 pa 4/ int / ctck 0/ scom 1/ key19 pc 7/ ctp 0/ sseg 1?/ key 18/ an 7 pc ?/ ptp 1/ sseg 14/ key 17/ an ? pc ?/ sseg 13/ key 1?/ an ? pc 4/ sseg 1?/ key 1?/ an 4 pc 3/ sseg 11/ key 14/ an 3 pc ?/ sseg 10 / key 13/ an ? pc 1/ sseg 9/ key 1? / an 1 pc 0/ sseg 8/ key 11/ an 0/ vref pb 7/ ptp ?i/ sseg 7/ key8 pb ?/ ptp ?/ sseg ?/ key 7 pb ?/ ptck ?/ sseg ?/ key ? pb 4/ sseg 4/ key ? pb 3/ sseg 3/ key 4 pb ?/ sseg ?/ key 3 pb 1/ sseg 1/ key ? pb 0/ sseg 0/ key 1 pd 1/ ctp 0b/ sseg 17/ xt ? pd 0/ ptp 1b/ sseg 1? / xt 1 pd ?/ sseg 18/ key 10 pd 3/ ptp ?b/ sseg 19/ key9 note: 1. if the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the / sign can be used for higher priority. 2. the ocdsda and ocdsck pins are the ocds dedicated pins and only available for the bs86bv12a/ bs86cv16a-3/bs86dv20a-3 devices, which are the ocds ev chips for the bs86b12a-3/bs86c16a-3/ BS86D20A-3 devices respectively.
rev. 1.40 1 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 13 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver pin description s with the exception of the power pins and some relevant transformer control pins, all pins on the device can be referenced by their port name, e.g. p a0, p a1, etc, which refer to the digital i/o function of the pins. however these port pins are also shared with other function such as the t ouch key function, t imer modules, etc. the function of each pin is listed in the following table s , however the details behind how each pin is confgured is contained in other sections of the datasheet. as the pin description table shows the situation for the package with the most pins, not all pins in the table will be available on smaller package sizes. bs86b12a-3 pin name function op i/t o/t description pa0/sdo/ ptck1/ scom ? /icpda/ ocdsda pa0 pawu papu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. sdo simc0 cmos spi data output ptck1 ptm1c0 st ptm1 ? lo ? k input scom ? slcdc0 scom lcd d ? ive ? output fo ? lcd panel ? o ?? on icpda st cmos in- ? i ?? uit p ? og ? a ?? ing add ? ess/data pin ocdsda st cmos on- ? hip de ? ug suppo ? t data/add ? ess pin ? fo ? ev ? hip only. pa1/scom0 pa1 pawu papu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. scom0 slcdc0 scom lcd d ? ive ? output fo ? lcd panel ? o ?? on pa ? / scs/ptp1i/ scom3/icpck/ ocdsck pa ? pawu papu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. scs simc0 st cmos spi slave sele ? t ptp1i ptm1c0 ptm1c1 st ptm1 input scom3 slcdc0 scom lcd d ? ive ? output fo ? lcd panel ? o ?? on icpck st in- ? i ?? uit p ? og ? a ?? ing ? lo ? k pin ocdsck st on- ? hip de ? ug suppo ? t ? lo ? k pin ? fo ? ev ? hip only. pa3/sdi/sda/ rx pa3 pawu papu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. sdi simc0 st spi data input sda simc0 st nmos i ? c data rx ucr1 st uart ? e ? eive ? data input pa4/int/ctck0/ scom1 pa4 pawu papu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. int intc0 integ st exte ? nal inte ?? upt ctck0 ctm0c0 st ctm0 ? lo ? k input scom1 slcdc0 st scom lcd d ? ive ? output fo ? lcd panel ? o ?? on pa7/sck/scl/ tx pa7 pawu papu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. sck simc0 st cmos spi se ? ial ? lo ? k scl simc0 st nmos i ? c clo ? k tx ucr1 cmos uart t ? ans ? itte ? data output pb0/sseg0/ key1 pb0 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg0 slcdc1 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key1 tkm0c1 nsi tou ? h key input
rev. 1.40 1? de?e??e? 0?? ?01? rev. 1.40 13 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver pin name function op i/t o/t description pb1/sseg1/ key ? pb1 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg1 slcdc1 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key ? tkm0c1 nsi tou ? h key input pb ? /sseg ? / key3 pb ? pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg ? slcdc1 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key3 tkm0c1 nsi tou ? h key input pb3/ptp ? b/ sseg3/key4 pb3 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. ptp ? b tmpc cmos ptm ? output sseg3 slcdc1 lcd d ? ive ? output fo ? lcd panel seg ? ent key4 tkm0c1 nsi tou ? h key input pb4/[ptp ? i]/ sseg4/key ? pb4 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. ptp ? i ptm ? c0 ptm ? c1 ifs st ptm ? input sseg4 slcdc1 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key ? tkm1c1 nsi tou ? h key input pb ? /ptck ? / sseg ? /key ? pb ? pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. ptck ? ptm ? c0 st ptm ? ? lo ? k input sseg ? slcdc1 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key ? tkm1c1 nsi tou ? h key input pb ? /ptp ? / sseg ? /key7 pb ? pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. ptp ? tmpc cmos ptm ? output sseg ? slcdc1 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key7 tkm1c1 nsi tou ? h key input pb7/ptp ? i/ sseg7/key8 pb7 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. ptp ? i ptm ? c0 ptm ? c1 ifs st ptm ? input sseg7 slcdc1 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key8 tkm1c1 nsi tou ? h key input pc0/sseg8/ key9/an0/vref pc0 pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg8 slcdc ? cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key9 tkm ? c1 nsi tou ? h key input an0 acerl an a/d conve ? te ? intput vref adcr1 an a/d conve ? te ? ? efe ? en ? e input pc1/sseg9/ key10/an1 pc1 pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg9 slcdc ? cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key10 tkm ? c1 nsi tou ? h key input an1 acerl an a/d conve ? te ? intput pc ? /sseg10/ key11/an ? pc ? pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg10 slcdc ? cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key11 tkm ? c1 nsi tou ? h key input an ? acerl an a/d conve ? te ? intput pc3/sseg11/ key1 ? /an3 pc3 pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg11 slcdc ? cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key1 ? tkm ? c1 nsi tou ? h key input an3 acerl an a/d conve ? te ? intput
rev. 1.40 14 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 1? de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver pin name function op i/t o/t description pc4/ptp1b/ sseg1 ? /an4 pc4 pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. ptp1b tmpc cmos ptm1 output sseg1 ? slcdc ? lcd d ? ive ? output fo ? lcd panel seg ? ent an4 acerl an a/d conve ? te ? intput pc ? /ctp0b/ sseg13/an ? pc ? pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. ctp0b tmpc cmos ctm0 output sseg13 slcdc ? cmos lcd d ? ive ? output fo ? lcd panel seg ? ent an ? acerl an a/d conve ? te ? intput pc ? /ptp1/ sseg14/an ? pc ? pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. ptp1 tmpc cmos ptm1 output sseg14 slcdc ? cmos lcd d ? ive ? output fo ? lcd panel seg ? ent an ? acerl an a/d conve ? te ? intput pc7/ctp0/ sseg1 ? /an7 pc7 pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. ctp0 tmpc cmos ctm0 output sseg1 ? slcdc ? cmos lcd d ? ive ? output fo ? lcd panel seg ? ent an7 acerl an a/d conve ? te ? intput vdd vdd pwr powe ? supply vss vss pwr g ? ound legend: i/t: input type; o/t: output type op: optional by register selection pwr: power; st: schmitt t rigger input cmos: cmos output; nmos: nmos output; scom: scom output an: analog signal; nsi: non-standard input bs86c16a-3 pin name function op i/t o/t description pa0/ sdo/ ptck1/ scom ? /icpda/ ocdsda pa0 pa wu pa pu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. sdo simc0 cmos spi data output ptck1 ptm1c0 st ptm1 ? lo ? k input scom ? slcdc0 scom lcd d ? ive ? output fo ? lcd panel ? o ?? on icpda st cmos in- ? i ?? uit p ? og ? a ?? ing add ? ess/data pin ocdsda st cmos on- ? hip de ? ug suppo ? t data/add ? ess pin ? fo ? ev ? hip only. pa1/ scom0 pa1 pa wu pa pu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. scom0 slcdc0 scom lcd d ? ive ? output fo ? lcd panel ? o ?? on pa ? / scs/ptp1i/ scom3/icpck/ ocdsck pa ? pa wu pa pu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. scs simc0 st cmos spi slave sele ? t ptp1i ptm1c0 ptm1c1 st ptm1 input scom3 slcdc0 scom lcd d ? ive ? output fo ? lcd panel ? o ?? on icpck st in- ? i ?? uit p ? og ? a ?? ing ? lo ? k pin ocdsck st on- ? hip de ? ug suppo ? t ? lo ? k pin ? fo ? ev ? hip only.
rev. 1.40 14 de?e??e? 0?? ?01? rev. 1.40 1 ? de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver pin name function op i/t o/t description pa 3/sdi/sda/rx pa 3 pa wu pa pu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. sdi simc0 st spi data input sda simc0 st nmos i ? c data rx ucr1 st uart ? e ? eive ? data input pa4/int/ctck0/ scom1 pa4 pa wu pa pu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. int intc0 integ st exte ? nal inte ?? upt ctck0 ctm0c0 st ctm0 ? lo ? k input scom1 slcdc0 scom lcd d ? ive ? output fo ? lcd panel ? o ?? on pa7/sck/scl/tx pa7 pa wu pa pu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. sck simc0 st cmos spi se ? ial ? lo ? k scl simc0 st nmos i ? c clo ? k tx ucr1 cmos uart t ? ans ? itte ? data output pb0/sseg0/ key1 pb0 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg0 slcdc1 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key1 tkm0c1 nsi tou ? h key input pb1/sseg1/ key ? pb1 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg1 slcdc1 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key ? tkm0c1 nsi tou ? h key input pb ? /sseg ? / key3 pb ? pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg ? slcdc1 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key3 tkm0c1 nsi tou ? h key input pb3/sseg3/ key4 pb3 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg3 slcdc1 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key4 tkm0c1 nsi tou ? h key input pb4/sseg4/ key ? pb4 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg4 slcdc1 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key ? tkm1c1 nsi tou ? h key input pb ? /ptck ? / sseg ? /key ? pb ? pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. ptck ? ptm ? c0 st ptm ? ? lo ? k input sseg ? slcdc1 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key ? tkm1c1 nsi tou ? h key input pb ? /ptp ? / sseg ? /key7 pb ? pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. ptp ? tmpc cmos ptm ? output sseg ? slcdc1 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key7 tkm1c1 nsi tou ? h key input pb7/ptp ? i/ sseg7/key8 pb7 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. ptp ? i ptm ? c0 ptm ? c1 st ptm ? input sseg7 slcdc1 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key8 tkm1c1 nsi tou ? h key input
rev. 1.40 1 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 17 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver pin name function op i/t o/t description pc0/sseg8/ key9/an0/vref pc0 pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg8 slcdc ? cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key9 tkm ? c1 nsi tou ? h key input an0 acerl an a/d conve ? te ? intput vref adcr1 an a/d conve ? te ? ? efe ? en ? e input pc1/sseg9/ key10/an1 pc1 pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg9 slcdc ? cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key10 tkm ? c1 nsi tou ? h key input an1 acerl an a/d conve ? te ? intput pc ? /sseg10/ key11/an ? pc ? pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg10 slcdc ? cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key11 tkm ? c1 nsi tou ? h key input an ? acerl an a/d conve ? te ? intput pc3/sseg11/ key1 ? /an3 pc3 pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg11 slcdc ? cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key1 ? tkm ? c1 nsi tou ? h key input an3 acerl an a/d conve ? te ? intput pc4/sseg1 ? / key13/an4 pc4 pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg1 ? slcdc ? cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key13 tkm3c1 nsi tou ? h key input an4 acerl an a/d conve ? te ? intput pc ? /sseg13/ key14/an ? pc ? pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg13 slcdc ? cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key14 tkm3c1 nsi tou ? h key input an ? acerl an a/d conve ? te ? intput pc ? /ptp1/ sseg14/ key1 ? /an ? pc ? pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. ptp1 tmpc cmos ptm1 output sseg14 slcdc ? cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key1 ? tkm3c1 nsi tou ? h key input an ? acerl an a/d conve ? te ? intput pc7/ctp0/ sseg1 ? / key1 ? /an7 pc7 pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. ctp0 tmpc cmos ctm0 output sseg1 ? slcdc ? cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key1 ? tkm3c1 nsi tou ? h key input an7 acerl an a/d conve ? te ? intput pd0/ptp1b/ sseg1 ? /xt1 pd0 pdpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. ptp1b tmpc cmos ptm1 output sseg1 ? slcdc3 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent xt1 co lxt lxt pin
rev. 1.40 1? de?e??e? 0?? ?01? rev. 1.40 17 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver pin name function op i/t o/t description pd1/ctp0b/ sseg17/xt ? pd1 pdpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. ctp0b tmpc cmos ctm0 output sseg17 slcdc3 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent xt ? co lxt lxt pin pd ? /sseg18 pd ? pdpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg18 slcdc3 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent pd3/ptp ? b/ sseg19 pd3 pdpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. ptp ? b tmpc cmos ptm ? output sseg19 slcdc3 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent vdd vdd pwr powe ? supply vss vss pwr g ? ound legend: i/t : input type ; o/t : output type op: optional by confguration option (co) or register selection pwr : power ; st : s chmitt t rigger input c mos : cmos output ; nmos : nmos output ; scom: scom output an: analog signal; nsi: no n-standard input lxt: low frequency crystal oscillator BS86D20A-3 pin na ? e fun ? tion op i/t o/t des ?? iption pa0/ sdo/ptck1/ scom ? /icpda/ ocdsda pa0 pa wu pa pu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. sdo simc0 cmos spi data output ptck1 ptm1c0 st ptm1 ? lo ? k input scom ? slcdc0 scom lcd d ? ive ? output fo ? lcd panel ? o ?? on icpda st cmos in- ? i ?? uit p ? og ? a ?? ing add ? ess/data pin ocdsda st cmos on- ? hip de ? ug suppo ? t data/add ? ess pin ? fo ? ev ? hip only. pa1/ scom0/ key ? 0 pa1 pa wu pa pu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. scom0 slcdc0 scom lcd d ? ive ? output fo ? lcd panel ? o ?? on key ? 0 tkm4c1 nsi tou ? h key input pa ? / scs/ptp1i/ scom3/icpck/ ocdsck pa ? pa wu pa pu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. scs simc0 st cmos spi slave sele ? t ptp1i ptm1c0 ptm1c1 st ptm1 input scom3 slcdc0 scom lcd d ? ive ? output fo ? lcd panel ? o ?? on icpck st in- ? i ?? uit p ? og ? a ?? ing ? lo ? k pin ocdsck st on- ? hip de ? ug suppo ? t ? lo ? k pin ? fo ? ev ? hip only. pa 3/sdi/sda/rx pa 3 pa wu pa pu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. sdi simc0 st spi data input sda simc0 st nmos i ? c data rx ucr1 st uart ? e ? eive ? data input
rev. 1.40 18 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 19 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver pin na ? e fun ? tion op i/t o/t des ?? iption pa4/int/ctck0/ scom1/key19 pa4 pa wu pa pu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. int intc0 integ st exte ? nal inte ?? upt ctck0 ctm0c0 st ctm0 ? lo ? k input scom1 slcdc0 scom lcd d ? ive ? output fo ? lcd panel ? o ?? on key19 tkm4c1 nsi tou ? h key input pa7/sck/scl/tx pa7 pa wu pa pu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. sck simc0 st cmos spi se ? ial ? lo ? k scl simc0 st nmos i ? c clo ? k tx ucr1 cmos uart t ? ans ? itte ? data output pb0/sseg0/ key1 pb0 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg0 slcdc1 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key1 tkm0c1 nsi tou ? h key input pb1/sseg1/ key ? pb1 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg1 slcdc1 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key ? tkm0c1 nsi tou ? h key input pb ? /sseg ? / key3 pb ? pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg ? slcdc1 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key3 tkm0c1 nsi tou ? h key input pb3/sseg3/ key4 pb3 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg3 slcdc1 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key4 tkm0c1 nsi tou ? h key input pb4/sseg4/ key ? pb4 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg4 slcdc1 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key ? tkm1c1 nsi tou ? h key input pb ? /ptck ? / sseg ? /key ? pb ? pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. ptck ? ptm ? c0 st ptm ? ? lo ? k input sseg ? slcdc1 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key ? tkm1c1 nsi tou ? h key input pb ? /ptp ? / sseg ? /key7 pb ? pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. ptp ? tmpc cmos ptm ? output sseg ? slcdc1 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key7 tkm1c1 nsi tou ? h key input pb7/ptp ? i/ sseg7/key8 pb7 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. ptp ? i ptm ? c0 ptm ? c1 st ptm ? input sseg7 slcdc1 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key8 tkm1c1 nsi tou ? h key input
rev. 1.40 18 de?e??e? 0?? ?01? rev. 1.40 19 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver pin na ? e fun ? tion op i/t o/t des ?? iption pc0/sseg8/ key11/an0/ vref pc0 pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg8 slcdc ? cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key11 tkm ? c1 nsi tou ? h key input an0 acerl an a/d conve ? te ? intput vref adcr1 an a/d conve ? te ? ? efe ? en ? e input pc1/sseg9/ key1 ? /an1 pc1 pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg9 slcdc ? cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key1 ? tkm ? c1 nsi tou ? h key input an1 acerl an a/d conve ? te ? intput pc ? /sseg10/ key13/an ? pc ? pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg10 slcdc ? cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key13 tkm ? c1 nsi tou ? h key input an ? acerl an a/d conve ? te ? intput pc3/sseg11/ key14/an3 pc3 pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg11 slcdc ? cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key14 tkm3c1 nsi tou ? h key input an3 acerl an a/d conve ? te ? intput pc4/sseg1 ? / key1 ? /an4 pc4 pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg1 ? slcdc ? cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key1 ? tkm3c1 nsi tou ? h key input an4 acerl an a/d conve ? te ? intput pc ? /sseg13/ key1 ? /an ? pc ? pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg13 slcdc ? cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key1 ? tkm3c1 nsi tou ? h key input an ? acerl an a/d conve ? te ? intput pc ? /ptp1/ sseg14/ key17/an ? pc ? pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. ptp1 tmpc cmos ptm1 output sseg14 slcdc ? cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key17 tkm4c1 nsi tou ? h key input an ? acerl an a/d conve ? te ? intput pc7/ctp0/ sseg1 ? / key18/an7 pc7 pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. ctp0 tmpc cmos ctm0 output sseg1 ? slcdc ? cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key18 tkm4c1 nsi tou ? h key input an7 acerl an a/d conve ? te ? intput pd0/ptp1b/ sseg1 ? /xt1 pd0 pdpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. ptp1b tmpc cmos ptm1 output sseg1 ? slcdc3 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent xt1 co lxt lxt pin
rev. 1.40 ? 0 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 ?1 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver pin na ? e fun ? tion op i/t o/t des ?? iption pd1/ctp0b/ sseg17/xt ? pd1 pdpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. ctp0b tmpc cmos ctm0 output sseg17 slcdc3 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent xt ? co lxt lxt pin pd ? /sseg18/ key10 pd ? pdpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. sseg18 slcdc3 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key10 tkm ? c1 nsi tou ? h key input pd3/ptp ? b/ sseg19/key9 pd3 pdpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up. ptp ? b tmpc cmos ptm ? output sseg19 slcdc3 cmos lcd d ? ive ? output fo ? lcd panel seg ? ent key9 tkm ? c1 nsi tou ? h key input vdd vdd pwr powe ? supply vss vss pwr g ? ound legend: i/t : input type ; o/t : output type op: optional by confguration option (co) or register selection pwr : power ; st : s chmitt t rigger input c mos : cmos output ; nmos : nmos output ; scom: scom output an: analog signal; nsi: no n-standard input lxt: low frequency crystal oscillator absolute maximum ratings supply v oltage .............. .................................................................................. v ss ?0.3v to v ss +6.0v input v oltage .............. .................................................................................... v ss ? 0.3v to v dd +0.3v storage t emperature ............... ..................................................................................... -50? c to 125?c operating t emperature .............. .................................................................................... -40? c to 85 ?c i ol t otal .............. ................................................................................................... .................... 80ma i oh t otal .............. ...................................................................................................................... -80ma total power dissipation .............. ........................................................................................... 500mw note: t hese a re st ress ra tings onl y. st resses e xceeding t he ra nge spe cified und er "absol ute ma ximum ratings" m ay c ause su bstantial d amage t o t hese d evices. fu nctional o peration o f t hese d evices a t other c onditions be yond t hose l isted i n t he spe cifcation i s no t i mplied a nd pr olonged e xposure t o extreme conditions may affect devices reliability.
rev. 1.40 ?0 de?e??e? 0?? ?01? rev. 1.40 ? 1 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver d.c. characteristics ta= ?? c symbol parameter test conditions min. typ. max. unit v dd conditions v dd ope ? ating voltage (hirc) f sys = 8mhz ? .7 ? . ? v f sys = 1 ? mhz ? .7 ? . ? v f sys = 1 ? mhz 4. ? ? . ? v i dd ope ? ating cu ?? ent (no ?? al) (hirc ? f sys =f h ? f s =f sub ) 3v no load ? f h = 8mhz ? adc off ? wdt ena ? le ? lvr ena ? le 1. ? 1.8 ? a ? v ? . ? 3.3 ? a 3v no load ? f h = 1 ? mhz ? adc off ? wdt ena ? le ? lvr ena ? le 1. ? ? .4 ? a ? v 3.3 ? .0 ? a ? v no load ? f h = 1 ? mhz ? adc off ? wdt ena ? le ? lvr ena ? le 4.0 ? .0 ? a ope ? ating cu ?? ent (no ?? al) (hirc ? f sys =f l ? f s =f sub ) 3v no load ? f h = 1 ? mhz ? f l = f h / ?? adc off ? wdt ena ? le ? lvr ena ? le 1. ? ? .0 ? a ? v ? . ? 3.3 ? a ? v no load ? f h = 1 ? mhz ? f l = f h / ? 4 ? adc off ? wdt ena ? le ? lvr ena ? le 0.8 1. ? ? a 3v 1. ? ? .3 ? a ope ? ating cu ?? ent (slow) (lxt/lirc ? f sys =f l ? f s =f sub ) (bs8 ? c1 ? a-3/bs8 ? d ? 0a-3 only) 3v no load ? f sys =lxt ? adc off ? wdt ena ? le ? lvr ena ? le ? lxtlp=0 19 38 a ? v 48 9 ? a 3v no load ? f sys =lxt ? adc off ? wdt ena ? le ? lvr ena ? le ? lxtlp=1 1 ? 3 ? a ? v 3 ? 7 ? a 3v no load ? f sys =lirc ? adc off ? wdt ena ? le ? lvr ena ? le 1 ? 3 ? a ? v 3 ? 7 ? a ope ? ating cu ?? ent (slow) (lirc ? f sys =f l ? f s =f sub ) (bs8 ? b1 ? a-3 only) 3v no load ? f sys =lirc ? adc off ? wdt ena ? le ? lvr ena ? le 1 ? 3 ? a ? v 3 ? 7 ? a
rev. 1.40 ?? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 ?3 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver symbol parameter test conditions min. typ. max. unit v dd conditions i stb idle1 mode stand ? y cu ?? ent (hirc ? f sys =f h ? f s =f sub ) 3v no load ? syste ? halt ? adc off ? wdt ena ? le ? f sys = 1 ? mhz 0.9 1.4 ? a ? v 1.4 ? .1 ? a idle0 mode stand ? y cu ?? ent (hirc ? f sys =off ? f s =f sub ) 3v no load ? syste ? halt ? adc off ? wdt ena ? le ? f sys = 1 ? mhz 1.4 3.0 a ? v ? .7 ? .0 a idle1 mode stand ? y cu ?? ent (hirc ? f sys = f l ? f s =f sub ) 3v no load ? syste ? halt ? adc off ? wdt ena ? le ? f sys = 1 ? mhz / ? 4 0.7 1.1 ? a ? v 1.4 ? .1 ? a idle0 mode stand ? y cu ?? ent (hirc ? f sys =off ? f s =f sub ) 3v no load ? syste ? halt ? adc off ? wdt ena ? le ? f sys = 1 ? mhz / ? 4 1.3 3.0 a ? v ? .3 ? .0 a idle1 mode stand ? y cu ?? ent (lirc ? f sys = f l =f lirc ? f s = f sub =f lirc ) 3v no load ? syste ? halt ? adc off ? wdt ena ? le ? f sys = lirc 1.9 4.0 a ? v 3.3 7.0 a idle0 mode stand ? y cu ?? ent (lxt/lirc ? f sys =off ? f s =f sub ) (bs8 ? c1 ? a-3/bs8 ? d ? 0a-3 only) 3v no load ? syste ? halt ? adc off ? wdt ena ? le ? lxtlp=0 (lxt on) ? 10 a ? v 18 30 a 3v no load ? syste ? halt ? adc off ? wdt ena ? le ? lxtlp=1 (lxt on) ? . ? ? a ? v ? 10 a 3v no load ? syste ? halt ? adc off ? wdt ena ? le (lirc on) 1.3 3.0 a ? v ? .4 ? .0 a idle0 mode stand ? y cu ?? ent (lirc ? f sys =off ? f s =f sub ) (bs8 ? b1 ? a-3 only) 3v no load ? syste ? halt ? adc off ? wdt ena ? le (lirc on) 1.3 3.0 a ? v ? .4 ? .0 a sleep mode stand ? y cu ?? ent (hirc ? f sys =off ? f s =f sub = off) 3v no load ? syste ? halt ? adc off ? wdt dis a ? le (lxt and lirc off) 0.1 1 a ? v 0.3 ? a sleep mode stand ? y cu ?? ent (lxt/lirc ? f sys =off ? f s =f sub = off) (bs8 ? c1 ? a-3/bs8 ? d ? 0a-3 only) 3v no load ? syste ? halt ? adc off ? wdt dis a ? le (lxt and lirc off) 0.1 1 a ? v 0.3 ? a v il input low voltage fo ? i/o po ? ts o ? input pins ? v 0 1. ? v 0 0. ? v dd v v ih input high voltage fo ? i/o po ? ts o ? input pins ? v 3. ? ? .0 v 0.8v dd v dd v v lvr low voltage reset voltage lvr ena ? le ? ? . ?? v - ? % ? . ?? + ? % v v lv d low voltage dete ? to ? voltage lvden = 1 ? v lvd = ? . 7v - ? % ? .7 + ? % v lvden = 1 ? v lvd = 3.0v - ? % 3.0 + ? % v lvden = 1 ? v lvd = 3.3v - ? % 3.3 + ? % v lvden = 1 ? v lvd = 3. ? v - ? % 3. ? + ? % v lvden = 1 ? v lvd = 4.0v - ? % 4.0 + ? % v i ol i/o po ? t sink cu ?? ent 3v v ol =0.1v dd 1 ? 3 ? ? a ? v v ol =0.1v dd 3 ? ? 4 ? a
rev. 1.40 ?? de?e??e? 0?? ?01? rev. 1.40 ? 3 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver symbol parameter test conditions min. typ. max. unit v dd conditions i oh i/o po ? t sou ?? e cu ?? ent 3v v oh = 0.9v dd ? pxps=00 -1.0 - ? .0 ? a ? v v oh = 0.9v dd ? pxps=00 - ? .0 -4.0 ? a 3v v oh = 0.9v dd ? pxps=01 -1.7 ? -3. ? ? a ? v v oh = 0.9v dd ? pxps=01 -3. ? -7.0 ? a 3v v oh = 0.9v dd ? pxps=10 - ? . ? - ? .0 ? a ? v v oh = 0.9v dd ? pxps=10 - ? .0 -10 ? a 3v v oh = 0.9v dd ? pxps=11 - ? . ? -11 ? a ? v v oh = 0.9v dd ? pxps=11 -11 - ?? ? a r ph pull-high resistan ? e fo ? i/o po ? ts 3v ? 0 ? 0 100 k ? v 10 30 ? 0 k a.c. characteristics ta= ?? c symbol parameter test conditions min. typ. max. unit v dd conditions f sys syste ? clo ? k (hirc) 3v/ ? v ta= ?? c - ? % 8 + ? % mhz - ? % 1 ? + ? % mhz ? v - ? % 1 ? + ? % mhz t timer ti ? e ? input pulse width 0.3 s f lirc syste ? clo ? k (3 ? khz) ? v ta = ? ? c -10% 3 ? +10% khz f lxt syste ? clo ? k (lxt) 3 ? 7 ? 8 hz t int inte ?? upt pulse width 10 s t lvr low voltage width to reset 1 ? 0 ? 40 480 s t lv d low voltage width to inte ?? upt ? 0 1 ? 0 ? 40 s t lv ds lvdo sta ? le ti ? e 1 ? s t eerd eeprom read ti ? e 1 ? 4 t sys t eewr eeprom w ? ite ti ? e 1 ? 4 ? s t rstd syste ? reset delay ti ? e (powe ? on ? eset ? lvr ? eset ? wdt s/w ? eset (wdtc)) ?? ? 0 100 ? s syste ? reset delay ti ? e (wdt no ?? al ? eset) 8.3 1 ? .7 33.3 ? s t sst syste ? sta ? t-up ti ? e ? pe ? iod (wake-up f ? o ? halt) f sys =lxt 10 ? 4 t sys f sys =hirc 1 ? f sys =lirc ? syste ? sta ? t-up ti ? e ? pe ? iod (wake-up f ? o ? halt ? f sys on at halt state ) ? 1rwh t sys sys
rev. 1.40 ? 4 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 ?? de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver sensor oscillator electrical characteristics ta= ?? c touch key rc osc=500khz symbol parameter test conditions min. typ. max. unit v dd condition i keyosc only senso ? (key) os ? illato ? ope ? ating cu ?? ent 3v *f senosc = ? 00khz 30 ? 0 a ? v ? 0 1 ? 0 i refosc only refe ? en ? e os ? illato ? ope ? ating cu ?? ent 3v *f refosc = ? 00khz ? m ntss=0 30 ? 0 a ? v ? 0 1 ? 0 3v *f refosc = ? 00khz ? m ntss=1 30 ? 0 a ? v ? 0 1 ? 0 c keyosc senso ? (key) os ? illato ? exte ? nal capa ? itan ? e ? v *f senosc = ? 00khz ? 10 ? 0 pf c refosc refe ? en ? e os ? illato ? inte ? nal capa ? itan ? e ? v *f senosc = ? 00khz ? 10 ? 0 pf f keyosc senso ? (key) os ? illato ? ope ? ating f ? equen ? y ? v * exte ? nal capa ? itan ? e =7 ? 8 ? 9 ? 10 ? 11 ? 1 ?? 13 ? 14 ? 1 ?? ? 0pf 100 ? 00 1000 khz f refyosc refe ? en ? e os ? illato ? ope ? ating f ? equen ? y ? v * inte ? nal capa ? itan ? e =7 ? 8 ? 9 ? 10 ? 11 ? 1 ?? 13 ? 14 ? 1 ?? ? 0pf 100 ? 00 1000 khz 1rwh i ?(1??& n+] dgmxvw wkh .(q fdsdflwru wr pdnh wkh ?hqvru ?vfloodwru iuhtxhqf = 56 dmx h 5hhuhfh floodu lhudo fdsdflu pdh h 5hhuhfh floodu uhtxhf = touch key rc osc =1000khz symbol parameter test conditions min. typ. max. unit v dd condition i keyosc only senso ? (key) os ? illato ? ope ? ating cu ?? ent 3v *f senosc =1000khz 40 80 a ? v 80 1 ? 0 i refosc only refe ? en ? e os ? illato ? ope ? ating cu ?? ent 3v *f refosc =10 00khz ? m ntss=0 40 80 a ? v 80 1 ? 0 3v *f refosc =10 00khz ? m ntss=1 40 80 a ? v 80 1 ? 0 c keyosc senso ? (key) os ? illato ? exte ? nal capa ? itan ? e ? v *f senosc =1000khz ? 10 ? 0 pf c refosc refe ? en ? e os ? illato ? inte ? nal capa ? itan ? e ? v *f senosc =1000khz ? 10 ? 0 pf f keyosc senso ? (key) os ? illato ? ope ? ating f ? equen ? y ? v * exte ? nal capa ? itan ? e = 1 ??? 3 ? 4 ????? 7 ? 8 ? 9 ? 10 ? 11 ? 1 ?? 13 ? 14 ? 1 ?? ? 0pf 1 ? 0 1000 ?? 00 khz f refyosc refe ? en ? e os ? illato ? ope ? ating f ? equen ? y ? v * inte ? nal capa ? itan ? e = 1 ??? 3 ? 4 ????? 7 ? 8 ? 9 ? 10 ? 11 ? 1 ?? 13 ? 14 ? 1 ?? ? 0pf 1 ? 0 1000 ?? 00 khz 1rwh i ?(1??& = dmx h fdsdflu pdh h 6hu floodu uhtxhf 56 = dmx h 5hhuhfh floodu lhudo fdsdflu pdh h 5hhuhfh floodu uhtxhf
rev. 1.40 ?4 de?e??e? 0?? ?01? rev. 1.40 ?? de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver touch key rc osc=1500khz symbol parameter test conditions min. typ. max. unit v dd condition i keyosc only senso ? (key) os ? illato ? ope ? ating cu ?? ent 3v *f senosc = 1 ? 00khz ? 0 1 ? 0 a ? v 1 ? 0 ? 4 0 i refosc only refe ? en ? e os ? illato ? ope ? ating cu ?? ent 3v *f refosc = 1 ? 00khz ? m ntss=0 ? 0 1 ? 0 a ? v 1 ? 0 ? 4 0 3v *f refosc = 1 ? 00khz ? m ntss=1 ? 0 1 ? 0 a ? v 1 ? 0 ? 4 0 c keyosc senso ? (key) os ? illato ? exte ? nal capa ? itan ? e 3v *f senosc = 1 ? 00khz 4 8 1 ? pf ? v ? 10 ? 0 c refosc refe ? en ? e os ? illato ? inte ? nal capa ? itan ? e 3v *f senosc = 1 ? 00khz 4 8 1 ? pf ? v ? 10 ? 0 f keyosc senso ? (key) os ? illato ? ope ? ating f ? equen ? y 3v * exte ? nal capa ? itan ? e = 1 ??? 3 ? 4 ????? 7 ? 8 ? 9 ? 10 ? 11 ? 1 ?? 13 ? 14 ? 1 ?? ? 0pf 1 ? 0 1 ? 00 3000 khz ? v 1 ? 0 1 ? 00 3000 f refyosc refe ? en ? e os ? illato ? ope ? ating f ? equen ? y 3v * inte ? nal capa ? itan ? e = 1 ??? 3 ? 4 ????? 7 ? 8 ? 9 ? 10 ? 11 ? 1 ?? 13 ? 14 ? 1 ?? ? 0pf 1 ? 0 1 ? 00 3000 khz ? v 1 ? 0 1 ? 00 3000 1rwh i ?(1??& =15 dmx h fdsdflu pdh h 6hu floodu uhtxhf =15 56 = 15 dmx h 5hhuhfh floodu lhudo fdsdflu pdh h 5hhuhfh floodu uhtxhf =15 touch key rc osc=2000khz symbol parameter test conditions min. typ. max. unit v dd condition i keyosc only senso ? (key) os ? illato ? ope ? ating cu ?? ent 3v *f senosc = ? 0 00khz 80 1 ? 0 a ? v 1 ? 0 3 ? 0 i refosc only refe ? en ? e os ? illato ? ope ? ating cu ?? ent 3v *f refosc = ? 0 00khz ? m ntss=0 80 1 ? 0 a ? v 1 ? 0 3 ? 0 3v *f refosc = ? 0 00khz ? m ntss=1 80 1 ? 0 a ? v 1 ? 0 3 ? 0 c keyosc senso ? (key) os ? illato ? exte ? nal capa ? itan ? e 3v *f senosc = ? 0 00khz 4 8 1 ? pf ? v ? 10 ? 0 c refosc refe ? en ? e os ? illato ? inte ? nal capa ? itan ? e 3v *f senosc = ? 0 00khz 4 8 1 ? pf ? v ? 10 ? 0 f keyosc senso ? (key) os ? illato ? ope ? ating f ? equen ? y 3v * exte ? nal capa ? itan ? e = 1 ??? 3 ? 4 ????? 7 ? 8 ? 9 ? 10 ? 11 ? 1 ?? 13 ? 14 ? 1 ?? ? 0pf 1 ? 0 ? 0 00 4000 khz ? v 1 ? 0 ? 000 4000 f refyosc refe ? en ? e os ? illato ? ope ? ating f ? equen ? y 3v * inte ? nal capa ? itan ? e = 1 ??? 3 ? 4 ????? 7 ? 8 ? 9 ? 10 ? 11 ? 1 ?? 13 ? 14 ? 1 ?? ? 0pf 1 ? 0 ? 0 00 4000 khz ? v 1 ? 0 ? 000 4000 1rwh i ?(1??& = dmx h fdsdflu pdh h 6hu floodu uhtxhf 56 = dmx h 5hhuhfh floodu lhudo fdsdflu pdh h 5hhuhfh floodu uhtxhf
rev. 1.40 ?? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 ?7 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver a/d converter electrical characteristics ta= ?? c symbol parameter test conditions min. typ. max. unit v dd conditions av dd a/d conve ? te ? ope ? ating voltage ? .7 ? . ? v v adi a/d conve ? te ? input voltage 0 v ref v v ref a/d conve ? te ? refe ? en ? e voltage ? av dd v v bg bandgap refe ? en ? e with buffe ? voltage -3% 1.09 +3% v dnl diffe ? ential non-linea ? ity 3v v ref =av dd =v dd t adck =0. ? s ta= ?? c -3 +3 lsb ? v 3v v ref =av dd =v dd t adck =0. ? s ta= -40 c~8 ? c - ? + ? lsb ? v inl integ ? al non-linea ? ity 3v v ref =av dd =v dd t adck =0. ? s ta= ?? c -4 +4 lsb ? v 3v v ref =av dd =v dd t adck =0. ? s ta= -40 c~8 ? c -8 +8 lsb ? v i adc additional powe ? consu ? ption if a/d conve ? te ? is used 3v no load (t adck =0.5s ) 0.9 1.3 ? ? a ? v no load (t adck =0.5s ) 1. ? 1.8 ? a i bg additional powe ? consu ? ption if v bg refe ? en ? e with buffe ? is used ? 00 300 a t adck a/d conve ? te ? clo ? k pe ? iod 0. ? 10 s t adc a/d conve ? sion ti ? e (in ? lude sa ? ple and hold ti ? e) 1 ? -bit adc 1 ? t adck t ads a/d conve ? te ? sa ? pling ti ? e 4 t adck t on ? st a/d conve ? te ? on-to-sta ? t ti ? e ? s t bg v bg tu ? n-on sta ? le ti ? e ? 00 s
rev. 1.40 ?? de?e??e? 0?? ?01? rev. 1.40 ? 7 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver lcd electrical characteristics ta= ?? c symbol parameter test conditions min. typ. max. unit v dd conditions i bias v dd /3 ? ias cu ?? ent fo ? lcd ? v isel[1:0] = 00b ? .8 8.3 10.8 a isel[1:0] = 01b 11.7 1 ? .7 ? 1.7 isel[1:0] = 10b 3 ? ? 0 ?? isel[1:0] = 11b 70 100 130 v scom 1/3 ? ias lcd com output (1/3 v dd ) ? . ? v~ ? . ? v no load 0.317v dd (1/3)v dd 0.3 ? v dd v 1/3 ? ias lcd com output ( ? /3 v dd ) ? . ? v~ ? . ? v no load 0. ? 34 v dd ( ? /3) v dd 0.7v dd v v sseg 1/3 ? ias lcd seg output (1/3 v dd ) ? . ? v~ ? . ? v no load 0.317v dd (1/3)v dd 0.3 ? v dd v 1/3 ? ias lcd seg output ( ? /3 v dd ) ? . ? v~ ? . ? v no load 0. ? 34 v dd ( ? /3) v dd 0.7v dd v power-on reset characteristics symbol parameter test conditions min. typ. max. unit v dd conditions v por v dd sta ? t voltage to ensu ? e powe ? -on reset 100 ? v rr vdd v dd raising rate to ensu ? e powe ? -on reset 0.03 ? v/ ? s t por mini ? u ? ti ? e fo ? v dd stays at v por to ensu ? e powe ? -on reset 1 ? s
rev. 1.40 ? 8 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 ?9 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver system architecture a key factor in the high-performan ce features of the holtek range of microcontrollers is attributed to their internal system architecture. the range of devices take advantag e of the usual features found within risc microcontrollers providing increased speed of operation and periodic performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are ef fectively executed in one or two cycles for most of the standard or e xtended i nstructions re spectively, wi th t he e xception of br anch or c all i nstructions which need one moe cycle. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addresse d. the simple addressi ng methods of these registers along with additi onal architectural features ensure that a minimum of external components is required to provide a functional i/ o and a/ d control syst em wi th m aximum re liability a nd fe xibility. t his m akes t h ese device s suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either a lxt, hirc or lirc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way , one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructio ns takes place in consecutive instruction c ycles, t he pi pelining st ructure of t he m icrocontroller e nsures t hat i nstructions a re effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute.
? ? ? ? ? system clock and pipelining
rev. 1.40 ?8 de?e??e? 0?? ?01? rev. 1.40 ? 9 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle t o frst obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.
? ? ? ? ? ? ? ? ? ? instruction fetching program counter during pro gram e xecution, t he progr am co unter i s use d t o ke ep t rack of t he a ddress of t he next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non- consecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executi ng instructions re quiring jumps to non-consecutive addresses suc h as a jump instruction, a subrout ine c all, i nterrupt or re set, e tc., t he m icrocontroller m anages progra m c ontrol by loading the required address into the program counter . for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execut ion, is discarded and a dummy cycle takes its place while the correct instruction is obtained. device program counter program counter high byte pcl register bs8 ? b1 ? a-3 pc10~pc8 pcl7~pcl0 bs8 ? c1 ? a-3 pc11~pc8 bs8 ? d ? 0a-3 pc1 ? ~pc8 the lower byte of the program counter , known as the program counter low register or pcl, is available for program control and is a readable and writeable register . by transferring data directly into t his r egister, a sh ort p rogram j ump c an b e e xecuted d irectly, h owever, a s o nly t his l ow b yte is available for manipulation, the jum ps are limited to the present page of memory , that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch.
rev. 1.40 30 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 31 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer , and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but t he a cknowledge si gnal wi ll b e i nhibited. w hen t he st ack po inter i s d ecremented, b y r et o r reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily . however , when the stack is full, a call subroutine instruction can still be exec uted whic h wi ll result in a st ack overfow . prec autions should be ta ken to avoid such cases which might cause unpredictable program branching. if the stack is overfow , the frst program counter save in the stack will be lost.
device stack levels bs8 ? b1 ? a-3 ? bs8 ? c1 ? a-3 ? bs8 ? d ? 0a-3 8 arithmetic and logic unit C alu the arith metic-logic unit or alu is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. connected to the main micro controller data bus, the alu receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register . as these alu calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa, ladd, laddm, ladc, ladcm, lsub, lsubm, lsbc, lsbcm, ldaa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla, land, landm, lor, lorm, lxor, lxorm, lcpl, lcpla ? rotation : rra, rr, rrca, rrc, rla, rl, rlca, rlc, lrr, lrra, lrrca, lrrc, lrla, lrl, lrlca, lrlc ? increment and decrement : inca, inc, deca, dec, linca, linc, ldeca, ldec ? branch d ecision : jmp , sz , sz a, snz , si z, sdz , si za, sdz a, c all, r et, r eti, l snz, l sz, lsza, lsiz, lsiz, lsdz, lsdza
rev. 1.40 30 de?e??e? 0?? ?01? rev. 1.40 31 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver flash program memory the program memory is the location where the user code or program is stored. for this device series the program memory is flash type, which means it can be programmed and re-programmed a l arge num ber of t imes, a llowing t he use r t he c onvenience of c ode m odification on t he sa me device. by using the appropriate programming tools, these flash device s of fer users the fexibility to conveniently debug and develop their applications while also of fering a means of feld programming and updating. structure the program memory has a capacity of 2 k16 bits to 8 k16 bits. the program memory is addressed by the program counter and also contains data, tabl e informati on and interrupt entries. table data, which can be setup in any location within the program memory , is addressed by a separate table pointer register. device capacity bs8 ? b1 ? a-3 ? kx1 ? bs8 ? c1 ? a-3 4k1 ? bs8 ? d ? 0 a-3 8k1 ? 0000h 0004h 003ch 0fffh reset inte??upt ve?to? 1? ?its reset inte??upt ve?to? 1? ?its 1fffh bs8?c1?a-3 bs8?d?0a-3 reset inte??upt ve?to? 1? ?its 07ffh bs8?b1?a-3 program memory structure special vectors within the program memory , certai n locations are reserved for the reset and interrupts. the location 0 000h i s reserved for use by t he de vice re set for progra m i nitialisation. aft er a de vice re set i s initiated, the program will jump to this location and begin execution.
rev. 1.40 3 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 33 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. t o use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register , tblp and tbhp . these registers defne the total address of the look-up table. after setting up the table pointer pair , the table data can be retrieved from the program memory using t he tabrd[m] o r tabrdl[m] i nstructions respectively wh en t he m emory [ m] i s l ocated in data memory sector 0 . if the memory [m] is located in data memory other sectors, the data can be retrieved from the program memory using the ltabrd[m] or ltabrdl[m] instructions respectively. when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defned data memory register [m] as specifed in the instruction. the higher o rder t able d ata b yte f rom t he pr ogram me mory wi ll b e t ransferred t o t he t blh sp ecial register. the accompanying diagram illustrates the addressing data fow of the look-up table.

table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there usi ng t he org statement. t he va lue a t t his org st atement i s 0f 00h whi ch re fers t o t he start address of the last page within the 4 k words program memory of the bs86c16a-3 . the table pointer is setup here to have an initial value of 06h. this will ensure that the frst data read from the data table will be at the program memory address 0f 06h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the specifc page if the t abrd [m] ins truction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the t abrd [m] instruction is executed. because the tblh register is a read /write register and can be restored, care should be taken to ensure its protection if both the main routine and interrupt s ervice routine us e table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation.
rev. 1.40 3? de?e??e? 0?? ?01? rev. 1.40 33 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a mov a,0 f h ; initialise high table pointer mov tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer , ; data at program memory address f 06h transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer , ; data at program memory address f 05h transferred to tempreg2 and tblh ; in this example the data 1ah is transferred to tempreg1 and data 0fh to ; register tempreg2 : : org 0f 00h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : in circuit programming C icp the provision of flash type program memory provides the user with a means of convenient and easy upgrades a nd m odifcations t o t heir p rograms o n t he sa me d evice. as a n a dditional c onvenience, holtek has provided a means of programming the microcontroller in-circuit using a -pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller , and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. the holtek flash mcu to w riter programming pin correspondence table is as follows: holtek write pins mcu programming pins function icpda pa 0 se ? ial data/a dd ? ess input/output icpck pa ? se ? ial clo ? k input vdd vdd powe ? supply vss vss g ? ound the program memory and eeprom data memory can both be programmed serially in-circuit using this -wire inte rface. dat a is downloaded and upl oaded serial ly on a single pin wit h an additi onal line for t he c lock. t wo a dditional l ines a re re quired for t he powe r suppl y. t he t echnical de tails regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. during the programming process the p a0 and p a2 i/o pins for data and clock programming purposes. the user must there take care to ensure that no other outputs are connected to these two pins.
rev. 1.40 34 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 3? de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver
note: * may be resistor or capacitor . the resistance of * must be greate r than 1k or the capacitance of * must be less than 1nf. on-chip debug support C ocds there are three ev chips named bs86bv12a, bs86cv16a-3 and bs86dv20a-3, which are used t o e mulate t he b s86b12a-3, b s86c16a-3 a nd b s86d20a-3 d evices r espectively. e ach e v chip device also provide s an on-chip debug function to debug the corresponding mcu device during t he de velopment proc ess. t he e v c hip a nd t he a ctual mcu de vice a re a lmost func tionally compatible except for the on-chip debug function. users can use the ev chip device to emulate the real chip device behavior by connecting the ocdsda and ocdsck pins to the holtek ht - ide development tools. the ocdsda pin is the ocds data/address input/output pin while the ocdsck pin is the ocds clock input pin. when users use the ev chip for debugging, other functions which are shared with the ocdsda and ocdsck pins in the actual mcu device will have no e ffect i n t he e v c hip. howe ver, t he t wo ocds pi ns whi ch a re pi n-shared wi th t he icp programming pins are still used as the flash memory programming pins for icp. for a more detailed ocds description, refer to the corresponding document named holtek e-link for 8-bit mcu ocds users guide. holtek e-link pins ev chip pins pin description ocdsda ocdsda on- ? hip de ? ug suppo ? t data /add ? ess input/output ocdsck ocdsck on- ? hip de ? ug suppo ? t clo ? k input vdd vdd powe ? supply gnd vss g ? ound
rev. 1.40 34 de?e??e? 0?? ?01? rev. 1.40 3 ? de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver ram data memory the data memory is a volatile area of 8-bit wide ram internal mem ory and is the location where temporary information is stored. structure divided into two type s, the frst of these is an area of ram, known as the special function data memory. he re a re l ocated r egisters wh ich a re n ecessary f or c orrect o peration o f t he d evice. ma ny of these registers can be read from and written to directly under program control, however , some remain protected from user manipulation. the second area of data memory is known as the general purpose data memory , which is reserved for general purpose use. all locations within this area are read and write accessible under program control. the overall data memory is subdivided into several sectors for the devices . the special purpose data memory registers addressed from 00h~7fh in data memory are common and accessible in all sector s, with the exception of the eec register at address 40h which is only accessible in sector 1. switching betwee n the dif ferent data memory sector s is achieved by properly setting the memory pointers to the correct value. the start address of the data memory for all devices is the address 00h. device special puroise data memory general puroise data memory capacity sectors capacity sectors bs8 ? b1 ? a-3 384 8 se ? to ? 0~ ? : 00h~7fh (eec ? egiste ? at 40h only a ?? essi ? le in se ? to ? 1) 384 8 se ? to ? 0: 80h~ffh se ? to ? 1: 80h~ffh se ? to ? ? : 80h~ffh bs8 ? c1 ? a-3 ? 1 ? 8 se ? to ? 0~3: 00h~7fh (eec ? egiste ? at 40h only a ?? essi ? le in se ? to ? 1) ? 1 ? 8 se ? to ? 0: 80h~ffh se ? to ? 1 : 80h~ffh se ? to ? ? : 80h~ffh se ? to ? 3 : 80h~ffh bs8 ? d ? 0a-3 7 ? 8 8 se ? to ? 0 ~ ? : 00h~7fh (eec ? egiste ? at 40h only a ?? essi ? le in se ? to ? 1) 7 ? 8 8 se ? to ? 0: 80h~ffh se ? to ? 1 : 80h~ffh se ? to ? ? : 80h~ffh se ? to ? 3 : 80h~ffh se ? to ? 4 : 80h~ffh se ? to ? ? : 80h~ffh data memory sturcture spe?ial fun?tion data me?o?y gene?al pu?pose data me?o?y 00h 7fh 80h ffh 40h in se?to? 1 se?to? 0 se?to? 1 eec se?to? n n=? fo? bs8?b1?a-3; n=3 fo? bs8?c1?a-3; n=? fo? bs8?d?0a-3 data memory structure
rev. 1.40 3 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 37 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver data memory addressing for th ese device s that support the extended instructions, there is no bank pointer for data memory . for data memory the desired sector is pointed by the mp1h or mp2h register and the certain data memory address in the selected sector is specifed by the mp1l or mp2l register when using indirect addressing access. direct addressing can be used in all sectors using the corresponding instruction which can address all available data memory space. for the accessed data memory which is located in any data memory s ectors except s ector 0, the extended ins tructions can be us ed to acces s the data memory instead o f u sing t he i ndirect a ddressing a ccess. t he m ain d ifference b etween st andard i nstructions and extended instructions is that the data memory address m in the extended instructions can be composed of two bytes , the high byte indicates a sector and the low byte indicates a specifc address. general purpose data memory all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieve d for use later . it is this area of ram memory that is known as general purpose data memory . this area of data memory is fully accessible by the user programing for both reading and writing operations. by using the bit operation instructions individual bits can be set or reset under program control giving the user a lar ge range of fexibility for bit manipulation in the data memory. special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writeable but some are protected and are readable only , the details of which are located under the relevant special function register section. note that for locat ions that are unused, any read instruction to these addresses will return the value 00h.
rev. 1.40 3? de?e??e? 0?? ?01? rev. 1.40 37 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver 00h iar0 01h mp0 0?h iar1 03h mp1l 04h 0?h acc 0?h pcl 07h tblp 08h tblh 09h tbhp 0ah status 0bh 0ch ctrl 0dh pc 0eh 0fh 10h adcr1 11h acerl 1?h 19h intc1 18h intc0 1bh 1ah 1dh 1ch 1fh intc? intc3 13h 14h slcdc1 1?h slcdc? 1?h 17h : unused? ?ead as 00h tmpc ?0h ?1h ??h ?9h ?8h ?bh ?ah ?dh ?ch ?fh ?eh ?3h ?4h ??h ??h ?7h 40h 41h 4?h 43h 44h 4?h 4?h 47h 48h 49h 4ah 4bh 4ch 4dh 4eh 4fh ?0h ?1h ??h ?3h ?4h lvdc 1eh slcdc0 eec se?to? 0~? se?to? 0? ? se?to? 1 ??h ??h ?0h ?1h ??h ?3h ?4h ??h ??h ?7h ?8h ?9h ?ah ?bh ?ch ?dh ?eh ?fh 70h 30h 31h 3?h 38h 3ch 33h 34h 3?h 3?h 37h 3bh 39h 3ah 71h 7?h 73h 74h 7?h 7?h 77h pawu pac papu 3dh 3fh 3eh 7fh mp1h iar? mp?l mp?h pcc adcr0 ?7h ?8h ?9h ?ah ?bh ?ch ?dh ?eh ?fh smod tbc sledc1 wdtc eed eea simtoc pbc pbpu simc?/sima simc1 simd ucr? brg pcpu 78h 79h 7ah 7bh 7ch 7dh 7eh integ pa sledc0 pscr pb simc0 usr ucr1 txr_rxr adrl adrh ifs tktmr tkc0 tk1?dl tk1?dh tkc1 tkm01?dl tkm01?dh tkm0rol tkm0roh tkm0c0 tkm0c1 tkm11?dl tkm11?dh tkm1rol tkm1roh tkm1c0 tkm1c1 tkm?1?dl tkm?1?dh tkm?rol tkm?roh tkm?c0 tkm?c1 ctm0c0 ctm0c1 ctm0dl ctm0dh ctm0al ctm0ah ptm1c0 ptm1c1 ptm1dl ptm1dh ptm1al ptm1ah ptm1rpl ptm1rph ptm?c0 ptm?c1 ptm?dl ptm?dh ptm?al ptm?ah ptm?rpl ptm?rph bs86b12a-3 special purpose data memory
rev. 1.40 38 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 39 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver 00h iar0 01h mp0 0?h iar1 03h mp1l 04h 0?h acc 0?h pcl 07h tblp 08h tblh 09h tbhp 0ah status 0bh 0ch ctrl 0dh pc 0eh 0fh 10h adcr1 11h acerl 1?h 19h intc1 18h intc0 1bh 1ah 1dh 1ch 1fh intc? intc3 13h 14h slcdc1 1?h slcdc? 1?h 17h : unused? ?ead as 00h tmpc slcdc3 ?0h ?1h ??h ?9h ?8h ?bh ?ah ?dh ?ch ?fh ?eh ?3h ?4h ??h ??h ?7h 40h 41h 4?h 43h 44h 4?h 4?h 47h 48h 49h 4ah 4bh 4ch 4dh 4eh 4fh ?0h ?1h ??h ?3h ?4h lvdc 1eh slcdc0 eec se?to? 0~3 se?to? 0? ?? 3 se?to? 1 ??h ??h ?0h ?1h ??h ?3h ?4h ??h ??h ?7h ?8h ?9h ?ah ?bh ?ch ?dh ?eh ?fh 70h 30h 31h 3?h 38h 3ch 33h 34h 3?h 3?h 37h 3bh 39h 3ah 71h 7?h 73h 74h 7?h 7?h 77h pawu pac papu 3dh 3fh 3eh 7fh mp1h iar? mp?l mp?h pcc adcr0 ?7h ?8h ?9h ?ah ?bh ?ch ?dh ?eh ?fh smod tbc sledc1 wdtc eed eea simtoc pbc pbpu simc?/sima simc1 simd ucr? brg pcpu 78h 79h 7ah 7bh 7ch 7dh 7eh integ pa sledc0 pscr pb simc0 usr ucr1 txr_rxr adrl adrh pd pdc pdpu tktmr tkc0 tk1?dl tk1?dh tkc1 tkm01?dl tkm01?dh tkm0rol tkm0roh tkm0c0 tkm0c1 tkm11?dl tkm11?dh tkm1rol tkm1roh tkm1c0 tkm1c1 tkm?1?dl tkm?1?dh tkm?rol tkm?roh tkm?c0 tkm?c1 tkm31?dl tkm31?dh tkm3rol tkm3roh tkm3c0 tkm3c1 ctm0c0 ctm0c1 ctm0dl ctm0dh ctm0al ctm0ah ptm1c0 ptm1c1 ptm1dl ptm1dh ptm1al ptm1ah ptm1rpl ptm1rph ptm?c0 ptm?c1 ptm?dl ptm?dh ptm?al ptm?ah ptm?rpl ptm?rph bs86c16a-3 special purpose data memory
rev. 1.40 38 de?e??e? 0?? ?01? rev. 1.40 39 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver 00h iar0 01h mp0 0?h iar1 03h mp1l 04h 0?h acc 0?h pcl 07h tblp 08h tblh 09h tbhp 0ah status 0bh 0ch ctrl 0dh pc 0eh 0fh 10h adcr1 11h acerl 1?h 19h intc1 18h intc0 1bh 1ah 1dh 1ch 1fh intc? intc3 13h 14h slcdc1 1?h slcdc? 1?h 17h : unused? ?ead as 00h tmpc slcdc3 ?0h ?1h ??h ?9h ?8h ?bh ?ah ?dh ?ch ?fh ?eh ?3h ?4h ??h ??h ?7h 40h 41h 4?h 43h 44h 4?h 4?h 47h 48h 49h 4ah 4bh 4ch 4dh 4eh 4fh ?0h ?1h ??h ?3h ?4h lvdc 1eh slcdc0 eec se?to? 0~? se?to? 0? ?~? se?to? 1 ??h ??h ?0h ?1h ??h ?3h ?4h ??h ??h ?7h ?8h ?9h ?ah ?bh ?ch ?dh ?eh ?fh 70h 30h 31h 3?h 38h 3ch 33h 34h 3?h 3?h 37h 3bh 39h 3ah 71h 7?h 73h 74h 7?h 7?h 77h pawu pac papu 3dh 3fh 3eh 7fh mp1h iar? mp?l mp?h pcc adcr0 ?7h ?8h ?9h ?ah ?bh ?ch ?dh ?eh ?fh smod tbc sledc1 wdtc eed eea simtoc pbc pbpu simc?/sima simc1 simd ucr? brg pcpu 78h 79h 7ah 7bh 7ch 7dh 7eh integ pa sledc0 pscr pb simc0 usr ucr1 txr_rxr adrl adrh pd pdc pdpu tktmr tkc0 tk1?dl tk1?dh tkc1 tkm01?dl tkm01?dh tkm0rol tkm0roh tkm0c0 tkm0c1 tkm11?dl tkm11?dh tkm1rol tkm1roh tkm1c0 tkm1c1 tkm?1?dl tkm?1?dh tkm?rol tkm?roh tkm?c0 tkm?c1 tkm31?dl tkm31?dh tkm3rol tkm3roh tkm3c0 tkm3c1 ctm0c0 ctm0c1 ctm0dl ctm0dh ctm0al ctm0ah ptm1c0 ptm1c1 ptm1dl ptm1dh ptm1al ptm1ah ptm1rpl ptm1rph tkm41?dl tkm41?dh tkm4rol tkm4roh tkm4c0 tkm4c1 ptm?c0 ptm?c1 ptm?dl ptm?dh ptm?al ptm?ah ptm?rpl ptm?rph BS86D20A-3 special purpose data memory
rev. 1.40 40 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 41 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver special function register description most of the special function register details will be described in the relevant functional section, however several registers require a separate description in this section. indirect addressing registers C iar0, iar1, iar2 the indirect addressing registers, iar0 , iar1 and iar 2 , although having their locations in normal ram r egister sp ace, d o n ot a ctually p hysically e xist a s n ormal r egisters. t he m ethod o f i ndirect addressing for ram da ta m anipulation use s t hese indi rect addre ssing re gisters a nd me mory pointers, i n c ontrast t o di rect m emory a ddressing, where t he a ctual m emory a ddress i s spe cifed. actions on t he iar0 , iar1 a nd iar 2 re gisters wi ll re sult i n no a ctual re ad or writ e ope ration t o these registers but rather to the memory location specifed by their corresponding memory pointers, mp0 , mp1l/mp1h or mp 2l/mp2h . acting as a pair , iar0 and mp0 can together access data from sector 0 while the iar1 register together with mp1l/mp1h register pair and iar2 register together with mp2l/mp2h register pair can access data from any sector. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers directly will return a result of 00h and writing to the registers directly will result in no operation. memory pointers C mp0, mp1l/mp1h, mp2l/mp2h five me mory po inters, k nown a s mp0 , mp1 l, mp1 h, mp2 l a nd mp 2h a re p rovided. t hese memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to is the address specifed by the related memory pointer . mp0, together with indirect addressing register, iar0, are used to access data from sector 0, while mp1 l/ mp1h together with iar1 and mp2l/mp2h together with iar2 are used to access data from all sector s according to the corresponding mp1h or mp2h register . direct addressing can be used in all sector s using the correspongding instruction which can address all available data memory space . the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example example 1 data .section data adres1 d b adres2 d b adres3 d b adres4 d b block d b code .section at 0 code org00h start : m ov a , 04h setup size of block m ov block , a m ov a , offset adres1 ; accumulator loaded with frst ram address a ; setup memory pointer with frst ram address c lr iar0 ; clear the data at address defned by mp0
rev. 1.40 40 de?e??e? 0?? ?01? rev. 1.40 41 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver ? example 2 data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: m ov a,04h ; setup size of block m ov block,a m ov a,01h ; setup the memory sector m ov mp1h,a dhdh ffddhlk50dh d hhlhlk50dh loop: f ,5 1 fhdkhddddhhhe03 l f lfhhhlh03 s dz block ; check if last memory location has been cleared j mp loop continue: : the important point to note here is that in the example shown above, no reference is made to specifc data memory addresses. direct addressing program example using extended instructions data .section data temp db ? code .section at 0 code org 00h start: lmov a ,[m] ; move [m] data to acc lsub a , [m+1] ; compare [m] and [m+1] data snz c ; [m]>[m+1]? jmp continue ; no lmov a ,[m] ; yes, exchange [m] and [m+1] data mov temp,a lmov a,[m+1] lmov [m],a mov a,temp lmov [m+1],a continue: : note: here m is a data memory address located in any data memory sectors. for example, m=1f0h, it indicates address 0f0h in sector 1.
rev. 1.40 4 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 43 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver accumulator C acc the a ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. w ithout the accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he da ta me mory resulting i n highe r program ming and t iming overheads. da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he ac cumulator; for e xample, whe n t ransferring da ta be tween one user - defined register and another , it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory . by manipulating this register , direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tbhp, tblh these three special function registers are used to cont rol operation of the look-up table which is stored i n t he progra m me mory. t blp a nd t bhp a re t he t able poi nter s a nd i ndicate t he l ocation where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored afte r a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location. status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), sc fag, cz fag, power down fag (pdf), and watchdog time-out fag (t o). these arithmetic/ logical o peration a nd sy stem m anagement fa gs a re u sed t o r ecord t he st atus a nd o peration o f t he microcontroller. with the exception of the to and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the t o or pdf fag. in addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. the t o fag can be af fected only by a system power -up, a wdt time-out or by executing the clr wdt or hal t instruction. the pdf fag is af fected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac , c sc and cz fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared.
rev. 1.40 4? de?e??e? 0?? ?01? rev. 1.40 43 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver ? pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. ? to is cleared by a system power-up or executing the clr wdt or halt instruction. t o is set by a wdt time-out. ? sc is the result of the xor operation which is performed by the ov fag and the msb of the current instruction operation result. ? cz is the operational result of different fags for different instructions. refer to register defnitions for more details. in additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. status register bit 7 6 5 4 3 2 1 0 na ? e sc cz to pdf ov z ac c r/w r r r r r/w r/w r/w r/w por x x 0 0 x x x x x unknown bit 7 sc : the result of the xor operation which is performed by the ov fag and the msb of the instruction operation result. bit 6 cz : the the operational result of different fags for different instuctions. for sub/subm/lsub/lsubm instructions, the cz fag is equal to the z fag. for sbc/sbcm/lsbc/lsbcm instructions, the cz flag is the and operation result which is performed by the previous operation cz fag and current operation zero fag. for other instructions, the cz fag willl not be affected. b it 5 to : w atchdog t ime-out fag 0: after power up or executing the clr wdt or halt instruction 1: a watchdog time-out occurred. b it 4 pdf : power down fag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction b it 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. b it 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero b it 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction b it 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction.
rev. 1.40 44 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 4? de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver eeprom data memory t he device s contain an area of internal eeprom data memory . eeprom, which stands for electrically erasable programmable read only memory , is by its nature a non-volatile form of memory, with data retention even when its power supply is removed. by incorporating this kind of d ata m emory, a wh ole n ew h ost o f a pplication p ossibilities a re m ade a vailable t o t he d esigner. the a vailability o f e eprom st orage a llows i nformation su ch a s p roduct i dentifcation n umbers, calibration values , s pecifc us er data, s ystem s etup data or other product information to be s tored directly within the product microcontroller . the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eeprom data memory capacity is 648 bits. unlike the program memory and ram data memory, the eeprom data memory is not directly mapped and is therefore not directly accessible in the same w ay as the other types of memory . read and w rite operations to the eep rom are carried o ut i n single b yte o perations u sing a n a ddress a nd d ata r egister i n sector 0 a nd a si ngle control register in sector 1. device capacity address bs8 ? b1 ? a-3 ? 48 00h~3fh bs8 ? c1 ? a-3 bs8 ? d ? 0a-3 eeprom registers three registers control the overall operation of the internal eeprom data memory . these are the address register , eea, the data register , eed and a single control register , eec. as both the eea and eed registers are located in sector 0, they can be directly accessed in the same way as any other special function register . the eec register however , being located in sector 1, cannot be directly addressed directly and can only be read from or written to indirectly using the mp1 h/mp1l or mp2h/mp2l memory pointer and indirect addressing register , iar1 or iar2 . because the eec control register is located at address 40h in sector 1, the memory pointer low byte register , mp1l or mp2l, must frst be set to the value 40h and the memory pointer high byte register , mp1h or mp2h , set to the value, 01h, before any operations on the eec register are executed. eeprom control registers list name bit 7 6 5 4 3 2 1 0 eea d ? d4 d3 d ? d1 d0 eed d7 d ? d ? d4 d3 d ? d1 d0 eec wren wr rden rd eea register bit 7 6 5 4 3 2 1 0 na ? e d ? d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 b it 7 ~ 6 unimplemented, read as 0 b it 5 ~ 0 data eeprom address data eeprom address bit 5 ~ bit 0
rev. 1.40 44 de?e??e? 0?? ?01? rev. 1.40 4 ? de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver eed register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d ? d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 0 data eeprom data data eeprom data bit 7 ~ bit 0 eec register bit 7 6 5 4 3 2 1 0 na ? e wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 b it 7 ~ 4 unimplemented, read as 0 b it 3 wren : data eeprom w rite enable 0: disable 1: enable this is the d ata eep rom w rite enable bit w hich mus t be s et high before d ata eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. b it 2 wr : eeprom w rite control 0: w rite cycle has fnished 1: activate a write cycle this i s t he da ta e eprom w rite c ontrol b it a nd wh en se t h igh b y t he a pplication program will activate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no ef fect if the wren has not frst been set high. b it 1 rden : data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero will inhibit data eeprom read operations. b it 0 rd : eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set high by the applic ation program will activate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no ef fect if the rden has not frst been set high. note: the wren, wr, rden and rd can not be set to 1 at the same time in one instruction. the wr and rd can not be set to 1 at the same time.
rev. 1.40 4 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 47 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver reading data from the eeprom to read data from the eeprom, the read enable bit, rden, in the eec register must frst be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea registe r. if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle term inates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register . the data will remain in the eed register until another read or write operation is executed. the application program can poll the rd bit to determine when the data is valid for reading. writing data to the eeprom to write data to the eeprom, the eeprom address of the data to be written must frst be placed in the eea register and the data placed in the eed register . then the write enable bit, wren, in the eec register must first be set high to enable the write function. after this, the wr bit in the e ec r egister m ust b e i mmediately se t h igh t o i nitial a wr ite c ycle. t hese t wo i nstructions must be executed consecutively . the global interrupt bit emi should also frst be cleared before implementing any write operations, and then set again after the write cycle has started. note that s etting t he w r bi t hi gh wi ll not i nitiate a wr ite c ycle i f t he w ren bi t ha s not be en se t. as t he eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fnished can be implemented either by polling the wr bit in the eec register or by using the eeprom interrupt. when the write cycle terminates, the wr bit will be automatically cleared to zero by the microcontroller , informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent write operation is provided in several ways. after the device is powered-on t he w rite e nable bi t i n t he c ontrol re gister wi ll be c leared pre venting a ny wri te operations. also at power -on the memory pointer high byte register , mp1h or mp2h , will be reset to zero, which means that data memory sector 0 will be selected. as the eeprom control register is located in sector 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the w rite enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt m ust frst be enable d by set ting the dee bit in the rele vant int errupt regist er. when an eeprom write cycle ends, the def request flag will be set. if the global and eeprom write interrupts is enabled and the stack is not full, a jump to the associated interrupt vector will take place. when the interrupt is serviced, the eeprom interrupt fag will be automatically reset.
rev. 1.40 4? de?e??e? 0?? ?01? rev. 1.40 47 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be enhanced by ensuring that the w rite enable bit is normally cleared to zero when not writing. also the memory po inter hi gh byt e re gister could be norm ally c leared t o z ero a s t his woul d i nhibit access to sector 1 where the eeprom control register exist. although certainly not necessary , consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly . the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. note that the devices should not enter the idle or sleep mode until the eeprom read or write operation is totally completed. otherwise, the eeprom read or write operation will fail. programming examples reading data from the eeprom C polling method mov a, eeprom_adres ; user defned address mov eea, a mov a, 040h ; setup memory pointer low byte mp1l mov mp1l, a ; mp1l points to eec register mov a, 01h ; setup memory pointer high byte mp1h mov mp1h, a set iar1.1 ; set rden bit, enable read operations set iar1.0 ; start read cycle - set rd bit back: sz iar1.0 ; check for read cycle end jmp back clr iar1 ; disable eeprom read/write clr mp1h mov a, eed ; move read data to register mov read_data, a writing data to the eeprom - polling method mov a, eeprom_adres ; user defned address mov eea, a mov a, eeprom_data ; user defned data mov eed, a mov a, 040h ; setup memory pointer low byte mp1l mov mp1l, a ; mp1l points to eec register mov a, 01h ; setup memory pointer high byte mp1h mov mp1h, a clr emi set iar1.3 ; set wren bit, enable write operations set iar1.2 ; start write cycle - set wr bit C executed immediately after ; set wren bit set emi back: sz iar1.2 ; check for write cycle end jmp back clr iar1 ; disable eeprom read/write clr mp1h
rev. 1.40 48 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 49 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver oscillators various osc illator opti ons of fer t he use r a wi de ra nge of funct ions a ccording t o t heir va rious application r equirements. t he f lexible f eatures o f t he o scillator f unctions e nsure t hat t he b est optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of confguration options and registers. oscillator overview all the devices include two internal oscillators and some devices also include an external oscillator . in addition to being the source of the main system clock the oscillators also provide clock sources for the watchdog t imer , t ime base s and tms . external oscillator requiring some external components as well as f ully integrated internal oscillators requiring no external components, are provided to form a wide range of both fast and slow system oscillators. for the bs86c16a-3 and BS86D20A-3 devices, the low speed oscillators are selected through the confguration option. the higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power re quirements, whi le t he op posite i s of c ourse t rue fo r t he l ower fre quency osc illators. w ith the capability of dynamically switching between fast and slow system clock, the device s ha ve the fexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. device type name freq. pins all th ? ee devi ? es inte ? nal high speed rc hirc 8/1 ? /1 ? mhz inte ? nal low speed rc lirc 3 ? khz bs8 ? c1 ? a-3/bs8 ? d ? 0a-3 exte ? nal low speed c ? ystal lxt 3 ? 7 ? 8hz xt1/xt ? oscillator types 6vwhp&orfn&rjxudwlrv there are three methods of generating the system clock, a high speed oscillator and two low speed oscillator s . the high speed oscillator is the internal 8mhz, 1 2mhz, 16 mhz rc oscillator . the two low spe ed osc illator s are t he i nternal 32 khz oscillator , l irc, a nd t he e xternal 32 .768khz c rystal oscillator, lxt . selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and cks2 ~ cks0 bits in the smod register and as the system clock can be dynamically selected. the a ctual sou rce c lock use d fo r t he l ow spe ed o scillator c omes fr om t he l irc osc illator o r i s chosen via confguration option depending on the selected device. the frequency of the slow speed or high speed system clock is also determined using the hlclk bit and cks2 ~ cks0 bits in the smod register . note that two oscillator selections must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no-oscillator selection for either the high or low speed oscillator. internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc os cillator has a pow er on default frequency of 8 m hz but can be s elected to be either 8mhz, 12mhz or 16mhz via a confguration option and the hircs1 and hircs0 bits in the ctrl register . device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised.
rev. 1.40 48 de?e??e? 0?? ?01? rev. 1.40 49 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver
? ?? ? ? ? ? ? - ? ? ? ? ? ? ? note: for the bs86b12a-3 device, f sub is directly sourced from the lirc oscillator without confguration option. system clock confgurations internal 32khz oscillator C lirc the internal 32khz system oscillat or is one of the low frequency oscillator s . it is a fully integrated rc osc illator wi th a t ypical fre quency of 32khz a t 5v , re quiring no e xternal c omponents for i ts implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. external 32.768khz crystal oscillator C lxt for the bs86c16a-3 and BS86D20A-3 devices, the external 32.768khz crystal system oscillator is one of t he l ow fre quency osc illator c hoices, whi ch i s sel ected vi a c onfiguration opt ion. t his clock source has a fxed frequency of 32.768khz and requires a 32.768khz crystal to be connected between pi ns xt 1 a nd xt 2. t he e xternal re sistor a nd c apacitor c omponents c onnected t o t he 32.768khz crystal are necessary to provide oscillation. for applications where precise frequencies are essential, these components may be required to provide frequency compensation due to dif ferent crystal m anufacturing t olerances. duri ng po wer-up t here i s a t ime de lay a ssociated wi th t he l xt oscillator waiting for it to start-up. when the microco ntroller enters the sleep or idle mode, the system clock is switched of f to stop microcontroller a ctivity a nd t o c onserve powe r. howe ver, i n m any m icrocontroller a pplications it may be necessary to keep the internal timers operational even when the microcontroller is in the sleep or idle mode. t o do this, another clock, independent of the system clock, must be provided. however, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer specification. the external parallel feedback resistor, rp, is required.
rev. 1.40 ? 0 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 ?1 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver the confguration option determine s if the xt1/xt2 pins are used for the lxt oscillator or as i/o pins or other pin-shared functions . ? if the lxt oscillator is not used for any clock source, the xt1/xt2 pins can be used as normal i/ o pins or other pin-shared functions . ? if the lxt oscillator is used for any clock source, the 32.768khz crystal should be connected to the xt1/xt2 pins. for osci llator st ability and t o minimize t he ef fects of noise and crosst alk, i t i s i mportant t o ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the mcu as possible.
? ? ? ? ? ?- ? ? ? external lxt oscillator lxt oscillator c1 and c2 values crystal frequency c1 c2 3 ? .7 ? 8khz 10pf 10pf note: 1. c1 and c ? values a ? e fo ? guidan ? e only. ? . r p = ? m ~100 is ? e ? o ?? ended. 32.768khz crystal recommended capacitor values lxt oscillator low power function the lxt oscillator can function in one of two modes, the quick start mode and the low power mode. the mode selection is executed using the lxtlp bit in the ctrl register. lxtlp bit lxt mode 0 qui ? k sta ? t 1 low-powe ? after pow er on , the lx tlp bit w ill be automatically cleared to zero ens uring that the lx t oscillator is in the quick start operating mode. in the quick start mode the lxt oscillator will power up a nd st abilise q uickly. ho wever, a fter t he l xt o scillator h as fu lly po wered u p i t c an be placed into the low-power mode by setting the lxtlp bit high. the oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the lxt oscillator start-up. in power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the lxtlp bit high about 2 seconds after power-on. it should be noted that, no matter what condition the lxtlp bit is set to, the lxt oscillator will always function normally , the only dif ference is that it will take more time to start up if in the low- power mode.
rev. 1.40 ?0 de?e??e? 0?? ?01? rev. 1.40 ? 1 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver operating modes and system clocks present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conficting requirements that are especially true i n ba ttery powe red por table a pplications. t he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce-versa, l ower spe ed c locks re duce current consumption. as holtek has provided these device s with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the main system clock, can come from either a high frequency , f h , or low frequency , f sub , source, and is selected using the hlclk bit and cks2~cks0 bits in the smod register . the high speed system clock is s ourced from the h irc os cillator . the low s peed s ystem clock s ource can be sourced from internal clock f sub . if f sub is selected then it can be sourced by either the lxt or lirc oscillators, selected via a confguration option. the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64.

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? ?- ? ? ? ? ?? ? ? ? ? ? ? ? ?? ??? ? ? ? ? ? ? ? ? ?? ???? ? ? ? ? ? ?? ? ? ? ? 6\vwhp&orfn&rq?jxudwlrqv note: for the bs86b12a-3 device, f sub is directly sourced from the lirc oscillator without confguration option. when the system clock source f sys is switched to f sub from f h , the high speed osc illation wi ll st op t o c onserve t he powe r. t hus t here i s no f h ~f h /64 for pe ripheral circuit to use.
rev. 1.40 ?? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 ?3 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver system operation modes there a re five d ifferent m odes o f o peration f or t he m icrocontroller, e ach o ne wi th i ts o wn special characteristics and which can be chosen according to the specific performance and power requirements of the appl ication. there are two modes all owing normal operati on of the microcontroller, the normal mode and slow mode. the remaining three modes, the sleep , idle0 and idle1 mode are used when the microcontroller cpu is switched off to conserve power. operating mode description cpu f sys f sub normal ? ode on f h ~f h / ? 4 on slow ? ode on f sub on ilde0 ? ode off off on idle1 ? ode off on on sleep ? ode off off off normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by the high speed oscillator . this mode operates allo wing the microco ntroller to operate normally with a clock source will come from the high speed oscillator , hirc. the high speed oscillator will however frst be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod regis ter. a lthough a high s peed os cillator is us ed, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller operates normally altho ugh now with a slower speed clock so urce. t he c lock so urce u sed wi ll b e f rom f sub . r unning t he m icrocontroller i n t his m ode allows it to run with much lower operating currents. in the slow mode, the f h is off. sleep mode the sl eep mo de i s e ntered wh en a n hal t i nstruction i s e xecuted a nd wh en t he i dlen b it i n the smod register is low . in the sleep mode the cpu will be stopped , and the f sub clock will be stopped too, the w atchdog t imer function is disabled. idle0 mode the idle0 mode is entered when a hal t instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the ctrl register is low . in the idle0 mode the system oscillator will be stop and will therefore be inhibited from driving the cpu. idle1 mode the idle1 mode is entered when a hal t instruction is executed and when the idlen bit in the smod registe r is high and the fsyson bit in the ctrl register is high. in the idle1 mode the s ystem os cillator w ill be inhibited from driving the cp u but may continue to provide a clock source to keep some peripheral functions operational. in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be the high speed or low speed system oscillator.
rev. 1.40 ?? de?e??e? 0?? ?01? rev. 1.40 ? 3 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver control register the smod register is used to control the internal clocks within the device s. smod register bit 7 6 5 4 3 2 1 0 na ? e cks ? cks1 cks0 lto hto idlen hlclk r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 1 1 b it 7 ~ 5 cks2 ~ cks0 : the system clock selection when hlclk is 0 000: f sub (lirc or lxt) 001: f sub (lirc or lxt) 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these t hree b its a re u sed t o se lect wh ich c lock i s u sed a s t he sy stem c lock so urce. i n addition t o t he sy stem c lock so urce, wh ich c an b e either t he l xt o r lirc, a d ivided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 unimplemented, read as 0. b it 3 lto : low speed s ystem oscillator ready fag 0: not ready 1: ready this is the low speed system oscilla tor ready fag which indicates when the low speed system oscillator is stable after pow er on reset or a wake-up has occurred. the fag will be low when in the sleep mode but after a wake-up has occurred, the fag will change to a high level after 1024 clock cycles if lxt oscillator is used and 1~2 clock cycles if the lirc oscillator is used. b it 2 hto : h igh speed system oscillator ready fag 0: not ready 1: ready this i s t he hi gh spe ed syst em osc illator re ady fl ag whi ch i ndicates whe n t he hi gh speed system oscillator is stable after a wake-up has occurred. this fag is cleared to zero by hardware when the device is powered on and then changes to a high level after the h igh sp eed sy stem o scillator i s stable. t herefore t his fag wi ll a lways b e r ead a s 1 by the application program after device power -on. the fag will be low when in the sleep or idle 0 mode but after power on reset or a wake-up has occurred, the fag will change to a high level after 15~16 clock cycles if the hirc oscillator is used. b it 1 idlen : idle mode control 0: disable 1: enable this i s t he idl e mo de cont rol bi t a nd de termines wha t ha ppens wh en t he hal t instruction is executed. if this bit is high, when a hal t instruction is executed the device wi ll e nter t he idle mo de. i n t he i dle1 mo de t he c pu wi ll st op r unning but t he syst em c lock wi ll c ontinue t o keep t he pe ripheral fun ctions ope rational, i f fsyson bit is high. if fsyson bit is low , the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a halt instruction is executed. b it 0 hlclk : system clock selection 0: f h /2 ~ f h /64 or f sub 1: f h this bit is used to select if the f h clock or the f h /2 ~ f h /64 or f sub cloc k is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2 ~ f h /64 or f sub clock will be selected. when system clock switches from the f h clock to the f sub clock and the f h clock will be automatically switched off to conserve power.
rev. 1.40 ? 4 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 ?? de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver ctrl register bit 7 6 5 4 3 2 1 0 na ? e fsyson hircs1 hircs0 lxtlp lvrf d1 wrf r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 x 0 0 x unknown b it 7 fsyson : f sys control in idle mode 0: disable 1: enable bit 6 unimplemented, read as 0. bit 5 ~ 4 hircs1~hircs0 : hirc frequency clock select 0 0: 8mhz 01 : 12 mhz 10: 16 mhz 11: 8 mhz it is recommended that the hirc frequency selected by these two bits is the same with the frequency determined by the confguration option to keep the hirc frequency accuracy specifed in the a.c. characteristics. bit 3 lxtlp : lxt low power control 0: quick start mode 1: low power mode this bit is only available for the bs86c16a-3 and BS86D20A-3 devices. b it 2 lvrf : lvr function reset fag describe elsewhere b it 1 undefned bit this bit can be read or written by user application program. b it 0 wrf : wdt control register software reset fag describe elsewhere operating mode switching the d evice s c an swi tch b etween o perating m odes d ynamically a llowing t he u ser t o se lect t he b est performance/power ratio for the pres ent task in hand. in this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the hal t instruction . when a hal t instructio n is executed, whether the device s enter the idle mode or the sleep mode is determined by the condition of the idlen bit in the smod register and fsyson in the ctrl register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h , to the clock source, f h /2~f h /64 or f sub . if the clock is from the f sub , the high speed clock source will stop running to conserve power . when this happens it must be noted that the f h /16 and f h /64 internal clock sources will also stop running . the accompanying fowchart shows what happens when the device s move between the various operating modes.
rev. 1.40 ?4 de?e??e? 0?? ?01? rev. 1.40 ?? de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver
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?? ? normal mode to slow mode switching when r unning i n t he nor mal mo de, wh ich u ses t he h igh sp eed sy stem o scillator, a nd t herefore consumes more power , the system clock can switch to run in the slow mode by clearing the hlclk bit to zero and set ting the cks2~cks0 bits to 000 or 001 in the smod register .this will then use the low speed system oscillator which will consume less power . users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the sl ow mo de i s so urced f rom t he lxt o r lirc o scillator s a nd t herefore r equires these oscillator s to be stable before full mode switching occurs. this is monitored using the lto bit in the smod register.
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rev. 1.40 ?? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 ?7 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver slow mode to normal mode switching in slow mode the system uses either the lxt or lirc low speed system oscillator . t o switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be set high or hlclk bit is low , but cks2~cks0 is set to 010, 01 1, 100, 101, 1 10 or 111. as a c ertain a mount of t ime wil l be re quired for t he hi gh fre quency c lock t o sta bilise, t he status o f t he ht o b it i s c hecked. t he a mount o f t ime re quired fo r h igh spe ed syst em o scillator stabilization is 15~16 clock cycles .
? ? ?? ???? ? ? ? ? ?? ???? ? ? ? ? ?? ???? entering the sleep mode there is only one way for the device s to enter the sleep mode and that is to execute the hal t instruction in the application program with the idlen bit in smod register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and the f sub clock will be stopped and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and stop counting. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared.
rev. 1.40 ?? de?e??e? 0?? ?01? rev. 1.40 ? 7 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver entering the idle0 mode there is only one way for the devic es to enter the idle0 mode and that is to execute the hal t instruction in the application program with the idlen bit in smod register equal to 1 and the fsyson bit in ctrl register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the halt instruc - tion, but the low frequency f sub clock will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. entering the idle1 mode there is only one way for the devic e s to enter the idle1 mode and that is to execute the hal t instruction in the application program with the idlen bit in smod register equal to 1 and the fsyson bit in ctrl register equal to 1. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and the low frequency f sub will be on and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting . ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device s to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode, there are other considerations which must also be taken into account by the circuit de signer i f t he powe r c onsumption i s t o be m inimised. spe cial a ttention m ust be m ade t o the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any floating input pins could create internal oscillations and result in increased current consumpti on. this also applies to devices which have dif ferent package types, as there may be unbonbed pins. these must eit her be set up as out puts or if setup as inputs must have pul l-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. t hese shoul d be pl aced i n a c ondition i n whi ch m inimum c urrent i s dra wn or c onnected only to external circuits that do not draw current, such as other cmos inputs. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator , the additional standby current will also be perhaps in the order of several hundred micro-amps .
rev. 1.40 ? 8 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 ?9 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external falling edge on port a ? a system interrupt ? a wdt overfow i f the device is woken up by a wdt overfow , a w atchdog t imer reset will be initiated. the pdf fag is cleared by a system power -up or executing the clear w atchdog t imer instructions and is set when executing the hal t instruction. the t o fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer , the other fags remain in their original status. each pin on port a can be setup using the p awu register to permit a negative transition on the pin to wake-up t he syste m. when a port a pin wake-up occurs, the progra m wil l resume exec ution at the i nstruction f ollowing t he halt i nstruction. i f t he sy stem i s wo ken u p by a n i nterrupt, t hen two possible situations may occur . the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the hal t instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag i s se t hi gh be fore e ntering t he sle ep or idl e mode, t he wa ke-up func tion of t he re lated interrupt will be disabled. system oscillator wake-up time (sleep mode) wake-up time (idle0 mode) wake-up time (idle1 mode) hirc 1 ? ~1 ? hirc ? y ? les 1~ ? hirc ? y ? les lirc 1~ ? lirc ? y ? les 1~ ? lirc ? y ? les lxt 10 ? 4 lxt ? y ? les 1~ ? lxt ? y ? les wake-up time programming considerations the high speed and low speed oscillators both use the same sst counter . for example, if the system is woken up from the sleep mode the hirc oscillator needs to start-up from an off state. if the device is woken up from the sleep mode to the no rmal mode, the high speed system oscillator needs an sst period. the device will execute the frst instruction after ht o is high. at this time, the lxt oscillator may not be stability if f sub is from lxt oscillator . the same situation occurs i n t he powe r-on st ate. t he l xt osc illator i s not rea dy yet whe n t he first i nstruction i s executed.
rev. 1.40 ?8 de?e??e? 0?? ?01? rev. 1.40 ? 9 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver watchdog timer the w atchdog t imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the w atchdog t imer clock source is provided by the internal f sub clock which is in turn supplied by either the lxt or lirc oscillator selected by a confguration option . the lirc internal oscillator has an approximate frequency of 32khz and this specifed internal clock period can vary with v dd , temperature and process variations. the lxt oscillator is supplied by an external 32.768 khz crystal. the w atchdog t imer so urce c lock i s t hen su bdivided b y a r atio o f 2 8 t o 2 18 t o g ive l onger timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register. watchdog timer control register a single register , wdtc, controls the required timeout period as well as the enable operation . the wdtc register is initiated to 01010011b at any reset except wdt time-out hardware warm reset . wdtc register bit 7 6 5 4 3 2 1 0 na ? e we4 we3 we ? we1 we0 ws ? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 b it 7~ 3 we4 ~ we0 : wdt function software control 01010b or 10101 b: en able d other values: reset mcu (reset will be active after 2 ~ 3 lirc clock for debounce time.) if the mcu reset is caused by the we [4:0] in wdtc software reset, the wrf fag of ctrl register will be set. b it 2~ 0 ws2 ~ ws0 : wdt t ime - out period selection 000: 2 8 /f sub 001: 2 10 /f sub 010: 2 12 /f sub 011: 2 14 /f sub 100: 2 15 /f sub 101: 2 16 /f sub 110: 2 17 /f sub 111: 2 18 /f sub these three bits determine the division ratio of the watchdog t imer source clock, which in turn determines the timeout period.
rev. 1.40 ? 0 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 ?1 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver ctrl register bit 7 6 5 4 3 2 1 0 na ? e fsyson hircs1 hircs0 lxtlp lvrf d1 wrf r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 x 0 0 x unknown b it 7 fsyson : f sys control in idle mode describe elsewhere b it 6 unimplemented, read as 0 bit 5 ~ 4 hircs1~hircs0 : hirc frequency clock select describe elsewhere b it 3 lxtlp : lxt low power control describe elsewhere bit 2 lvrf : lvr function reset fag describe elsewhere bit 1 undefned bit this bit can be read or written by user application program. bit 0 wrf : wdt control register software reset fag 0: not occur 1: occurred this bit is set high by the wdt cont rol register soft ware reset and cl eared by the application program. note that this bit can only be cleared to zero by the application program. watchdog timer operation the w atchdog t imer ope rates by provi ding a de vice re set whe n i ts t imer ove rfows. t his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he watchdog t imer before it overfows to prevent the w atchdog t imer from executing a reset. this is done using the cle ar watchdog instructions. if the program malfunction s for whatever reason, jumps to an unknown location, or enters an endless loop, the clear wdt instruction will not be executed in the correct manne r, in which case the w atchdog t imer will overfow and reset the device. there are fve bits, we4~we0, in the wdtc register to enable the wdt functio n. when the we4~we0 bits value is equal to 01010b or 10101b, the wdt function is enabled. however , if the we4~we0 bits are changed to any other values except 01010b and 10101b, which is caused by the environmental noise, it will reset the microcontroller after 2~3 lirc clock cycles. after power on these bits will have a value of 01010b. under norm al progra m ope ration, a w atchdog t imer t ime-out wi ll i nitialise a de vice re set a nd se t the status bit t o. however , if the system is in the sleep or idle mode, when a w atchdog t imer time-out occurs, the t o bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the w atchdog t imer. the frst is a wd t software reset, which means a certain value is written into the we4~we0 bit fled exce pt 01010b and 10101b, t he second is using the w atchdog t imer software clear instruction and the third is via a halt instruction. there is only one method of using software instruction to clear the w atchdog t imer. that is to use the single clr wdt instruction to clear the wdt . the maximum time-out period is when the 2 18 division ratio is selected. as an example, with a 32 khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 8 seconds for the 2 18 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration.
rev. 1.40 ?0 de?e??e? 0?? ?01? rev. 1.40 ? 1 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver clr wdt inst?u?tion 11-stage divide? 7-stage divide? we4~we0 ?its wdtc registe? reset mcu f sub 8-to-1 mux clr ws?~ws0 wdt ti?e-out (? 8 /f sub ~ ? 18 /f sub ) lirc halt inst?u?tion lxt m u x configu?ation option 1rwh )ru wkh %?% ghylfh wkh i ?8% lv vxssolhg rqo e wkh /??& rvfloodwru watchdog timer reset and initialisation uhvhw ixfwlr lv d ixgdphwdo sduw ri d plfurfrwuroohu hvxulj wkdw wkh ghylfh fd eh vhw wr vrph suhghwhuplhg frglwlr luuhvshfwlyh ri rxwvlgh sdudphwhuv 7kh prvw lpsruwdw uhvhw frglwlr lv diwhu srzhu lv uvw dssolhg wr wkh plfurfrwuroohu , wklv fdvh lwhudo flufxlwu zloo hvxuh wkdw wkh pl furfrwuroohu diwhu d vkruw gho d zloo eh l d zhoo ghilhg vwdwh dg uhd g wr h[hfxwh w kh u vw s urjudp l vwuxfwlr i whu w klv s rzhur u hvhw f huwdl l psruwdw l whudo u hjlvwhuv zloo eh vhw wr ghhg vwdwhv ehiruh wkh surjudp frpphfhv 2h ri wkhvh uhjlvwhuv lv wkh 3urjudp &rxwhu zklfk zloo eh uhvhw wr ]hur iruflj wkh plfurfrwuroohu wr ehjl surjudp h[hfxwlr iurp wkh orzhvw 3urjudp 0hpru dgguhvv rwkhu wsh ri uhvhw lv z kh wkh : dwfkgrj 7 lphu ryhuiorz v dg uhvhwv wkh plfurfrwuroohu oo wshvri uhvhw rshudwlrv uhvxow l gli ihuhw uhjlvwhu frglwlrv ehlj vhwxs rwkhu uhvhw h[lvwv l wkh irup ri d /rz 9 rowdjh 5hvhw / 95 zkhuh d ixoo uhvhw lv lpsohphwhg l vlwxdwlrv zkhuh wkh srzhu vxsso yrowdjh idoov ehorz d fhuwdl wkuhvkrog reset functions 7khuh duh vhyhudo zdv l zklfk d plfurfrwuroohu uhvhw fd rffxu wkurxjk hyhwv rffxuulj lwhudoo power-on reset 7kh p rvw ixg dphwdo d g xd yrlgdeoh uh vhw l v w kh rh w kdw rf fxuv d iwhu srzh u l v uvw d ssolhg w r wkh plfurfrwuroohu v zhoo dv hvxulj wkdw wkh 3urjudp 0hpru ehjlv h[hfxwlr iurp wkh uvw phpru dgguhvv d srz hur uhvhw dov r hvxuhv wkdw fhuwdl rwkhu uhjlvwhuv duh suhvhw wr nrz frglwlrv oo wkh ,2 sruw dg sruw frwuro uhjlvwhuv zloo srzhu xs l d kljk frglwlr hvxulj wkdw doo slv zloo eh uvw vhw wr lsxwv vdd powe? - on reset sst ti?e - out t rstd 1rwh w ??7' lv srzhurq ghod wslfdo wlph pv power-on reset timing chart
rev. 1.40 ?? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 ?3 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver low voltage reset C lvr the micr ocontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device . the l vr function is always enabled with a specifc l vr voltag e, v lvr . if the supply voltage of the device drops to within a range of 0.9v~ v lvr such as might occur when changing the battery , the l vr will automatically reset the device internally and the l vrf bit in the ctrl register will also be set high . f or a valid lvr signal, a low voltage, i.e., a voltage in the range between 0.9v~ v lvr must exist for greater than the value t lvr specifed in the a.c. characteri stics. if the low voltage state does not exceed this value , the l vr will ignore the low supply voltage and will not perform a reset function. the actual v lvr is fxed at a voltage value of 2.55v . note that the l vr function will be automatically disabled when the device enters the sleep or idle mode. note: t rstd is power-on delay, typical time=50ms low voltage reset timing chart ctrl register bit 7 6 5 4 3 2 1 0 na ? e fsyson hircs1 hircs0 lxtlp lvrf d1 wrf r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 x 0 0 x unknown b it 7 fsyson : f sys control in idle mode describe elsewhere bit 6 unimplemented, read as 0. bit 5 ~ 4 hircs1~hircs0 : hirc frequency clock select describe elsewhere bit 3 lxtlp : lxt low power control describe elsewhere b it 2 lvrf : lvr function reset fag 0: n ot occur 1: occurred this bit is set high when a specifc low v oltage reset situation conditi on occurs. this bit can only be cleared to zero by the application program. b it 1 undefned bit this bit can be read or written by user application program. b it 0 wrf : wdt control register software reset fag describe elsewhere
rev. 1.40 ?? de?e??e? 0?? ?01? rev. 1.40 ? 3 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver watchdog time-out reset during normal operation the w atchdog time-out reset during normal operation is the same as a lvr reset except that the watchdog time-out fag t o will be set to 1. note: t rstd is power-on delay, typical time=16.7ms wdt time-out reset during normal operation timing chart watchdog time-out reset during sleep or idle mode the w atchdog time-out reset during sleep or idle mode is a little dif ferent from other kinds of re set. mo st of t he c onditions re main unc hanged e xcept t hat t he pro gram count er a nd t he st ack pointer will be cle ared to 0 and the t o fag will be set to 1. refer to the a.c. characteristics for t sst details. note: the t sst is 15~16 clock cycles if the system clock source is provided by the hirc. the t sst is 1~2 clock for the lirc. the t sst is 1024 clock for the lxt. wdt time-out reset during sleep or idle timing chart reset initial conditions the dif ferent types of reset described af fect the reset fags in dif ferent ways. these fags, known as p df and t o are located in the s tatus regis ter and are controlled by various microcontroller operations, su ch a s t he sl eep o r i dle mo de f unction o r w atchdog t imer. t he r eset f lags a re shown in the table: to pdf reset conditions 0 0 powe ? -on ? eset u u lvr ? eset du ? ing normal o ? slow mode ope ? ation 1 u wdt ti ? e-out ? eset du ? ing normal o ? slow mode ope ? ation 1 1 wdt ti ? e-out ? eset du ? ing idle o ? sleep mode ope ? ation note: u stands fo ? un ? hanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset p ? og ? a ? counte ? reset to ze ? o inte ?? upts all inte ?? upts will ? e disa ? led wdt clea ? afte ? ? eset ? wdt ? egins ? ounting ti ? e ? modules ti ? e ? modules will ? e tu ? ned off input/output po ? ts i/o po ? ts will ? e setup as inputs ? an0~an7 as a/d input pins sta ? k pointe ? sta ? k pointe ? will point to the top of the sta ? k
rev. 1.40 ? 4 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 ?? de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver the dif ferent kinds of resets all af fect the internal registers of the micr ocontroller in dif ferent ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. registe ? bs8 ? b1 ? a-3 bs8 ? c1 ? a-3 bs8 ? d ? 0a-3 powe ? on reset lvr reset (no ?? al ope ? ation) wdt ti ? e-out (no ?? al ope ? ation) wdt ti ? e-out (halt)* p ? og ? a ? counte ? 0000h 0000h 0000h 0000h iar0 0000 0000 0000 0000 0000 0000 uuuu uuuu mp0 0000 0000 0000 0000 0000 0000 uuuu uuuu iar1 0000 0000 0000 0000 0000 0000 uuuu uuuu mp1l 0000 0000 0000 0000 0000 0000 uuuu uuuu mp1h 0000 0000 0000 0000 0000 0000 uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tbhp ---- -xxx ---- -xxx ---- -uuu ---- -uuu ---- xxxx ---- uuuu ---- uuuu ---- uuuu ---x xxxx ---u uuuu ---u uuuu ---u uuuu status xx00 xxxx uuuu uuuu uu1u uuuu uu11 uuuu smod 000- 0011 000- 0011 000- 0011 uuu- uuuu iar ? 0000 0000 0000 0000 0000 0000 uuuu uuuu mp ? l 0000 0000 0000 0000 0000 0000 uuuu uuuu mp ? h 0000 0000 0000 0000 0000 0000 uuuu uuuu integ ---- --00 ---- --00 ---- --00 ---- --uu intc0 -000 0000 -000 0000 -000 0000 -uuu uuuu intc1 0000 0000 0000 0000 0000 0000 uuuu uuuu intc ? 0000 0000 0000 0000 0000 0000 uuuu uuuu intc3 0000 0000 0000 0000 0000 0000 uuuu uuuu pa 1--1 1111 1--1 1111 1--1 1111 u--u uuuu pac 1--1 1111 1--1 1111 1--1 1111 u--u uuuu papu 0--0 0000 0--0 0000 0--0 0000 u--u uuuu pawu 0--0 0000 0--0 0000 0--0 0000 u--u uuuu sledc0 0101 0101 0101 0101 0101 0101 uuuu uuuu sledc1 ---- 0101 ---- 0101 ---- 0101 ---- uuuu --01 0101 --01 0101 --01 0101 --uu uuuu wdtc 0101 0011 0101 0011 0101 0011 uuuu uuuu tbc 0000 0000 0000 0000 0000 0000 uuuu uuuu pscr --00 --00 --00 --00 --00 --00 --uu --uu eea --00 0000 --00 0000 --00 0000 --uu uuuu eed 0000 0000 0000 0000 0000 0000 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 uuuu uuuu pbpu 0000 0000 0000 0000 0000 0000 uuuu uuuu simtoc 0000 0000 0000 0000 0000 0000 uuuu uuuu
rev. 1.40 ?4 de?e??e? 0?? ?01? rev. 1.40 ?? de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver registe ? bs8 ? b1 ? a-3 bs8 ? c1 ? a-3 bs8 ? d ? 0a-3 powe ? on reset lvr reset (no ?? al ope ? ation) wdt ti ? e-out (no ?? al ope ? ation) wdt ti ? e-out (halt)* simc0 (spi mode) 111- --00 111- --00 111- --00 uuu- --uu simc0 (i ? c mode) 111- 000- 111- 000- 111- 000- uuu- uuu- simc1 1000 0001 1000 0001 1000 0001 uuuu uuuu simd xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu simc ? 0000 0000 0000 0000 0000 0000 uuuu uuuu sima 0000 000- 0000 000- 0000 000- uuuu uuu- usr 0000 1011 0000 1011 0000 1011 uuuu uuuu ucr1 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu ucr ? 0000 0000 0000 0000 0000 0000 uuuu uuuu brg xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu txr_rxr xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrl (adrfs=0) xxxx ---- xxxx ---- xxxx ---- uuuu ---- adrl (adrfs=1) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh (adrfs=0) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh (adrfs=1) ---- xxxx ---- xxxx ---- xxxx ---- uuuu adcr0 0110 -000 0110 -000 0110 -000 uuuu -uuu adcr1 00-0 -000 00-0 -000 00-0 -000 uu-u -uuu acerl 1111 1111 1111 1111 1111 1111 uuuu uuuu tmpc --00 0000 --00 0000 --00 0000 --uu uuuu slcdc0 0000 0000 0000 0000 0000 0000 uuuu uuuu slcdc1 0000 0000 0000 0000 0000 0000 uuuu uuuu slcdc ? 0000 0000 0000 0000 0000 0000 uuuu uuuu slcdc3 ---- 0000 ---- 0000 ---- 0000 ---- uuuu lvdc --00 -000 --00 -000 --00 -000 --uu -uuu ifs ---- ---0 ---- ---0 ---- ---0 ---- ---u pc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcpu 0000 0000 0000 0000 0000 0000 uuuu uuuu ctrl 0-00 -x00 0-00 -x00 0-00 -x00 u-uu -uuu 0-00 0x00 0-00 0x00 0-00 0x00 u-uu uuuu pd ---- 1111 ---- 1111 ---- 1111 ---- uuuu pdc ---- 1111 ---- 1111 ---- 1111 ---- uuuu pdpu ---- 0000 ---- 0000 ---- 0000 ---- uuuu tktmr 0000 0000 0000 0000 0000 0000 uuuu uuuu tkc0 -000 0000 -000 0000 -000 0000 -uuu uuuu tk1 ? dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tk1 ? dh 0000 0000 0000 0000 0000 0000 uuuu uuuu tkc1 ---- --11 ---- --11 ---- --11 ---- --uu tkm01 ? dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm01 ? dh 0000 0000 0000 0000 0000 0000 uuuu uuuu
rev. 1.40 ?? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 ?7 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver registe ? bs8 ? b1 ? a-3 bs8 ? c1 ? a-3 bs8 ? d ? 0a-3 powe ? on reset lvr reset (no ?? al ope ? ation) wdt ti ? e-out (no ?? al ope ? ation) wdt ti ? e-out (halt)* tkm0rol 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm0roh ---- --00 ---- --00 ---- --00 ---- --uu tkm0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm0c1 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu tkm11 ? dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm11 ? dh 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm1rol 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm1roh ---- --00 ---- --00 ---- --00 ---- --uu tkm1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm1c1 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu tkm ? 1 ? dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm ? 1 ? dh 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm ? rol 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm ? roh ---- --00 ---- --00 ---- --00 ---- --uu tkm ? c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm ? c1 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu tkm31 ? dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm31 ? dh 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm3rol 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm3roh ---- --00 ---- --00 ---- --00 ---- --uu tkm3c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm3c1 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu ctm0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu ctm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu ctm0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu ctm0dh ---- --00 ---- --00 ---- --00 ---- --uu ctm0al 0000 0000 0000 0000 0000 0000 uuuu uuuu ctm0ah ---- --00 ---- --00 ---- --00 ---- --uu ptm1c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- ptm1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm1dh ---- --00 ---- --00 ---- --00 ---- --uu ptm1al 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm1ah ---- --00 ---- --00 ---- --00 ---- --uu ptm1rpl 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm1rph ---- --00 ---- --00 ---- --00 ---- --uu tkm41 ? dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm41 ? dh 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm4rol 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm4roh ---- --00 ---- --00 ---- --00 ---- --uu tkm4c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm4c1 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu ptm ? c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- ptm ? c1 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm ? dl 0000 0000 0000 0000 0000 0000 uuuu uuuu
rev. 1.40 ?? de?e??e? 0?? ?01? rev. 1.40 ? 7 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver registe ? bs8 ? b1 ? a-3 bs8 ? c1 ? a-3 bs8 ? d ? 0a-3 powe ? on reset lvr reset (no ?? al ope ? ation) wdt ti ? e-out (no ?? al ope ? ation) wdt ti ? e-out (halt)* ptm ? dh ---- --00 ---- --00 ---- --00 ---- --uu ptm ? al 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm ? ah ---- --00 ---- --00 ---- --00 ---- --uu ptm ? rpl 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm ? rph ---- --00 ---- --00 ---- --00 ---- --uu eec ---- 0000 ---- 0000 ---- 0000 ---- uuuu 1rwh vwdqgv iru zdup uhvhw lpsohph x d u xfdh d u x
rev. 1.40 ? 8 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 ?9 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver input/output ports holtek m icrocontrollers of fer c onsiderable fe xibility on t heir i/ o port s. w ith t he i nput or out put designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the devices provide bidirectional input/output lines labeled with port names p a ~ pd. these i/o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. a ll of thes e i/o ports can be used for input and output operations. for input operation, these ports are non-latch ing, which means the inputs must be ready at the t2 rising edge of instruction mov a, [m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. i/o register list device register name bit 7 6 5 4 3 2 1 0 bs8 ? b1 ? a-3 bs8 ? c1 ? a-3 bs8 ? d ? 0a-3 pawu pawu 7 pawu 4 pawu 3 pawu ? pawu 1 pawu 0 papu papu 7 papu 4 papu 3 papu ? papu 1 papu 0 pa pa 7 pa 4 pa 3 pa ? pa 1 pa 0 pac pac 7 pac 4 pac 3 pac ? pac 1 pac 0 pbpu pbpu7 pbpu ? pbpu ? pbpu4 pbpu3 pbpu ? pbpu1 pbpu0 pb pb7 pb ? pb ? pb4 pb3 pb ? pb1 pb0 pbc pbc7 pbc ? pbc ? pbc4 pbc3 pbc ? pbc1 pbc0 pcpu pcpu7 pcpu ? pcpu ? pcpu4 pcpu3 pcpu ? pcpu1 pcpu0 pc pc7 pc ? pc ? pc4 pc3 pc ? pc1 pc0 pcc pcc7 pcc ? pcc ? pcc4 pcc3 pcc ? pcc1 pcc0 bs8 ? c1 ? a-3 bs8 ? d ? 0a-3 pdpu pdpu3 pdpu ? pdpu1 pdpu0 pd pd3 pd ? pd1 pd0 pdc pdc3 pdc ? pdc1 pdc0 pawun: pa wake-up function control 0: disable 1: enable pan/pbn/pcn/pdn: i/o data bit 0: data 0 1: data 1 pacn/pbcn/pccn/pdcn: i/o t ype selection 0: output 1: input papun/pbpun/pcpun/pdpun: i/o pull-high function control 0: disable 1: enable pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . t o eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor . these pull-high re sistors a re se lected usi ng re gisters p apu~pdpu, a nd a re i mplemented usi ng we ak pmos transistors.
rev. 1.40 ?8 de?e??e? 0?? ?01? rev. 1.40 ? 9 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver port a wake-up the hal t instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. v arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low . this function is especially suitable for applications that can be woken up via extern al switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. i/o port control registers each i/o port has its ow n control register known as p ac~p d c, to control the input/output configuration. w ith this control register , each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register . for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register . however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pin-remapping function there is an ifs register which is used to select the ptp2i pin function for the bs86b12a-3 device. ifs register bit 7 6 5 4 3 2 1 0 na ? e ptp ? is r/w r/w por 0 bit 7 ~ 1 unimplemented, read as 0 bit 0 ptp2is : ptp2i pin remapping control 0: ptp2i on pb7 (default) 1: ptp2i on pb4
rev. 1.40 70 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 71 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will dif fer from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown.

??? ?? ? ? ? generic input/output structure

? ? ? ?
? ? - ? ? ? ? ? ? ? ? - a/d input/output sturcture
rev. 1.40 70 de?e??e? 0?? ?01? rev. 1.40 71 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver source current selection the source current of each pin in these devices can be configured with dif ferent source current which is selected by the corresponding pin source current select bits. these source current bits are available when the corresponding pin is confgured as a cmos output. otherwise, these select bits have no ef fect. users should refer to the d.c. characteristics section to obtain the exact value for different applications. sledc0 register bit 7 6 5 4 3 2 1 0 na ? e pbps3 pbps ? pbps1 pbps0 paps3 paps ? paps1 paps0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 bit 7 ~ 6 pbps3~pbps2 : pb7~pb4 source current select 00 : source = level 0 (min.) 01 : source = level 1 10 : source = level 2 11 : source = level 3 (max .) these bits are available when the corresponding pin is confgured as a cmos output. bit 5 ~ 4 pbps1~pbps0 : pb3~pb 0 source current select 00 : source = level 0 (min.) 01 : source = level 1 10 : source = level 2 11 : source = level 3 (max .) these bits are available when the corresponding pin is confgured as a cmos output. bit 3 ~ 2 paps3~paps2 : pa7 and pa 4 source current select 00 : source = level 0 (min.) 01 : source = level 1 10 : source = level 2 11 : source = level 3 (max .) these bits are available when the corresponding pin is confgured as a cmos output. bit 1 ~ 0 paps1~paps0 : pa3~ pa 0 source current select 00 : source = level 0 (min.) 01 : source = level 1 10 : source = level 2 11 : source = level 3 (max .) these bits are available when the corresponding pin is confgured as a cmos output.
rev. 1.40 7 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 73 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver sledc1 register bit 7 6 5 4 3 2 1 0 na ? e pdps1 pdps0 pcps3 pcps ? pcps1 pcps0 r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 bit 7 ~ 6 unimplemented, read as 0 bit 5 ~ 4 pdps1~pdps0 : pd3~pd 0 source current select 00 : source = level 0 (min.) 01 : source = level 1 10 : source = level 2 11 : source = level 3 (max .) these bits are available when the corresponding pin is confgured as a cmos output. note: these bits are only available for the bs86c16a-3 and BS86D20A-3 devices. bit 3 ~ 2 pcps3~pcps2 : pc7~pc 4 source current select 00 : source = level 0 (min.) 01 : source = level 1 10 : source = level 2 11 : source = level 3 (max .) these bits are available when the corresponding pin is confgured as a cmos output. bit 1 ~ 0 pcps1~pcps0 : pc3~pc 0 source current select 00 : source = level 0 (min.) 01 : source = level 1 10 : source = level 2 11 : source = level 3 (max .) these bits are available when the corresponding pin is confgured as a cmos output. programming considerations within the user program, one of the frst things to consider is port initi alisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an i nput st ate, t he l evel of whi ch de pends on t he ot her c onnected c ircuitry a nd whe ther pul l-high selections have been chosen. if the port control registers, p ac~p d c, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port dat a regi sters, p a~p d , a re frst progra mmed. se lecting whi ch pi ns a re i nputs a nd whi ch are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function.
rev. 1.40 7? de?e??e? 0?? ?01? rev. 1.40 73 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver timer modules C tm one of the most fundamental functions in any microcontroller device is the ability to control and measure time. t o implement time related functions the device includes several t imer modules, abbreviated t o t he na me t m. t he t ms a re m ulti-purpose t iming un its a nd se rve t o pr ovide operations such as t imer/counter, input capture, compare match output and single pulse output as we ll a s be ing t he fun ctional uni t for t he ge neration of pw m si gnals. e ach of t he t ms ha s t wo individual interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the common features of the dif ferent tm types are described here with more detailed information provided in the individual compact and periodic tm section s. introduction each de vice contain s a 10 -bit co mpact t m, ct m0, a nd t wo 10 -bit pe riodic t ms, pt m1 a nd ptm2 . al though si milar i n na ture, t he di fferent t m t ypes va ry i n t heir fe ature c omplexity. t he common features to the compact and periodic tms will be described in this section and the detailed operation will be described in corresponding sections. the main features and dif ferences between the two types of tms are summarised in the accompanying table. function ctm ptm ti ? e ? /counte ? i/p captu ? e co ? pa ? e mat ? h output pwm channels 1 1 single pulse output 1 pwm align ? ent edge edge pwm adjust ? ent pe ? iod & duty duty o ? pe ? iod duty o ? pe ? iod tm function summary ctm0 ptm1 ptm2 10-bit ctm 10-bit ptm 10-bit ptm tm name/type reference tm operation the two different t ypes o f t m s o ffer a d iverse r ange o f f unctions, f rom si mple t iming o perations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a fre e runni ng c ounter who se va lue i s t hen c ompared wi th t he va lue of pre -programmed i nternal comparators. when the free running counter has the same value as the pre-programmed comparator , known a s a c ompare m atch si tuation, a t m i nterrupt si gnal wi ll be ge nerated whi ch c an c lear t he counter a nd pe rhaps a lso c hange t he c ondition of t he t m ou tput pi n. t he i nternal t m c ounter i s driven by a user selectable clock source, which can be an internal clock or an external pin. tm clock source the clock source which drives the main counter in each tm can originate from various sources. the selection of the required clock source is implemented using the xtnck2~x tnck0 bits in the xtmn control registers , where x can stand for c or p and n is the serial number . the clock source can be a ratio of either the system clock f sys or the internal high clock f h , the f sub clock source or the external x tckn pin. the x tckn pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting.
rev. 1.40 74 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 7? de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver tm interrupts the compact and periodic type tms each has two internal interrupts, the internal comparator a or com parator p , whi ch ge nerate a tm interrupt when a com pare match condition oc curs. whe n a tm interrupt is generated, it can be used to clear the counter and also to change the state of the tm output pin. tm external pins each of the tms, irrespective of what type, has one or two tm input pin s , with the label x tckn and xtpni respectively . the tm input pin, xtckn, is essentially a clock source for the tm and is selected using the x tnck2~x tnck0 bits in the x tmnc0 register . this external tm input pin allows an externa l clock source to drive the internal tm. the tm input pin can be chosen to have either a rising or falling active edge. the ptckn pins are also used as the external trigger input pin in single pulse output mode for the ptm. the other tm input pin, ptpni, is the capture input whose active edge can be a rising edge, a falling edge or both rising and fallin g edges and the active edge transit ion type is selected using the ptnio1~ptnio0 bits in the ptmnc1 register. the tms each ha s two output pins. when the tm is in the compare match output mode, these pins can be controlled by the tm to s witch to a high or low level or to toggle w hen a compare match situation occurs. the externa l x tpn and xtpnb output pin s are also the pin s where the tm generates the pwm output waveform. as the tm output pins are pin-shared with other function, the tm output function must frst be setup using the associated register. a single bit in the register determines if its associated pin is to be used as an external tm output pin or if it is to have another function. the number of external pins for each tm type is dif ferent, the details are provided in the accompanying table. device ctm0 ptm1 ptm2 bs8 ? b1 ? a-3 ctck0 ctp0 ? ctp0b ptck1 ? ptp1i ptp1 ? ptp1b ptck ?? ptp ? i ptp ?? ptp ? b bs8 ? c1 ? a-3 bs8 ? d ? 0a-3 tm input/output pins
rev. 1.40 74 de?e??e? 0?? ?01? rev. 1.40 7 ? de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver tm input/output pin control register selecting t o ha ve a t m i nput/output or whe ther t o re tain i ts ot her sha red func tion i s i mplemented using one register , with a single bit in each register corresponding to a tm input/output pin. setting the bit high will setup the corresponding pin as a tm input/output, if reset to zero the pin will retain its original other function.
c tm0 function pin control block diagram

ptm1 function pin control block diagram
rev. 1.40 7 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 77 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver
ptm2 function pin control block diagram tmpc register bit 7 6 5 4 3 2 1 0 na ? e tm ? pc1 tm ? pc0 tm1pc1 tm1pc0 tm0pc1 tm0pc0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 b it 7 ~6 unimplemented, read as 0 bit 5 t m2pc1 : ptp2b pin control 0: disabled 1: enabled bit 4 tm2pc0 : ptp2 pin control 0: disabled 1: enabled bit 3 tm1pc1 : ptp 1b pin control 0: disabled 1: enabled bit 2 tm1pc0 : ptp 1 pin control 0: disabled 1: enabled bit 1 tm0pc1 : ctp0b pin control 0: disabled 1: enabled bit 0 tm0pc0 : ctp0 pin control 0: disabled 1: enabled
rev. 1.40 7? de?e??e? 0?? ?01? rev. 1.40 77 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver programming considerations the tm counter registers and the capture/compare ccra and ccrp registers , being 1 0 -bit, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buf fer, reading or writing to these register pairs must be carried out in a specifc way . the important point to note is that data transfer to and from the 8-bit buffer and its rela ted low byte only takes place when a write or read operation to its corresponding high byte is executed. as the ccra and ccrp register s are implemented in the way shown in the following diagram and accessing th ese register s is carried out in a specifc way described above, it is recommended to use the mov instruction to access the ccra and ccrp low byte register s , named x tm n al and ptmnrpl , in the following access procedures. accessing the ccra or ccrp low byte register without following these access procedures will result in unpredictable values. data bus 8- ?it buffe? xtmndh xtmndl xtmnah xtmnal xtmn counte? registe? ( read only ) xtmn ccra registe? ( read / w?ite ) ptm n ccr p registe? ( read / w?ite ) p tm nrp h p tm nrp l 7kh iroorzlqj vwhsv vkrz wkh uhdg dqg zulwh surfhgxuhv :ulwlqj 'dwd wr &&? ru &&?3 step 1. w rite data to low byte xtmn al or ptmnrpl C note that here data is only written to the 8-bit buffer. step 2. w rite data to high byte xtmn ah or ptmnrph C here data is written directly to the high byte regis ters and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccr a or ccrp step 1. read data from the high byte xtmn dh, xtmn ah or ptmnrph C here d ata i s r ead d irectly f rom t he hi gh b yte r egisters a nd si multaneously d ata i s l atched from the low byte register into the 8-bit buffer. step 2. read data from the low byte xtmn dl, xtmn al or ptmnrpl C this step reads data from the 8-bit buffer.
rev. 1.40 78 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 79 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver compact type tm C ctm 0 although the simplest form of the two tm types, the compact tm type still contains three operating modes, wh ich a re compare ma tch ou tput, t imer/event c ounter a nd pw m ou tput m odes. t he compact tm can also be controlled with an external input pin and can drive two external output pin s.
? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? - ??? ?? - ??? - ? ? ? - ? ?? ? - ? ? - ? ? ? compact type tm block diagram compact tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. t here a re a lso t wo i nternal c omparators wi th t he na mes, com parator a a nd com parator p. these c omparators wi ll c ompare t he v alue i n t he c ounter wi th c crp a nd c cra r egisters. t he ccrp is three bits wide whose value is compared with the highest three bits in the counter while the ccra is the ten bits and therefore compares with all counter bits. the only way of changing the value of the 1 0 -bit counter using the application program, is to clear the counter by changing the c t 0 on bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a ctm0 interrupt signal will also usually be generated. the compact type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources i ncluding a n i nput pi n a nd c an a lso c ontrol one out put pi n. al l ope rating set up c onditions are selected using relevant internal registers. compact type tm register description overall ope ration of each compact t m i s c ontrolled usi ng several re gisters. a re ad onl y re gister pair exists to store the internal counter 1 0 -bit value, while a read/write register pair exists to store the internal 1 0 -bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. register name bit 7 6 5 4 3 2 1 0 ctm0c0 ct0 pau ct0 ck ? ct0ck1 ct0ck0 ct0on ct0 rp ? ct0rp1 ct0rp0 ctm0c1 ct0m1 ct0m0 ct0io1 ct0io0 ct0oc ct0pol ct0dpx ct0cclr ctm0dl d7 d ? d ? d4 d3 d ? d1 d0 ctm0dh d9 d8 ctm0al d7 d ? d ? d4 d3 d ? d1 d0 ctm0ah d9 d8 compact tm register list
rev. 1.40 78 de?e??e? 0?? ?01? rev. 1.40 79 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver ctm0c0 register bit 7 6 5 4 3 2 1 0 na ? e ct0 pau ct0 ck ? ct0ck1 ct0ck0 ct0on ct0 rp ? ct0rp1 ct0rp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ct0 pau : ctm 0 counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the ctm0 will remain powered up a nd c ontinue t o c onsume po wer. t he c ounter wi ll re tain i ts re sidual va lue whe n this bit changes from low to high and resume counting from this value when the bit changes to a low value again. b it 6~4 ct0ck2~ct0ck0 : select ctm0 counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f sub 101: f sub 110: ctck0 rising edge clock 111: ctck0 falling edge clock these t hree bit s a re use d t o se lect t he c lock source for t he ct m 0 . t he e xternal pi n clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f sub are other internal clocks, the details of which can be found in the oscillator section. b it 3 ct0on : ctm 0 counter on/off control 0: off 1: on this bit controls the overall on/of f function of the ctm 0 . setting the bit high enables the counter to run, clearing the bit disables the ctm 0 . clearing this bit to zero will stop the counter from counting and turn of f the ctm 0 which will reduce its power consumption. when the bit changes state from low to high the interna l counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value. if t he c tm 0 i s i n t he c ompare ma tch ou tput mo de t hen t he c tm 0 o utput p in wi ll be reset to its initial condition, as specifed by the ct 0 oc bit, when the ct 0 on bit changes from low to high. bit 2~0 ct0rp2~ct0rp0 : ctm0 ccrp 3-bit register, compared with the ctm0 counter bit 9~bit 7 comparator p match period 000: 1024 ctm0 clocks 001: 128 ctm0 clocks 010: 256 ctm0 clocks 011: 384 ctm0 clocks 100: 512 ctm0 clocks 101: 640 ctm0 clocks 110: 768 ctm0 clocks 111: 896 ctm0 clocks these three bits are used to setup the value on the internal ccrp 3-bit register , which are then compared with the internal counter s highest three bits. the result of this comparison can be selected to clear the internal counter if the ct 0 cclr bit is set to zero. setting the ct0 cclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in effect allowing the counter to overfow at its maximum value.
rev. 1.40 80 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 81 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver c tm0c1 register bit 7 6 5 4 3 2 1 0 na ? e ct0m1 ct0m0 ct0io1 ct0io0 ct0oc ct0pol ct0dpx ct0cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7~6 ct0m1~ct0m0 : select ctm 0 operating mode 00: compare match output mode 01: undefned 10: pwm mode 11: t imer/counter mode these bits setup the required operating mode for the c tm0 . t o ensure reliable operation the c tm 0 should be switched of f before any changes are made to the ct0 m1 and ct0 m0 bits. in the t imer/counter mode, the ctm0 output pin control must be disabled. b it 5 ~4 ct0io1~ct0io0 : select ctp 0 output function compare match output mode 00: n o change 01: o utput low 10: o utput high 11: t oggle output pwm mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefned timer/counter mode unused these two bits are used to determine how the ctm 0 output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the ctm 0 is running. in t he c ompare ma tch ou tput mo de, t he c t 0 io1 a nd c t 0 io0 b its d etermine h ow t he ctm 0 o utput p in c hanges st ate wh en a c ompare m atch o ccurs f rom t he c omparator a. the ctm 0 output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the ctm 0 output pin s hould be s etup us ing the ct 0 oc bit in the ctm 0 c1 regis ter. n ote that the output level requested by the ct 0 io1 and ct 0 io0 bits must be dif ferent from the initial value setup using the ct 0 oc bit otherwise no change will occur on the ctm 0 output pin when a compare match occurs. after the ctm 0 output pin changes state it can be reset to its initial level by changing the level of the ct 0 on bit from low to high. in the pwm mode, the ct 0 io1 and ct 0 io0 bits determine how the ctm 0 output pin changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to only change the values of the ct 0 io1 and ct 0 io0 bits only after the ctm 0 has been switched off. unpredictable pwm outputs will occur if the ct 0 io1 and ct 0 io0 bits are changed when the ctm 0 is running.
rev. 1.40 80 de?e??e? 0?? ?01? rev. 1.40 81 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver b it 3 ct0oc : ctp 0 output control bit compare match output mode 0: i nitial low 1: i nitial high pwm mode 0: a ctive low 1: a ctive high this i s t he o utput c ontrol b it f or t he c tm 0 o utput p in. i ts o peration d epends u pon whether ct m 0 i s be ing used i n t he com pare ma tch output mode or i n t he pwm mode. it ha s no e ffect i f t he ct m 0 i s i n t he t imer/counter mode. in t he com pare match out put mode i t de termines t he l ogic l evel of t he ct m 0 out put pi n be fore a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. b it 2 ct0pol : ctp 0 output polarity control 0: non-invert 1: invert this bi t c ontrols t he pol arity of t he ct p 0 out put pi n. w hen t he bi t i s se t hi gh t he ctm 0 output pin will be inverted and not inverted when the bit is zero. it has no effect if the ctm 0 is in the t imer/counter mode. b it 1 ct0dpx : ctm 0 pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determin es which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. b it 0 ct0cclr : select ctm 0 counter clear condition 0: ctm0 comparatror p match 1: ctm0 comparatror a match this b it i s u sed t o se lect t he m ethod wh ich c lears t he c ounter. r emember t hat t he compact ctm 0 contains two comparators, comparator a and comparator p , either of which can be selected to clear the internal counter . w ith the ct 0 cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare mat ch occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the ct 0 cclr bit is not used in the pwm mode. ctm0 dl register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d ? d4 d3 d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 b it 7 ~ 0 ctm0 counter low byte register bit 7 ~ bit 0 ctm0 1 0 -bit counter bit 7 ~ bit 0 ctm0dh register bit 7 6 5 4 3 2 1 0 na ? e d9 d8 r/w r r por 0 0 b it 7 ~ 2 unimplemented, read as 0 bit 1 ~ 0 c tm0 counter high byte register bit 1 ~ bit 0 ctm0 1 0 -bit counter bit 9 ~ bit 8
rev. 1.40 8 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 83 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver c tm0 al register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d ? d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 0 ctm0 ccra low byte register bit 7 ~ bit 0 ctm0 1 0 -bit ccra bit 7 ~ bit 0 ctm0ah register bit 7 6 5 4 3 2 1 0 na ? e d9 d8 r/w r/w r/w por 0 0 bit 7 ~ 2 unimplemented, read as 0 b it 1 ~ 0 ctm0 ccra high byte register bit 1 ~ bit 0 ctm0 1 0 -bit ccra bit 9 ~ bit 8 compact type tm operating modes the compact t ype tm can operate in one of three operating modes, compare match output mode, pwm output mode or t imer/counter mode. the operating mode is selected using the ct0 m1 and ct0 m0 bits in the ctm0 c1 register. compare match output mode to select this mode, bits c t 0 m1 and c t 0 m0 in the c tm 0 c1 register , should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare match from comparator a and a compare match from comparator p . when the ct0 cclr bit is low , there are two ways in which the counter can be cleared. one is when a compare match from comparator p , the other is when the ccrp bits are all zero which allows the counter to overfow . here both ctma0 f and ctmp0 f interrupt request fags for comparator a and comparator p respectively, will both be generated. if the c t 0 cclr bit in the c tm 0 c1 register is high then the counter wi ll be cleared when a compare match occurs from comparator a. however , here only the c tma0 f interrupt request fag wi ll be ge nerated e ven i f t he va lue of t he ccrp bi ts i s l ess t han t hat of t he ccra re gisters. therefore when c t 0 cclr is high no c tmp0 f interrupt request flag will be generated. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the ctma0f interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the c tm0 output pin will change state. the c tm0 output pin condition however only changes state when a c tma0 f interrupt request fag is generated after a compare match occurs from comparat or a. the ctmp0 f interrupt request fa g, g enerated f rom a c ompare m atch o ccurs f rom c omparator p , wi ll h ave n o e ffect o n the c tm0 output pin. the way in which the c tm0 output pin changes state are determined by the condition of the ct0 io1 and ct0 io0 bits in the ctm0 c1 register . the ctm0 output pin can be selected using the ct0 io1 and ct0 io0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the c tm 0 output pin, which is setup after the ct0 on bit changes from low to high, is setup using the ct0 oc bit. note that if the ct0 io1 and ct0 io0 bits are zero then no pin change will take place.
rev. 1.40 8? de?e??e? 0?? ?01? rev. 1.40 83 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver ccra ccrp 0x3 ff counte? ove?flow ccra int . flag ctma 0f ccrp int . flag ctmp 0f ccrp > 0 counte? ?lea?ed ?y ccrp value ctm 0 o/ p pin ct 0 on pause counte? reset output pin set to initial level low if ct 0 oc = 0 output toggle with ctma 0f flag he?e ct 0 io [1:0 ] = 11 toggle output sele?t now ct 0 io [1:0 ] = 10 a?tive high output sele?t output not affe?ted ?y ctma 0f flag . re?ains high until ?eset ?y ct 0 on ?it compare match output mode - ct 0 cclr = 0 ct 0 cclr = 0 ; ct 0m[1:0 ] = 00 ct 0 pau resu?e stop ti?e ccrp > 0 ccrp = 0 ct 0 pol output pin reset to initial value output inve?ts when ct 0pol is high output ?ont?olled ?y othe? pin - sha?ed fun?tion counte? value compare match output mode C ct0cclr = 0 note: 1. w ith ct0 cclr = 0 , a comparator p match will clear the counter 2. the c tm0 output pin controlled only by the c tma0 f fag 3. the o utput pin reset to initial state by a c t0 on bit rising edge
rev. 1.40 84 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 8? de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver ccra ccrp 0x3 ff ccrp int . flag ctmp 0f ccra int . flag ctma 0f ccra > 0 counte? ?lea?ed ?y ccra value ctm 0 o/ p pin ct 0 on pause counte? reset output pin set to initial level low if ct 0 oc = 0 output toggle with ctma 0f flag he?e ct 0 io [1:0 ] = 11 toggle output sele?t now ct 0 io [1:0 ] = 10 a?tive high output sele?t output not affe?ted ?y ctma 0f flag . re?ains high until ?eset ?y ct 0 on ?it compare match output mode - c0tcclr = 1 ct 0 cclr = 1 ; ct 0m[1:0 ] = 00 ct 0 pau resu?e stop ti?e ccra = 0 ct 0 pol output pin reset to initial value output inve?ts when ct 0pol is high output ?ont?olled ?y othe? pin - sha?ed fun?tion counte? value output does not ?hange no ctma 0 f flag gene?ated on ccra ove?flow ccra = 0 counte? ove?flow ctmp 0 f not gene?ated compare match output mode C ct0cclr = 1 note: 1. w ith ct0 cclr = 1 , a comparator a match will clear the counter 2. the c tm output pin controlled only by the c tma0 f fag 3. the output pin reset to initial state by a c t0 on rising edge 4. the c tmp0 f fags is not generated when ct0 cclr = 1
rev. 1.40 84 de?e??e? 0?? ?01? rev. 1.40 8 ? de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver timer/counter mode to se lect t his m ode, bi ts c t 0 m1 a nd c t 0 m0 i n t he c tm 0 c1 re gister should be se t t o 1 1 respectively. the t imer/counter mode operates in an identical way to the compare match output mode generating the same interrupt flags. the exception is that in the t imer/counter mode the c tm0 output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the ctm0 output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits c t 0 m1 and c t 0 m0 in the c tm0 c1 register should be set to 10 respectively. the pwm function within the ctm0 is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fixed frequency but of varying duty cycle on the ctm0 output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fe xible. i n t he pw m m ode, t he ct0 cclr b it h as n o e ffect on t he pw m operation . bot h of t he ccra and ccrp re gisters a re use d t o ge nerate t he pw m wave form, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the ct0 dpx bit in the ctm0 c1 register . the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the ct0 oc bit in the ctm0 c1 register is used to select the required polarity of the pwm waveform while the two ct0 io1 and ct0 io0 bits are used to enable the pwm output or to force the ctm0 output pin to a fxed high or low level. the ct0 pol bit is used to reverse the polarity of the pwm output waveform. ? ctm, pwm mode, edge-aligned mode, ct0dpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe ? iod 1 ? 8 ??? 384 ? 1 ? ? 40 7 ? 8 89 ? 10 ? 4 duty ccra if f sys = 16mhz, ctm0 clock source is f sys /4, ccrp = 100b, ccra =128, the ctm0 pwm output frequency = (f sys /4) / 512 = f sys /2048 = 7.8125 khz, duty = 128/ 512 = 25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ? ctm, pwm mode, edge-aligned mode, ct0dpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe ? iod ccra duty 1 ? 8 ??? 384 ? 1 ? ? 40 7 ? 8 89 ? 10 ? 4 the pwm output period is determi ned by the ccra register value together with the ctm0 clock while the pwm duty cycle is defned by the ccrp register value.
rev. 1.40 8 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 87 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver ccrp ccra counter value counter cleared by ccrp ccra int . flag ctma0 f ccrp int . flag ctmp0 f ctm 0 o/ p pin ( ct 0oc =1 ) ct 0on pwm duty cycle set by ccra pwm period set by ccrp pwm mode ? ct 0 dpx = 0 counter stop if ct 0on bit low counter reset when ct 0on returns high pwm resumes operation output controlled by other pin-shared function time ct0 dpx = 0; ct0 m [1: 0]=10 ct 0 pol output inverts when ct0 pol = 1 ct 0 pau resume pause ctm 0 o/ p pin ( ct 0oc = 0) note: 1. here ct0 dpx = 0 - counter cleared by ccrp 2. a c ounter c lear sets pwm period 3. the i nternal pwm function continues running even when ct0 io[1:0] = 00 or 01 4. the c t0 cclr bit has no infuence on pwm operation
rev. 1.40 8? de?e??e? 0?? ?01? rev. 1.40 87 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver ccra ccrp counter value counter cleared by ccra ccrp int . flag ctmp0 f ccra int . flag ctma0 f ctm 0 o/ p pin ( ct 0 oc =1 ) ct 0 on pwm duty cycle set by ccrp pwm period set by ccra pwm mode ? ct 0 dpx = 1 counter stop if ct 0on bit low counter reset when ct 0on returns high pwm resumes operation output controlled by other pin-shared function time ct0 dpx =1 ; ct0 m [1: 0]=10 ct 0 pol output inverts when ct0 pol = 1 ct 0 pau resume pause ctm 0 o/ p pin ( ct 0 oc = 0) note: 1. here ct 0 dpx = 1 - counter cleared by ccra 2. a counter clear sets pwm period 3. the internal pwm function continues even when ct 0 io[1:0] = 00 or 01 4. the ct 0 cclr bit has no infuence on pwm operation
rev. 1.40 88 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 89 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver periodic type tm C ptm 1 & ptm2 the pe riodic t ype t m c ontains fv e o perating m odes, wh ich a re c ompare ma tch ou tput, t imer/ event counter , capture input, single pulse output and pwm output modes. the periodic tm can be controlled with two external input pin s and can drive two external output pin s.
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? ??? ?? ? ??? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? note: 1. ptpnb is the inverse signal of ptpn. 2. for the bs86b12a-3 device, the ptp2i pin source can be selected using the ifs register. periodic type tm block diagram (n= 1 or 2) periodic tm operation at the core is a 10 count-up counter which is driven by a user selectable internal or external clock source. t here a re a lso t wo i nternal c omparators wi th t he na mes, com parator a a nd com parator p. t hese c omparators wi ll c ompare t he v alue i n t he c ounter wi th c crp a nd c cra r egisters. t he ccrp comparator is 10 -bit wide . the only way of changing the value of the 10 -bit counter using the application program, is to clear the counter by changing the ptnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when t hese c onditions occ ur, a pt m i nterrupt si gnal wi ll a lso usua lly be ge nerated. t he p eriodic type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control more than one output pin. all operating setup conditions are selected using relevant internal registers.
rev. 1.40 88 de?e??e? 0?? ?01? rev. 1.40 89 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver periodic type tm register description overall operation of the p eriodic t ype tm is controlled using a series of registers. a read only register pair exists to store the intern al counter 10 -bit value, while two read/write register pair s exist to store the intern al 10 -bit ccra value and ccrp value . the remain ing two registers are control registers which setup the different operating and control modes. register name bit 7 6 5 4 3 2 1 0 ptmnc0 p tnpau p tnck ? ptnck1 ptnck0 ptnon ptmnc1 ptnm1 ptnm0 ptnio1 ptnio0 ptnoc ptnpol ptncapts ptncclr ptmndl d7 d ? d ? d4 d3 d ? d1 d0 ptmndh d9 d8 ptmnal d7 d ? d ? d4 d3 d ? d1 d0 ptmnah d9 d8 ptmnrpl d7 d ? d ? d4 d3 d ? d1 d0 ptmnrph d9 d8 10-bit periodic tm register list (n= 1 or 2) ptmnc0 register bit 7 6 5 4 3 2 1 0 na ? e ptn pau ptn ck ? ptnck1 ptnck0 ptnon r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 b it 7 ptn pau : ptmn counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal c ounter ope ration. w hen i n a pa use c ondition t he p tm wi ll re main powe red up a nd c ontinue t o c onsume po wer. t he c ounter wi ll re tain i ts re sidual va lue whe n this bit changes from low to high and resume counting from this value when the bit changes to a low value again. b it 6 ~ 4 ptnck2 ~ ptnck0 : select ptmn counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f sub 101: f sub 110: ptckn rising edge clock 111: ptckn falling edge clock these three bits are used to select the clock source for the p tm. the external pin clock source can be chosen to be active on the rasing or falling edge. the clock source f sys is the system clock, while f h and f sub are other internal clocks, the details of which can be found in the oscillator section.
rev. 1.40 90 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 91 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver b it 3 ptnon : ptmn counter on/off control 0: off 1: on this bit controls the overall on/of f function of the p tm. setting the bit high enables the counter to run, clearing the bit disables the p tm. clearing this bit to zero will stop the counter from counting and turn of f the p tm which will reduce its power consumption. when the bit changes state from low to high the interna l counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high again. if the p tm is in the compare match output mode , pwm output mode or single pulse output mode then the p tm output pin will be reset to its initial conditi on, as specifed by the ptnoc bit, when the ptn on bit changes from low to high. b it 2 ~ 0 unimplemented, read as 0 ptmnc1 register bit 7 6 5 4 3 2 1 0 na ? e ptnm1 ptnm0 ptnio1 ptnio0 ptnoc ptnpol ptncapts ptncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 6 ptnm1~ptnm0 : select ptmn operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: t imer/counter mode these bit s se tup t he required operat ing mode for t he p tm. t o ensure rel iable operation the p tm should be switched of f before any changes are made to the bits. in the t imer/counter mode, the p tm output pin state is undefned . b it 5 ~ 4 ptnio1~ptnio0 : select ptpn output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of ptpni or ptckn 01: input capture at falling edge of ptpni or ptckn 10: input capture at falling/rising edge of ptpni or ptckn 11: input capture disabled timer/counter mode: unused these two bits are used to determi ne how the p tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the p tm is running.
rev. 1.40 90 de?e??e? 0?? ?01? rev. 1.40 91 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver in the compare match output mode, the p t n io1 ~p t n io0 bits determine how the p tm output pin changes state when a compare match occurs from the comparator a. the p tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the p t n io1~p t n io0 bits are both zero, then no change will take place on the output. the initial value of the p tm output pin should be setup using the ptnoc bit in the ptmnc1 regis ter . n ote that the output level reques ted by the p t n io1 ~p t n io0 bits must be di fferent from t he i nitial va lue se tup usi ng t he ptnoc bi t ot herwise no change w ill occur on the p tm output pin when a compare match occurs . a fter the p tm output pin changes state it can be reset to its initial level by changing the level of the ptnon bit from low to high. in t he pw m mod e, t he p t n io1 a nd p t n io0 bi ts de termine ho w t he p tm ou tput pin changes state when a certain compare match condition occurs. the pwm output function i s m odifed b y changing t hese t wo b its. i t i s n ecessary t o c hange t he v alues o f the ptn io1 and ptn io0 bits only after the p tm has been switched of f. unpredictable pwm outputs will occur if the ptn io1 and p tn io0 bits are changed when the p tm is running . b it 3 ptnoc : ptpn output control bit compare match output mode 0: i nitial low 1: i nitial high pwm mode/ single pulse output mode 0: active low 1: active high this is the output control bit for the p tm output pin. its operation depends upon whether p tm i s b eing u sed i n t he c ompare ma tch ou tput mo de o r i n t he pw m mode/ single pulse output mode. it has no ef fect if the p tm is in the t imer/counter mode. in the compare match output mode it determines the logic level of the p tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. b it 2 ptnpol : ptpn output polarity control 0: non-invert 1: invert this bit controls the polarity of the ptm output pin. when the bit is set high the p tm output pin will be inverted and not inverted when the bit is zero. it has no ef fect if the p tm is in the t imer/counter mode. b it 1 ptncapts : ptmn capture trigger source select 0: from ptpni 1: from ptckn b it 0 ptncclr : select ptmn counter clear condition 0: p tm comparatror p match 1: p tm comparatror a match this b it i s u sed t o se lect t he m ethod wh ich c lears t he c ounter. r emember t hat t he periodic t m c ontains t wo c omparators, com parator a a nd com parator p , e ither of which can be selected to clear the internal counter . w ith the p t n cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare mat ch occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the ptn cclr bit is not used in the pwm, single pulse or input capture mode.
rev. 1.40 9 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 93 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver p tmn dl register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d ? d4 d3 d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 b it 7 ~ 0 ptmn counter low byte register bit 7 ~ bit 0 ptmn 1 0 -bit counter bit 7 ~ bit 0 ptmndh register bit 7 6 5 4 3 2 1 0 na ? e d9 d8 r/w r r por 0 0 bit 7 ~ 2 unimplemented, read as 0 b it 1 ~ 0 ptmn counter high byte register bit 1 ~ bit 0 ptmn 1 0 -bit counter bit 9 ~ bit 8 ptmn al register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d ? d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 0 ptmn ccra low byte register bit 7 ~ bit 0 ptmn 1 0 -bit ccra bit 7 ~ bit 0 ptmnah register bit 7 6 5 4 3 2 1 0 na ? e d9 d8 r/w r/w r/w por 0 0 bit 7 ~ 2 unimplemented, read as 0 b it 1 ~ 0 ptmn ccra high byte register bit 1 ~ bit 0 ptmn 1 0 -bit ccra bit 9 ~ bit 8 ptmnrp l register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d ? d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 0 ptmn ccr p low byte register bit 7 ~ bit 0 ptmn 1 0 -bit ccrp bit 7 ~ bit 0
rev. 1.40 9? de?e??e? 0?? ?01? rev. 1.40 93 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver ptmnrph register bit 7 6 5 4 3 2 1 0 na ? e d9 d8 r/w r/w r/w por 0 0 bit 7 ~ 2 unimplemented, read as 0 b it 1 ~ 0 ptmn ccr p high byte register bit 1 ~ bit 0 ptmn 1 0 -bit ccrp bit 9 ~ bit 8 periodic type tm operating modes the p eriodic type tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or t imer/counter mode. the operating mode is selected using the ptnm1 and ptnm0 bits in the ptmnc1 register. compare match output mode to select this mode, bits ptnm1 and ptnm0 in the ptmnc1 register , should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare match from comparator a and a compare match from comparator p . when the ptncclr bit is low , there are two ways in which the counter can be cleared. one is when a compare match from comparator p , the other is when the ccrp bits are all zero which allows the counter to overfow . here both ptman f and ptmpn f interrupt request fags for comparator a and comparator p respectively, will both be generated. if the ptncclr bit in the ptmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the p t m a n f interrupt request fag will be generated e ven i f t he va lue of t he ccrp bi ts i s l ess t han t hat of t he ccra re gisters. t herefore when ptncclr is high no ptmpn f interrupt request fag will be generated. in the compare match output mode, the ccra can not be cleared to zero . if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the p tmanf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the ptm output pin, will change state. the ptm output pin condition however only changes state when a ptman f interrupt request fag is generated after a compare match occurs from comparator a. the ptmpn f interrupt request fag, g enerated f rom a c ompare m atch o ccurs f rom c omparator p , wi ll h ave n o e ffect o n t he pt m output pin. the way in which the ptm output pin changes state are determined by the condition of the ptnio1 and ptnio0 bits in the ptmnc1 register . the ptm output pin can be selected using the ptnio1 and ptnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the ptm output pin, which is setup afte r the ptnon bit changes from low to high, is setup using the ptnoc bit. note that if the ptnio1 and ptnio0 bits are zero then no pin change will take place.
rev. 1.40 94 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 9? de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver counte? value 0x3 ff ccrp ccra ptnon ptnpau ptnpol ccrp int . flag ptmpnf ccra int . flag ptmanf ptm n o/ p pin ti?e ccrp =0 ccrp > 0 counte? ove?flow ccrp > 0 counte? ?lea?ed ?y ccrp value pause resu?e stop counte? resta?t ptncclr = 0 ; ptnm [1:0 ] = 00 output pin set to initial level low if ptnoc =0 output toggle with ptmanf flag note ptnio [1:0 ] = 10 a?tive high output sele?t he?e ptnio [1:0 ] = 11 toggle output sele?t output not affe?ted ?y ptmanf flag . re?ains high until ?eset ?y ptnon ?it output pin reset to initial value output inve?ts when ptnpol is high un- defined compare match output mode C ptncclr=0 note: 1. w ith ptncclr=0 a comparator p match will clear the counter 2. the ptm output pin is controlled only by the ptmanf fag 3. the output pin is reset to itsinitial state by a ptnon bit rising edge 4. n = 1 or 2
rev. 1.40 94 de?e??e? 0?? ?01? rev. 1.40 9 ? de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver counte? value 0x3 ff ccrp ccra ptnon ptnpau ptnpol ccrp int . flag ptmpnf ccra int . flag ptmanf ptm n o/ p pin ti?e ccra =0 ccra = 0 counte? ove?flow ccra > 0 counte? ?lea?ed ?y ccra value pause resu?e stop counte? resta?t ptncclr = 1 ; ptnm [1:0 ] = 00 output pin set to initial level low if ptnoc =0 output toggle with ptmanf flag note ptnio [1:0 ] = 10 a?tive high output sele?t he?e ptnio [1:0 ] = 11 toggle output sele?t output not affe?ted ?y tnaf flag . re?ains high until ?eset ?y ptnon ?it output pin reset to initial value output ?ont?olled ?y othe? pin - sha?ed fun?tion output inve?ts when ptnpol is high ptmpnf not gene?ated no ptmanf flag gene?ated on ccra ove?flow output does not ?hange compare match output mode C ptncclr=1 note: 1. w ith ptncclr=1 a comparator a match will clear the counter 2. the ptm output pin is controlled only by the ptmanf fag 3. the output pin is reset to its initial state by a ptnon bit rising edge 4. a ptmpnf fag is not generated when ptncclr=1 5. n = 1 or 2
rev. 1.40 9 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 97 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver timer/counter mode to se lect t his m ode, bi ts pt nm1 a nd pt nm0 i n t he pt mnc1 regi ster shoul d be se t t o 1 1 respectively. the t imer/counter mode operates in an identical way to the compare match output mode generating the same interrupt flags. the exception is that in the t imer/counter mode the ptm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. pwm output mode to select this mode, bits ptnm1 and ptnm0 in the ptmnc1 register should be set to 10 respectively. the pwm function within the ptm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fixed frequency but of varying duty cycle on the ptm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extre mely fexible. in the pwm output mode, the ptncclr bit has no ef fect on the pwm operation . both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the ptnoc bit in the ptmnc1 register is used to select the required polarity of the pwm waveform while the two ptnio1 and ptnio0 bits are used to enable the p wm output or to force the p tm output pin to a f xed high or low level. the ptnpol bit is used to reverse the polarity of the pwm output waveform. ? 10-bit ptm, pwm mode, edge-aligned mode ccrp 1~1023 0 pe ? iod 1~10 ? 3 10 ? 4 duty ccra if f sys = 16 mhz, ptmn clock source select f sys /4, ccrp = 512 and ccra = 128, the ptm n pwm output frequency = (f sys /4) / 512 = f sys /2048 = 7.8125 khz, duty = 128/512 = 25%, if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%.
rev. 1.40 9? de?e??e? 0?? ?01? rev. 1.40 97 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver counte? value ccrp ccra ptnon ptnpau ptnpol ccrp int . flag ptmpnf ccra int . flag ptmanf ptm n o/ p pin ( ptnoc =1) ti?e counte? ?lea?ed ?y ccrp pause resu?e counte? stop if ptnon ?it low counte? reset when ptnon ?etu?ns high ptnm [1:0 ] = 10 pwm duty cy?le set ?y ccra pwm ?esu?es ope?ation output ?ont?olled ?y othe? pin - sha?ed fun?tion output inve?ts when ptnpol = 1 pwm pe?iod set ?y ccrp ptm n o/ p pin ( ptnoc =0) pwm output mode note: 1. a counter clear sets the pwm period 2. the internal pwm function continues running even when ptnio [1:0] = 00 or 01 3. the ptncclr bit has no infuence on pwm operation 4. n = 1 or 2
rev. 1.40 98 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 99 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver single pulse mode to select this mode, bits ptnm1 and ptnm0 in the ptmnc1 register should be set to 10 respectively and also the ptnio1 and ptnio0 bits should be set to 11 respectively. the single pulse output mode, as the name suggests, will generate a single shot pulse on the ptm output pin. the trigge r for the pul se out put le ading edge is a low to high transiti on of the ptnon bit, which can be implement ed using the application program. however in the single pulse mode, the ptnon bit can als o be made to automatically change from low to high us ing the external p tckn pin, which will in turn initiate the single pulse output. when the ptnon bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the ptnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the ptnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the ptnon bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a ptm interrupt. the counter can o nly b e r eset b ack t o z ero wh en t he pt non b it c hanges f rom l ow t o h igh wh en t he c ounter restarts. in the single pulse mode ccrp is not used. the ptncclr bit is not used in this mode.

? ? ? ? ? ? ? ? ??? single pulse generation (n= 1 or 2)
rev. 1.40 98 de?e??e? 0?? ?01? rev. 1.40 99 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver counte? value ccrp ccra ptnon ptnpau ptnpol ccrp int . flag ptmpnf ccra int . flag ptmanf ptm n o/ p pin ( ptnoc =1) ti?e counte? stopped ?y ccra pause resu?e counte? stops ?y softwa?e counte? reset when ptnon ?etu?ns high ptnm [1:0 ] = 10 ; ptnio [1:0 ] = 11 pulse width set ?y ccra output inve?ts when ptnpol = 1 no ccrp inte??upts gene?ated ptm n o/ p pin ( ptnoc =0) ptckn pin softwa?e t?igge? clea?ed ?y ccra ?at?h ptckn pin t?igge? auto. set ?y ptckn pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse is triggered by the ptckn pin or by setting the ptnon bit high 4. a ptckn pin active edge will automatically set the ptnon bit hight 5. in the single pulse mode, ptnio [1:0] must be set to 11 and can not be changed. 6. n = 1 or 2
rev. 1.40 100 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 101 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver capture input mode to select this mode bits ptnm1 and ptnm0 in the ptmnc1 register should be set to 01 respectively. this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the external signal is suppl ied on the pt p ni or pt ckn pin whic h is sel ected using the pt ncapts bit in the ptmnc1 register . the input pin active edge can be either a rising edge, a falling edge or both rising and fallin g edges; the active edge transition type is selected using the ptnio1 and ptnio0 bits in the ptmnc1 register. the counter is started when the ptnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the ptp ni or ptckn pin the present value in the counter will be lat ched into the ccra registers and a ptm interrupt generated. irrespective of what events oc cur on t he pt p ni or pt ckn pi n , t he c ounter wi ll c ontinue t o fre e run unt il t he pt non bit changes from high to low . when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p , a p tm interrupt w ill als o be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the ptnio1 and ptnio0 bits can select the acti ve trigger edge on the ptp ni or ptckn pin to be a rising edge, falling edge or both edge types. if the ptnio1 and ptnio0 bits are both set high, then no capture operation will take place irrespective of what happens on the ptp ni or ptckn pin, however it must be noted that the counter will continue to run. as the ptpni or p tckn pin is pin shared with other functions, care must be taken if the p tmn is in the capture input mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the p tncclr, p tnoc and p tnpol bits are not used in this mode.
rev. 1.40 100 de?e??e? 0?? ?01? rev. 1.40 101 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver counte? value yy ccrp ptn on ptn pau ccrp int . flag ptmpnf ccra int . flag ptmanf ccra value ti?e counte? ?lea?ed ?y ccrp pause resu?e counte? reset ptn m [1:0 ] = 01 p tm n ?aptu?e pin p tpn i o? ptckn xx counte? stop ptn io [1:0 ] value xx yy xx yy a?tive edge a?tive edge a?tive edge 00 ? rising edge 01 ? falling edge 10 ? both edges 11 ? disa?le captu?e capture input mode note: 1. ptnm [1:0] = 01 and active edge set by the ptnio [1:0] bits 2. a ptm capture input pin active edge transfers the counter value to ccra 3. ptncclr bit not used 4. no output function C ptnoc and ptnpol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero. 6. n = 1 or 2
rev. 1.40 10 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 103 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however , to properly process these signals by a microcontroller , they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller , the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview the device s contain a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. device input channels a/d channel select bits input pins bs8 ? b1 ? a-3 8 acs4 ? acs ? ~ acs0 an0~an7 bs8 ? c1 ? a-3 bs8 ? d ? 0a-3 the accompanying block diagram shows the overall internal structure of the a/d converter , together with its associated registers.
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? ?? ? ? ? ? ? ? ? ? ??? ? a/d converter structure a/d converter register description overall operation of the a /d converter is controlled us ing fve regis ters. a read only regis ter pair exists to store the a / d c onverter data 12-bit value. the remaining three registers are control registers which setup the operating and control function of the a/d converter. name bit 7 6 5 4 3 2 1 0 adrl(adrfs=0) d3 d ? d1 d0 adrl(adrfs=1) d7 d ? d ? d4 d3 d ? d1 d0 adrh(adrfs=0) d11 d10 d9 d8 d7 d ? d ? d4 adrh(adrfs=1) d11 d10 d9 d8 adcr0 start eocb adoff adrfs acs ? acs1 acs0 adcr1 acs4 v109en vrefs adck ? adck1 adck0 acerl ace7 ace ? ace ? ace4 ace3 ace ? ace1 ace0 a/d converter register list
rev. 1.40 10? de?e??e? 0?? ?01? rev. 1.40 103 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver a/d converter data registers C adrl, adrh as the devices contain an internal 12-bit a/d converter , it require s two data registers to store the converted va lue. t hese a re a hi gh byt e re gister, kno wn a s adr h, a nd a l ow by te re gister, kno wn as adrl. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digiti z ed conversion value. as only 12 bits of the 16-bit register space is ut ili z ed, t he form at i n whi ch t he da ta i s st ored i s c ontrolled by t he adrfs bi t i n t he adcr0 register as shown in the accompany ing table. d0~d1 1 are the a/d conversion result data bits. any unused bits will be read as zero. adrfs adrh adrl 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 d11 d10 d9 d8 d7 d ? d ? d4 d3 d ? d1 d0 0 0 0 0 1 0 0 0 0 d11 d10 d9 d8 d7 d ? d ? d4 d3 d ? d1 d0 a/d data registers a/d converter control registers C adcr0, adcr1, acerl to control the function and operation of the a/d converter, three control registers known as adcr0, adcr1, acerl are provided. these 8-bit registers defne functions such as the selection of which analog channel is connected to the internal a/d converter , the digiti z ed data format, the a/d clock source as well as controlling the start function and monitoring the a/d converter end of conversion status. t he acs 2 ~acs0 bi ts i n t he adcr0 re gister a nd acs4 bi t i s t he adcr1 re gister de fne the a / d c onverter input channel number . as the device s contain only one actual analog to di gital converter hardware circuit, each of the individual 8 analog inputs must be routed to the converter . it is the function of the acs4 and acs 2 ~ acs0 bits to determine which analog channel input signals or internal 1. 0 9v is actually connected to the internal a/d converter. the acerl control register contains the ace 7 ~ace0 bits which determine which pins on port c are used as analog inputs for the a/d converter input and which pins are not to be used as the a/d converter input. setting the corresponding bit high will select the a/d input function, clearing the bit to zero will select either the i/o or other pin-shared function. when the pin is selected to be an a/d input, its original function whether it is an i/o or other pin-shared function will be removed. in addition, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an a/d input. adcr0 register bit 7 6 5 4 3 2 1 0 na ? e start eocb adoff adrfs acs ? acs1 acs0 r/w r/w r r/w r/w r/w r/w r/w por 0 1 1 0 0 0 0 bit 7 start : start the a/d conversion 0-->1-->0: start 0-->1 : reset the a/d converter and set eocb to 1 this bi t i s use d t o i nitiate a n a/ d c onversion proc ess. t he bi t i s norm ally l ow but if s et high and then cleared low again, the a /d converter w ill initiate a convers ion process. when the bit is set high the a/d converter will be reset. bit 6 eocb : end of a/d conversion fag 0: a/d conversion ended 1: a/d conversion in progress this read only fag is used to indicate when an a/d conversion process has completed. when the conversion process is running the bit will be high.
rev. 1.40 104 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 10? de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bit 5 adoff : a/d converter module power on/off control bit 0: a /d converter module power on 1: a /d c onverter module power off this bit controls the power to the a/d internal function. this bit should be cleared to zero to enable the a/d converter . if the bit is set high then the a/d converter will be switched of f reducing the device power consumption. as the a/d converter will consume a limited amount of power , even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. note: 1. it is recommended to set adoff=1 before entering idle/sleep mode for saving power. 2. adoff=1 will power down the a/d converter module. bit 4 adrfs : a/d converter data format control 0: a /d converter data msb is adrh bit 7, lsb is adrl bit 4 1: a /d converter data msb is adrh bit 3, lsb is adrl bit 0 this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d data register section. bit 3 unimplemented, read as 0 bit 2 ~ 0 acs2 ~ acs0 : select a/d channel (when acs4 is 0) 0 00: an0 00 1: an1 0 10: an2 0 11: an3 100: an4 101: an5 110: an6 111: an7 these are the a/d channel select control bits. as there is only one internal hardware a/d converter each of the eight a/d input s must be routed to the internal converter using these bits. if bit acs4 in the adcr1 register is set high then the internal 1. 0 9v will be routed to the a/d converter. adcr1 register bit 7 6 5 4 3 2 1 0 na ? e acs4 v109en vrefs adck ? adck1 adck0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 acs4 : select internal 1. 0 9v as a/d converter input control 0: disable 1: enable this bit enables 1. 0 9v to be connected to the a/d converter . the v1 0 9en bit must frst have been set to enable the bandgap circuit 1. 0 9v voltage to be used by the a/d converter. when the acs4 bit is set high, the bandgap 1. 0 9v voltage will be routed to the a/d converter and the other a/d input channels disconnected. bit 6 v1 09en : internal 1. 0 9v control 0: disable 1: enable this bit controls the internal bandgap circuit on/of f function to the a/d converter . when the bit is set high the bandgap 1. 0 9v voltage can be used by the a/d converter . if 1. 0 9v is not used by the a/d converter and the l vr function is disabled then the bandgap reference circuit will be automatically switched of f to conserve power . when 1.0 9v is switched on for use by the a/d converter, a time t bg should be allowed for the bandgap circuit to stabilise before implementing an a/d conversion. bit 5 unimplemented, read as 0
rev. 1.40 104 de?e??e? 0?? ?01? rev. 1.40 10 ? de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bit 4 vrefs : select a/d converter reference voltage 0: internal a /d converter power 1: v ref pin this bit is used to select the reference voltage for the a/d converter . if the bit is high then the a/d converter reference voltage is supplied on the external vref pin. if the pin is low then the internal referenc e is used which is taken from the power supply pin vdd. bit 3 unimplemented, read as 0 bit 2 ~ 0 adck2 ~ adck0 : select a/d converter clock source 000: f sys 001: f sys /2 010: f sys /4 011: f sys /8 100: f sys /16 101: f sys /32 110: f sys /64 111: undefned these three bits are used to select the clock source for the a/d converter. acerl register bit 7 6 5 4 3 2 1 0 na ? e ace7 ace ? ace ? ace4 ace3 ac e ? ace1 ace0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 ace7 : defne pc7 is a/d input or not 0: not a/d input 1: a/d input, an 7 bit 6 ace6 : defne pc6 is a/d input or not 0: not a/d input 1: a/d input, an 6 bit 5 ace5 : defne pc5 is a/d input or not 0: not a/d input 1: a/d input, an 5 bit 4 ace4 : defne pc4 is a/d input or not 0: not a/d input 1: a/d input, an 4 bit 3 ace3 : defne pc3 is a/d input or not 0: not a/d input 1: a/d input, an3 bit 2 ace2 : defne pc2 is a/d input or not 0: not a/d input 1: a/d input, an2 bit 1 ace1 : defne pc1 is a/d input or not 0: not a/d input 1: a/d input, an1 bit 0 ace0 : defne pc0 is a/d input or not 0: not a/d input 1: a/d input, an0
rev. 1.40 10 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 107 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver a/d operation the st art bit in the adcr0 register is used to start and reset the a/d converter . when the microcontroller se ts t his b it f rom l ow t o h igh a nd t hen l ow a gain, a n a nalog t o d igital c onversion c ycle will be initiated. when the st art bit is brought from low to high but not low again, the eocb bit in the adcr0 register will be set high and the analog to digital converter will be reset. it is the st art bit that is used to control the overall start operation of the internal analog to digital converter. the eocb bit in the adcr0 register is used to indicate when the analog to digital conversion process is complete. this bit w ill be automatically s et to 0 by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request fag will be set in t he i nterrupt c ontrol r egister, a nd i f t he i nterrupts a re e nabled, a n a ppropriate i nternal i nterrupt signal wil l be generated. thi s a/ d i nternal int errupt si gnal wi ll direct the progra m flow t o t he associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter , which originates from the system clock f sys , can be chosen to be either f sys or a subdivided version of f sys . the division ratio value is determined by the adck2~adck0 bits in the adcr1 register. although t he a/ d c lock sourc e i s de termined by t he syst em c lock f sys , a nd by bi ts adck2~adck0, there are some limitations on the maximum a/d clock source speed that can be selected. as the minimum value of permissible a/d clock period, t adck , is from 0.5s to 10 s, care must be taken for system clock frequencies. for example, if the system clock operates at a frequency of 4mhz, the adck2~adck0 bits should not be set to 000b or 1 10b . doing so will give a/d clock p eriods t hat a re l ess t han t he m inimum a/ d c lock p eriod o r g reater t han t he m aximum a/ d clock period which may result in inaccurate a/d conversion values. refer t o t he fol lowing t able for e xamples, wh ere va lues m arked wi th a n a sterisk * sh ow whe re, depending upon the device, special care must be taken, as the values may be less than the specifed minimum a/d clock period. f sys a/d clock period (t adck ) adck2, adck1, adck0 =000 (f sys ) adck2, adck1, adck0 =001 (f sys /2) adck2, adck1, adck0 =010 (f sys /4) adck2, adck1, adck0 =011 (f sys /8) adck2, adck1, adck0 =100 (f sys /16) adck2, adck1, adck0 =101 (f sys /32) adck2, adck1, adck0 =110 (f sys /64) adck2, adck1, adck0 =111 1mhz 1s ? s 4s 8s 1 ? s* 3 ? s* ? 4 s* 8qghqhg ? mhz ? 00ns 1s ? s 4s 8s 1 ? s* 3 ? s* 8qghqhg 4mhz ?? 0ns* ? 00ns 1s ? s 4s 8s 1 ? s* 8qghqhg 8mhz 1 ?? ns* ?? 0ns* ? 00ns 1s ? s 4s 8s 8qghqhg 1 ? mhz 83ns* 1 ? 7ns* 333ns* ?? 7ns 1.33s ? . ? 7 s ? .33 s 8qghqhg 1 ? mhz ?? . ? ns* 1 ?? ns* ?? 0ns* ? 00ns 1s ? s 4s 8qghqhg a/d clock period examples controlling t he powe r on/ off func tion of t he a/ d c onverter c ircuitry i s i mplemented usi ng t he adoff bit in the adcr0 register . this bit must be zero to power on the a/d converter . when the adoff bi t i s c leared t o z ero t o powe r on t he a/ d c onverter i nternal c ircuitry a c ertain de lay, a s indicated in the timing diagram, must be allowed before an a/d conversion is initiated. even if no pins are selected for use as a/d inputs by clearing the ace 7 ~ace0 bits in the acerl register , if the adoff bit is zero then some power will still be consumed. in power conscious applications it is therefore recommended that the adoff is set high to reduce power consumption when the a/d converter function is not being used.
rev. 1.40 10? de?e??e? 0?? ?01? rev. 1.40 107 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver the reference voltage supply to the a/d converter can be supplied from either the positive power supply pin, vdd, or from an external reference sources supplied on pin vref . the desired selection is made using the vrefs bit. as the vref pin is pin-shared with other functions, when the vrefs bit is set high, the vref pin function will be selected and the other pin functions will be disabled automatically. a/d input pins all of the a/d analog input pins are pin-shared with the i/o pins on port c as well as other functions. the ace 7 ~ace0 bits in the acerl register , determine whether the input pins are setup as a/d converter analog inputs or whether they have othe r functions. if the ace 7 ~ace0 bits for its corres ponding pin is s et high then the pin w ill be s etup to be an a /d converter input and the original pin functions will be disabled. in this w ay, pins can be changed under program control to change t heir func tion be tween a/ d i nputs a nd ot her func tions. al l pul l-high re sistors, whi ch a re setup through register programming, will be automatically disconnecte d if the pins are setup as a/ d inputs. note that it is not necessary to frst setup the a/d pin as an input in the p c c port control register to enable the a/d input as when the ace 7 ~ace0 bits enable an a/d input, the status of the port control register will be overridden. the a/d converter has its own reference voltage pin, vref , however the reference voltage can also be supplied from the power supply pin, a choice which is made through the vrefs bit in the adcr1 register. the analog input values must not be allowed to exceed the value of v ref .
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? ? - a/d input structure
rev. 1.40 108 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 109 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/ d conversion process. ? step 1 select the required a/d conversion clock by correctly programming bits adck2~adck0 in the adcr1 register. ? step 2 enable the a/d by clearing the adoff bit in the adcr0 register to zero. ? step 3 select which channel is to be connected to the internal a/d converter by correctly programming the acs4 , acs2 ~acs0 bits which are also contained in the adcr1 and adcr0 register s. ? step 4 select which pins are to be used as a/d inputs and confgure them by correctly programming the ace7 ~ace0 bits in the acerl register. ? step 5 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master interr upt control bit, emi, and the a/d converter interrupt bit, ade , must both be set high to do this. ? step 6 the analog to digital conversion process can now be initialised by setting the st art bit in the adcr 0 register from low to high and then low again. note that this bit should have been originally cleared to zero. ? step 7 to check when the analog to digital conversion proc ess is complete, the eocb bit in the adcr0 register can be polled. the conversion process is complete when this bit goes low . when this occurs the a/d data registers adrl and adrh can be read to obtain the conversion value. as an alternative method , if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur. note: when check ing for the end of the conversion process, if the method of polling the eocb bit in the adcr0 register is used, the interrupt enable step above can be omitted. the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware w ill begin to carry out the conversion, d uring wh ich t ime t he p rogram c an c ontinue wi th o ther f unctions. t he t ime t aken f or t he a/d conversion is 16 t adck where t adck is equal to the a/d clock period.
rev. 1.40 108 de?e??e? 0?? ?01? rev. 1.40 109 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver

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? ? ? - ? ? ? ? ? ? ? ? ? ?- ? a/d conversion timing programming considerations during m icrocontroller ope rations where t he a/d c onverter i s not be ing used, t he a/d i nternal circuitry can be switched of f to reduce power consumption, by setting bit adoff high in the adcr0 r egister. w hen t his h appens, t he i nternal a/ d c onverter c ircuits wi ll n ot c onsume p ower irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. a/d transfer function as the device contain s a 12-bit a/d converter , its full-scale converted digiti z ed value is equal to fffh. since the full-scale analog input value is equal to the v dd or v ref voltage, this gives a single bit analog input value of v dd or v ref divided by 4096. 1 lsb= (v dd or v ref ) / 4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage = a/d output digital value (v dd or v ref ) / 4096 the diagram shows the ideal transfer function between the analog input value and the digitised output val ue for t he a/ d conve rter. e xcept for t he di gitised ze ro val ue, t he subsequent digi tised values will change at a point 0.5 lsb below where they would change without the of fset, and the last full scale digiti z ed value will change at a point 1.5 lsb below the v dd or v ref level.

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? ideal a/d transfer function
rev. 1.40 110 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 111 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver a/d programming example s the following two programming examples illustrate how to setup and implement an a/d conversion. in the frst example, the method of polling the eocb bit in the adcr0 register is used to det ect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an eocb polling method to detect the end of conversion fou ( glvdeoh&ryhuwhulwhuuxsw mov a ,03h 5d hhf 66 dffdlfk f 2 d k h5fhl1a1 5d mov a ,01h 5d hdehdfhf1fkdhfhh : dbfhl f 6 5 klkhdlllldhfhl h 6 5 hh f 6 5 d lb2 ] 2 kh5hlh2lhhfhfhl lb2 flhl d 5 hdehfhlhdh 5behd dhhhhhhlh d 5+ hdklkehfhlhdh 5+behd dhhhhhhlh : : dbfhl dh[fhl
rev. 1.40 110 de?e??e? 0?? ?01? rev. 1.40 111 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver example: using the interrupt method to detect the end of conversion clr a de ; disable a/d converter interrupt mov a ,03h mov a dcr1,a ; select f sys /8 as a/d clock and switch off 1.09v clr a doff mov a ,0fh ; setup acerl to confgure pins an0~an3 mov ac erl,a mov a ,01h mov a dcr0,a ; enable and connect an0 channel to a/d converter start_conversion: clr st art ; high pulse on start bit to initiate conversion set s tart ; reset a/d clr s tart ; start a/d clr a df ; clear a/d converter interrupt request fag set a de ; enable a/d converter interrupt set e mi ; enable global interrupt : : ; a/d converter interrupt service routine adc_isr: mov ac c_stack,a ; save acc to user defned memory mov a ,status mov s tatus_stack,a ; save status to user defned memory : : mov a ,adrl ; read low byte conversion result value mov a drl_buffer,a ; save result to user defned register mov a ,adrh ; read high byte conversion result value mov a drh_buffer,a ; save result to user defned register : : exit_int_isr: mov a ,status_stack mov s tatus,a ; restore status from user defned memory mov a ,acc_stack ; restore acc from user defned memory reti
rev. 1.40 11 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 113 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver touch key function each device provides multiple touch key functions. the touch key function is fully integrated and requires no external components, allowing touch key functions to be implemented by the simple manipulation of internal registers. touch key structure the touch keys are pin shared with the p a ~ p d logic i/o pins, with the desired function chosen via register bits. keys are or ganised into several groups , with each group known as a module and having a module number , m0 to m n . each module is a fully independent set of four t ouch keys and each t ouch key has its own oscillator . each module contains its own control logic circuits and register set. examination of the register names will reveal the module number it is referring to. device keys - n touch key module touch key shared i/o pin bs8 ? b1 ? a-3 1 ? m0 key1~key4 pb0~pb3 m1 key ? ~key8 pb4~pb7 m ? key9~key1 ? pc0~pc3 bs8 ? c1 ? a-3 1 ? m0 key1~key4 pb0~pb3 m1 key ? ~k ey8 pb4~pb7 m ? key9~key 1 ? pc0~pc3 m3 key13~key 1 ? pc4~pc7 bs8 ? d ? 0a-3 ? 0 m0 key1~key4 pb0~pb3 m1 key ? ~k ey8 pb4~pb7 m ? key9~key 1 ? pd3 ? pd ?? pc0 ? pc1 m3 key13~key 1 ? pc ? ~pc ? m4 key17~key ? 0 pc ?? pc7 ? pa4 ? pa1 7rxfk.h?hjlvwhu'hqlwlrq each touch key module, which contains four touch key functions, has its own suite registers. the following table shows the register set for each touch key module. the mn within the register name refers to the t ouch key module number , the bs86b12a-3 has a ra nge of m0 to m2, the bs86c16a-3 has a range of m0 to m 3, the BS86D20A-3 has a range of m0 to m 4. name usage tktmr tou ? h key 8-bit ti ? e ? / ? ounte ? ? egiste ? tkc0 counte ? on-off and ? lea ? ? ont ? ol/ ? efe ? en ? e ? lo ? k ? ont ? ol/sta ? t bit tk 1 ? dl tou ? h key ? odule 1 ? -bit ? ounte ? low ? yte ? ontents tk 1 ? dh tou ? h key ? odule 1 ? -bit ? ounte ? high ? yte ? ontents tkc1 tou ? h key osc f ? equen ? y sele ? t tkmn1 ? d l module n 1 ? -bit ? ounte ? low ? yte ? ontents tkmn1 ? d h module n 1 ? -bit ? ounte ? high ? yte ? ontents tkmnrol refe ? en ? e osc inte ? nal ? apa ? ito ? sele ? t tkmnroh refe ? en ? e osc inte ? nal ? apa ? ito ? sele ? t tkmnc0 cont ? ol registe ? 0 multiplexe ? key sele ? t tkmnc1 cont ? ol registe ? 1 key os ? illato ? ? ont ? ol/refe ? en ? e os ? illato ? ? ont ? ol/ tou ? h key o ? i/o sele ? t register listing (n=0~4)
rev. 1.40 11 ? de?e??e? 0?? ?01? rev. 1.40 113 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver register name bit 7 6 5 4 3 2 1 0 tktmr d7 d ? d ? d4 d3 d ? d1 d0 tkc0 tkrcov tkst tkcfov tk1 ? ov tscs tk1 ? s1 tk1 ? s0 tk 1 ? dl d7 d ? d ? d4 d3 d ? d1 d0 tk 1 ? dh d 1 ? d14 d13 d 1 ? d11 d10 d9 d8 tkc1 tkfs1 tkfs0 tkm n1 ? dl d7 d ? d ? d4 d3 d ? d1 d0 tkm n1 ? dh d 1 ? d14 d13 d 1 ? d11 d10 d9 d8 tkmnrol d7 d ? d ? d4 d3 d ? d1 d0 tkmnroh d9 d8 tkmnc0 mnmxs1 mnmxs0 mndfen d4 mnsofc mn sof ? mnsof1 mnsof0 tkmnc1 mntss mnroen mnkoen mnk4io mnk3io mn k ? io mnk1io touch key module (n=0~4) tktmr register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d ? d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~0 touch key 8-bit timer/counter register time slot counter overfow set-up time is (256-tktmr[7:0])32 tkc0 register bit 7 6 5 4 3 2 1 0 na ? e tkrcov tkst tkcfov tk1 ? ov tscs tk1 ? s1 tk1 ? s0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 b it 7 unimplemented, read as 0 bit 6 tkrcov : t ime slot counter overfow fag 0: no overfow 1: overfow if module 0 or a ll module time slot counter , select ed by the tscs bit , is overfow , the touch key interrupt request fag , tkmf , will be set and all module key osc s and ref oscs auto stop. all module 16-bit c/f counter, 16-bit counter, 5-bit time slot counter and 8-bit time slot timer counter will be automatically switched off. b it 5 tkst : start t ouch key detection control bit 0: s topped 0->1: started in al l module s the 16-bit c/f count er, 16-bit count er, 5-bi t t ime sl ot count er wi ll be automatically cleared when this bit is cleared to zero (8-bit programmable time slot counter will not be cleared , which overflow time is setup by user ). when this bit changes from low to high , the 16-bit c/f counter , 16-bit counter , 5-bit time slot counter and 8-bit time slot timer counter will be automatically on and enable key osc and ref osc output clock input to these counter s. b it 4 tkcfov : t ouch key module 16-bit c/f counter overfow fag 0: not overfow 1: overfow when t he t ouch ke y m odule 1 6-bit c /f c ounter o verflows, t his b it wi ll b e se t t o 1 . as this fag will not be automatically cleared, it has to be cleared by the application program.
rev. 1.40 114 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 11 ? de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver b it 3 tk16ov : t ouch key module 16-bit counter overfow fag 0: not overfow 1: overfow when the touch key module 16-bit counter overfows, this bit will be set to 1. as this fag will not be automatically cleared, it has to be cleared by the application program. b it 2 tscs : t ouch key time slot counter select 0: each module uses its own time slot counter. 1: all t ouch key module use module 0 time slot counter. b it 1~0 tk16s1~ tk16s0 : t he touch key module 16-bit counter clock source s elect 00: f sys 01: f sys /2 10: f sys /4 11: f sys /8 tkc1 register bit 7 6 5 4 3 2 1 0 na ? e tkfs1 tkfs0 r/w r/w r/w por 1 1 b it 7 ~2 unimplemented, read as 0 bit 1~0 tk fs1~tkfs0 : t ouch key osc frequency select 00 : 500khz 01 : 1000 khz 10: 1500 khz 1 1 : 2000 khz tk16dl register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d ? d4 d3 d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 b it 7 ~0 touch key module 16-bit counter low byte contents tk16dh register bit 7 6 5 4 3 2 1 0 na ? e d 1 ? d14 d13 d 1 ? d11 d10 d9 d8 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 b it 7 ~0 touch key module 16-bit counter high byte contents tkmn16dl register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d ? d4 d3 d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 b it 7 ~0 module n 16-bit counter low byte contents
rev. 1.40 114 de?e??e? 0?? ?01? rev. 1.40 11 ? de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver tkmn16dh register bit 7 6 5 4 3 2 1 0 na ? e d 1 ? d14 d13 d 1 ? d11 d10 d9 d8 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 b it 7 ~0 module n 16-bit counter high byte contents tkmnrol register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d ? d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~0 reference osc inernal capacitor select osc inernal capacitor select : (tkmn ro[9:0] 50pf ) / 1024 tkmnroh register bit 7 6 5 4 3 2 1 0 na ? e d9 d8 r/w r/w r/w por 0 0 b it 7~2 unimplemented, read as 0 b it 1~0 reference osc inernal capacitor select osc inernal capacitor select: (tkmn ro[9:0] 50pf ) / 1024 tkmnc0 register bit 7 6 5 4 3 2 1 0 na ? e mnmxs1 mnmxs0 mndfen d4 mnsofc mn sof ? mnsof1 mnsof0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~6 mnmxs1 ~mnmxs0: multiplexer key select bit module number mnmxs1 mnmxs0 m0 m1 m2 m3 m4 0 0 key 1 key ? key 9 key 13 key 17 0 1 key ? key ? key 10 key 14 key 18 1 0 key 3 key 7 key 11 key 1 ? key 19 1 1 key 4 key 8 key 1 ? key 1 ? key ? 0 b it 5 mndfen : multi-frequency control 0: disable 1: enable b it 4 d4 : data bit for test only the bit is used for test purpose only and must be kept as 0 for normal operations. bit 3 mnsofc : c to f osc frequency hopping function control 0: the frequency hopping function is controlled by m nsof2 ~ m nsof 0 bits 1: the frequency hopping function is controlled by hardware regardless of what is the state of mnsof2~ m nsof 0 bits this bit is used to select the touch key oscillator frequency hopping function control method. when this bit is set to 1, the key oscillator frequency hopping function is controlled by the hardware circuit regardless of the mnsof2~mnsof0 bits value.
rev. 1.40 11 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 117 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bit 2~0 mnsof2~mnsof0 : touch key module n reference and key oscillators hopping frequency select 000: f hop0 C min. hopping frequency 001: f hop1 010: f hop2 011: f hop3 100: f hop4 C selected touch key oscillator frequency 101: f hop5 110: f hop6 111: f hop7 C max. hopping frequency tkmnc1 register bit 7 6 5 4 3 2 1 0 na ? e mntss mnroen mnkoen mnk4io mnk3io mnk ? io mnk1io r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 b it 7 mn tss: time slot counter clock select 0: reference oscillator 1: f sys /4 b it 6 unimplemented, read as 0 b it 5 mnroen : reference osc control 0: disable 1: enable b it 4 mnkoen : key osc control 0: disable 1: enable b it 3~0 mnk4io~ mnk1io : i/o p in or t ouch k ey f unction select mnk4io m0 m1 m2 m3 m4 pb3/key 4 pb7/key 8 pc3/key 12 or pc1/key 12 pc7/key 16 or pc5/key 16 pa1/key 20 0 i/o 1 tou ? h key mnk3io m0 m1 m2 m3 m4 pb2/key 3 pb6/key 7 pc2/key 11 or pc0/key 11 pc6/key15 or pc4/key 15 pa4/key 19 0 i/o 1 tou ? h key mnk2io m0 m1 m2 m3 m4 pb1/key 2 pb5/key 6 pc1/key 10 or pd2/key 10 pc5/key 14 or pc3/key 14 pc7/key 18 0 i/o 1 tou ? h key mnk1io m0 m1 m2 m3 m4 pb0/key 1 pb4/key 5 pc0/key 9 or pd3/key 9 pc4/key 13 or pc2/key 13 pc6/key 17 0 i/o 1 tou ? h key input
rev. 1.40 11 ? de?e??e? 0?? ?01? rev. 1.40 117 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver touch key operation when a fnge r t ouches or i s i n proxi mity t o a t ouch pa d, t he c apacitance of t he pa d wi ll i ncrease. by using this capa citance variation to change slightly the frequency of the internal sense oscillator , touch actions can be sensed by mea suring these frequency changes. using an internal programmable divider the reference clock is used to generate a fixed time period. by counting a number of generated clock cycles from the sense oscillator during this fxed time period touch key actions can be determined. each touch key module contains four touch key inputs which are shared logical i/o pins, and the desired function is selected using register bits. each touch key has its own independent sense oscillator. there are therefore four sense oscillators within each touch key module. during this reference clock fixed interval, the number of clock cycles generated by the s ense oscillator is measured, and it is this value that is used to determine if a touch action has been made or not. at the end of the fxed reference clock time interval a t ouch key interrupt signal will be generated. using the tscs bit in the tkc0 register can select the module 0 time slot counter as the time slot counter for all modules. all modules use the same started signal. the 16-bit c/f counter , 16-bit counter, 5-bit tim e slot counter in all module s will be automatically cleared when this bit is cleared to zero, but the 8-bit programmable time slot counter will not be cleare d. the overfow time is setup by user . when this bit changes from low to high , the 16-bit c/f counter , 16-bit counter , 5-bit time slot counter and 8-bit time slot timer counter will be automatically switched on. the key oscillator and reference oscillator in all modules will be autom atically stopped and the 16- bit c/f counter , 16-bit counter , 5-bit time slot counter and 8-bit time slot timer counter will be automatically switched of f when the 5-bit time slot counter overfows. the clock source for the time slot counter and 8+5 bit counter , is sourced from the reference oscillator or f sys /4. the reference oscillator and key oscillator will be enabled by setting the mnroen bit and mnkoen bits in the tkmnc1 register. w hen the time s lot counter in all the touch key modules or in the touch key module 0 overfow s, a n actual t ouch k ey interrupt will take place . the touch keys mentioned here are the keys which are enabled. each touch key module consists of four touch keys , key1 ~ key4 are contained in module 0, key5 ~ key8 are contained in module 1, key9 ~ key12 are contained in module 2, key13 ~ key16 are contained in the module 3 and key17 ~ key20 are contained in the module 4. each touch key module has an identical structure.
rev. 1.40 118 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 119 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver key 1 key ? key 3 key 4 key osc key osc key osc key osc mux. filte? ove?flow 1?-?it ?ounte? ove?flow f sys ?f sys /?? f sys /4? f sys /8 tk1?s1~tk1?s0 ?-?it ti?e slot ?ounte? ove?flow 8-?it ti?e slot ti?e? ?ounte? ref osc mux. f sys /4 mntss 8-?it ti?e slot ti?e? ?ounte? p?eload ?egiste? ove?flow multi- f?equen?y 1?-?it c/f ?ounte? note: 1. each touch key module contains the content in the red dash line. 2. the content in the black dash line is the module number (0~n). each module contains 4 touch keys. touch key module block diagram
rev. 1.40 118 de?e??e? 0?? ?01? rev. 1.40 119 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver the touch key sense oscilltor and reference oscillator timing diagram is shown in the following fgure: tkst mnkoen mnroen key osc clk refe?en?e osc clk f cftmck ena?le f cftmck (mndfen=0) f cftmck (mndfen=1) tkrcov set tou?h key inte??upt ?equest flag ha?dwa?e ?lea? to "0" (???-tktmr) ove?flow *3?
touch key or i/o function select
rev. 1.40 1 ? 0 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 1?1 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver touch key interrupt the touch key only has single inter rupt, w hen the time slot counter in all the touch key modules or in the touch key module 0 overfow s, a n actual t ouch k ey interrupt will take place . the touch keys mentioned here are the keys which are enabled. the 16-bit c/f counter , 16-bit counter , 5-bit time slot counter and 8 -bit time slot counter in all module s will be automatically cleared. programming considerations after t he rel evant regi sters are se tup, t he t ouch key det ection process i s i nitiated t he cha nging t he tk st bit from low to high. this will enable and synchronise all releva nt oscillators. the tkrcov fag, whi ch i s t he t ime sl ot c ounter fa g wi ll go hi gh a nd re main hi gh unt il t he c ounter ove rfows. when this happens an interrupt signal will be generated. when the external touch key size and layout are defined, their related capacitances will then determine the sensor oscillator frequency.
rev. 1.40 1?0 de?e??e? 0?? ?01? rev. 1.40 1 ? 1 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver serial interface module C sim the device s contain a serial interface module, which includes both the four -line spi interface and the two-line i 2 c interface types, to allow an easy method of communica tion with exte rnal peripheral hardware. ha ving re latively si mple c ommunication prot ocols, t hese se rial i nterface t ypes a llow the microcontroller to interface to external spi or i 2 c based hardware such as sensors, flash or eeprom memory , etc. the sim interface pins are pin-shared with other i/o pins therefore the sim interface function must first be selected by setting the sim enable/disable bit. as both interface types share the same pins and registers, the choice of whether the spi or i 2 c type is used is made using sim operating mode bits , named sim2~sim0, in the simc0 register . these pull-high resistors of the sim pin-shared i/o pins are selected using pull-high control registers when the sim function is enabled. it is suggested that the user shall not enter the device to hal t status by application program during processing sim communication. spi interface the spi interface is often used to communicate with external peripheral devices such as sensors, flash or eeprom memory devices etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the device s can be either mas ter or s lave. a lthough the s pi interface s pecifcation can control multiple s lave devices from a single master , th ese device s provide only one scs pin. if the master need s to control multiple slave devices from a single master, the master can use i/o pin to select the slave devices. spi interface operation the spi i nterface i s a f ull d uplex sy nchronous se rial d ata l ink. i t i s a f our l ine i nterface wi th p in names sdi, sdo, sck and scs . pins sdi and sdo are the serial data input and serial data output lines, sck is the serial clock line and scs is the slave select line. as the spi interface pins are pin- shared wi th n ormal i /o p ins a nd wi th t he i 2 c f unction p ins, t he spi i nterface m ust fr st b e e nabled b y setting the correct bits in the simc0 and simc2 registers. after the desired spi confguration has been set it can be disabled or enabl ed using the simen bit in the simc0 register . communication between devices connected to the spi interface is carried out in a slave/master mode with all data transfer initiat ions be ing implemented by the master . the master also control s the clock signal. as the device only contains a single scs pin only one slave device can be utilized. the scs pin is controlled by software, set csen bit high to enable the scs pin function, clear the csen bit to zero, the scs pin will be in foating state. the spi function in th ese device s offers the following features: ? full duplex synchronous data transfer ? both master and slave modes ? lsb frst or msb frst data transmission modes ? transmission complete fag ? rising or falling active clock edge the status of the spi interface pins is determined by a number of facto rs such as whether the device is in the master or slave mode and upon the condition of certain control bits such as csen and simen.
rev. 1.40 1 ?? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 1?3 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver

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? ? ? ? - ? ? ?? ? ??? ? ? ? spi block diagram spi registers there are three internal registers which control the overall operation of the spi interface. these are the simd data register and two registers simc0 and simc2. note that the simc1 register is only used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 simc0 sim ? sim1 sim0 simdbnc1 simdbnc0 simen simicf simc ? d7 d ? ckpolb ckeg mls csen wcol trf simd d7 d ? d ? d4 d3 d ? d1 d0 spi registers list the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the device writes data to the spi bus, the actual data to be transmitted must be placed in the simd register . after the data is received from the spi bus, the device can read it from the simd register . any transmission or reception of data from the spi bus must be made via the simd register. ? simd register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d ? d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w for x x x x x x x x x unknow there are also two control registers for the spi interface, simc0 and simc2. note that the simc2 register also has the name sima which is used by the i 2 c function. the simc1 register is not used by the spi functio n, only by the i 2 c function. register simc0 is used to control the enable/disable function and to set the data transmi ssion clock frequency . register simc2 is used for other control functions such as lsb/msb selection, write collision fag etc.
rev. 1.40 1?? de?e??e? 0?? ?01? rev. 1.40 1 ? 3 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver ? simc0 register bit 7 6 5 4 3 2 1 0 na ? e sim ? sim1 sim0 simdbnc1 simdbnc0 simen simicf r/w r/w r/w r/w r/w r/w r/w r/w for 1 1 1 0 0 0 0 %lw a sim2~sim0 6,0 2shudwl 0rgh rwuro 63, pdvwhu prgh 63, forfn lv i sys /4 63 pdhu ph 63 fof l sys /16 63 pdhu ph 63 fof l sys /64 63 pdhu ph 63 fof l 68 63 pdhu ph 63 fof l 37 53 fpsduh pdf uhtxhf 63 odyh ph odyh ph 8 xh ph 7hh l hxs h yhudoo shudl ph h 6 xfl hoo d hohfl l h u 63 xfl h duh xh fuo h 63 dhu6ody h hohfl d h 63 dhu fof uhtxhf 7h 63 fof l d xfl h hp fof ex fd d o eh f h eh xuf h u p f 68 u h ptm1 h 63 6o dyh h l hohfh h h fof loo eh xssolh e d hhudo dhu hylfh l 8lpsohphh uhd d l a simdbnc1~simdbnc0 , herxfh 7 lph 6hohfwlr hvfulehg l , uhlvwhuv vhfwlr lw simen 6,0 rwuro lvdeoh deoh 7kh l w l v w kh ryh udoo r rii f rwuro iru w kh 6,0 l whuidfh : kh w kh 6,0 1 l w l v fohduhg wr hur wr glvdeoh wkh 6,0 lwhuidfh wkh 6, 62 6 dg 66 ru 6 dg 6/ olhv zloo orvh wkhlu 63, ru , ixfwlr dg wkh 6,0 rshudwl fxuuhw zloo eh uhgxfhg wr d pllp xp ydoxh :kh wkh lw lv klk wkh 6,0 lwhuidfh lv hdeohg , i wkh 6,0 lv frxuhg wr rshudwh dv d 63, lwhuidfh yld wkh 6,0a6,0 lwv wkh frwhwv ri wkh 63, frwuro uhlvwhuv zloo uhpdl dw wkh suhylrxv vhwwlv zkh wkh 6,01 lw fkdhv iurp orz wr klk dg vkrxog wkhuhiruh eh uvw llwldol v hg e wkh dssolfdwlr surudp ,i wkh 6,0 lv frxuhg wr rshudwh dv d , lwhuidfh yld wkh 6,0a6,0 lwv dg wkh 6,01 lw fkdhv iurp orz wr klk wkh frwhwv ri wkh , frwuro lwv vxfk dv 7 dg 7 zloo uhpdl dw wkh suhylrxv vhwwlv dg vkrxog wkhuhiruh eh uvw llwldol v hg e w kh d ssolfdwlr surud p zkl oh w kh uh ohydw , dv vxf k d v 6 65: dg 5 zloo eh vhw wr wkhlu ghidxow vwdwhv lw simicf 63, ,frpsohwhg od 1r 63, lfrpsohwh wudvihu rffxuv 1 63 lfpsohh udhu ffxuuh tl l l o dydlodeoh h h 6 l fxuh shudh l d 63 odyh ph h 63 shudh l h odyh ph l h 61 d 61 l e ehl h l ex h 66 sl l l sxooh l e h hhudo pdhu hylfh ehuh h 63 dd udhu l fpsohho lh h 6 l loo eh h e duhduh hhu l h 75 l :h l fll ffxu h fuuhsl lhu uxs loo ffxu l h l huuxs xf l l h deoh hyh u h 7 5 l l oo eh h l l h 6 l l h l e duh dssolfdl suudp
rev. 1.40 1 ? 4 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 1?? de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver ? simc2 register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? ckpolb ckeg mls csen wcol trf r/w r/w r/w r/w r/w r/w r/w r/w r/w for 0 0 0 0 0 0 0 0 %lw a 8qghqhg %lw 7klv %lw fdq eh uhdg ru zulwwhq e xvhu vriwzduh surjudp %lw ckpolb 63, forfn olh edvh frglwlr vhohfwlr 7 kh 6 olh zloo eh klk zkh wkh forfn lv ldfwlyh 7 kh 6 olh zloo eh orz zkh wkh forfn lv ldfwlyh 7kh 32/ lw ghwhuplhv wkh edvh frglwlr ri wkh forfn olh li wkh lw lv klk wkh wkh 6 olh zloo eh orz zkh wkh forfn lv ldfwlyh :kh wkh 32/ lw lv orz wkh wkh 6 olh zloo eh klk zkh wkh forfn lv ldfwlyh lw ckeg 63, 6 forfn dfwlyh hgh wsh vhohfwlr 32/ 6 lv klk edvh ohyho dg gdwd fdswxuh dw 6 ulvl hgh 6 lv klk edvh ohyho dg gdwd fdswxuh dw 6 idool hgh 32/ 6 lv orz edvh ohyho dg gdwd fdswxuh dw 6 idool hgh 6 lv orz edvh ohyho dg gdwd fdswxuh dw 6 ulvl hgh 7kh dg 32/ lwv duh xvhg wr vhwxs wkh zd wkdw wkh forfn vldo rxwsxwv dg lsxwv gdwd r wkh 63, exv 7khvh wzr lwv pxvw eh frxuhg ehiruh gdwd wudvihu lv hhfxwhg rwkhuz lvh d huurhrxv forfn hgh pd eh hhudwhg 7kh 32/ lw ghwhuplhv w kh ed vh f rglwlr ri w kh f orfn o lh l i w kh l w l v kl k w kh w kh 6 o lh zloo eh orz zkh wkh forfn lv ldfw lyh :kh wkh 32/ lw lv orz wkh wkh 6 olh zloo eh klk zkh wkh forfn lv ldfwlyh 7kh lw ghwhuplhv dfwlyh forfn hgh wsh zklfk ghshgv xsr wkh frglwlr ri 32/ lw lw mls 63, dwd vkliw rughu /6 06 7klv lv wkh gdwd vkliw vhohfw lw dg lv xvhg wr vhohfw krz wkh gdwd lv wudvihuuhg hlwkhu 06 ru /6 uvw 6hwwl wkh lw klk zloo vhohfw 06 uvw dg orz iru /6 uvw lw csen 63, 66 sl rwuro lvdeoh 1 deoh 7h 61 l l xh d d hdeohldeoh u h 66 sl l l l o h h 66 sl loo eh ldeoh d sodfh l d dl fll h l l l h 66 sl loo eh hdeoh d xh d d hohf sl l wcol 63, : ulwh roolvlr d 1 r froolvlr roolvlr 7kh :2/ d lv xvhg wr ghwhfw li d gdwd froolvlr kdv rffxuuhg ,i wklv lw lv klk lw phdv wkdw gdwd kdv ehh dwwhpswhg wr eh zulwwh wr wkh 6,0 uhlvwhu gxul d gdwd wudvihu rshudwlr 7klv zulwl rshudwlr zloo eh lruhg li gdwd lv ehl wudvihuuhg 7kh lw fd eh fohduhg e wkh dssolfdwlr surudp lw trf 63, 7 udvplw5hfhlyh rpsohwh d 63, g dwd lv ehl wudvihuuhg 63, gdwd wudvplvvlr lv frpsohwhg 7kh 75 lw lv wkh 7 udvplw5hfhlyh rpsohwh d dg lv vhw klk dxwrpdwlfdoo zkh d 63, gdwd wudvplvvlr lv frpsoh whg exw pxvw eh fohduhg wr hur e wkh dssolfdwlr surudp ,w fd eh xvhg wr hhudwh d lwhuuxsw
rev. 1.40 1?4 de?e??e? 0?? ?01? rev. 1.40 1 ?? de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver spi communication after the spi inte rface is enabled by setting simen bit and the output pins are confgured to spi function, then in the master mode, when data is written to the simd register , transmission/reception will b egin si multaneously. w hen t he d ata t ransfer i s c omplete, t he t rf fa g wi ll b e se t a utomatically, but must be cleared using the application program. in the slave mode, when the clock signal from the master has been received, any data in the simd register will be transmitted and any data on the sdi pi n wi ll be shift ed i nto t he simd re gister. t he m aster shoul d out put a n scs signa l t o e nable the slave device before a clock signal is provided . the slave data to be transfer red should be well prepared at the appropriate moment relative to the scs signal depending upon the confgurations of the ckpolb bit and ckeg bit . the accompanying timing diagram shows the relationship between the slave data and scs signal for various confgurations of the ckpolb and ckeg bits. the spi will continue to function in specific idle modes if the clock source used by the spi interface is still active.
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?? ?? ? ?? ? ?? ?? -? ?? ?? ?? ?? ?? -? ?? ? ?? ?? ? ?? ?? ?? ? ?? ? ?? ?? -? ?? ?? ?? ?? ?? -? ?? ? ?? ?? ? ?? ?
? ? spi master mode timing

? ? ? ? ??? ? - ? ? ?? spi slave mode timing C ckeg=0
rev. 1.40 1 ?? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 1?7 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver

? ? ??? ?? ? ? ? ?? ?? ? - ? ?? ?? ? ? ?? ? ? ? ? ?? ? ?? ?? ?? ? ? ? ? ?? ? ?? ? ?? ? ?? ? ? ?? ? spi slave mode timing C ckeg=1

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? ? ? ? ? ? -? ?? ? ? ? ? ? ? ???? ??? ? ????? ?? ?? ? ???? ? spi transfer control flowchart
rev. 1.40 1?? de?e??e? 0?? ?01? rev. 1.40 1 ? 7 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver i 2 c interface the i 2 c interface is used to communicate with external peripheral devices such as sensors, eeprom memor y, etc. originally developed by philips, it is a two line low speed serial interface for synchronous serial data transfer . the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. i 2 c master/slave bus connection

? ? ? ? ??- ? ? ? ? ?? ? ? ? - ? ? ? ? ? ? ? ? ? ? ? ?? - ? ? ? ? ??
? ?? ? i 2 c block diagram i 2 c interface operation the i 2 c serial interface is a two line interf ace, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identifed by a unique address which will be transmitted and received on the i 2 c bus. when two device s communicate with each other on the bidirectional i 2 c bus, one is known as the master de vice a nd one a s t he sl ave de vice. bot h m aster a nd sl ave c an t ransmit a nd re ceive da ta , however, it is the master device that has overall control of the bus. for these devices, which only operates in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode. the pull-up control function pin-shared with scl/sda pin is still applicable even if i 2 c device is activ ated and the related internal pull-up register could be controlled by its corresponding pull-up control register.
rev. 1.40 1 ? 8 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 1?9 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver
the simdbnc1 and simdbnc0 bits determine the debounce time of the i 2 c interface. this uses the system clock to in ef fect add a debounce time to the external clock to reduce the possibility of gl itches on t he c lock l ine c ausing e rroneous ope ration. t he de bounce t ime, i f se lected, c an be chosen to be either 2 or 4 sys tem clocks. t o achieve the required i 2 c data trans fer speed, there exists a relationship between the system clock, f sys , and the i 2 c debounce time. for either the i 2 c standard or fast mode operation, users must take care of the selected system clock frequency and the confgured debounce time to match the criterion shown in the following table. i 2 c debounce time selection i 2 c standard mode (100khz) i 2 c fast mode (400khz) no de ? oun ? e f sys > ? mhz f sys > ? mhz ? syste ? ? lo ? k de ? oun ? e f sys > 4mhz f sys > 10mhz 4 syste ? ? lo ? k de ? oun ? e f sys > 8mhz f sys > ? 0mhz i 2 c minimum f sys frequency i 2 c registers there are four control registers associated with the i 2 c bus, simc0, simc1 , simt oc and sima and one data register , simd. the simd register , which is shown in the above spi section, is used to store the data being transmitted and received on the i 2 c bus. before the microcontroller writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simd register . after the data is received from the i 2 c bus, the micro controller can read it from the simd register . any transmission or reception of data from the i 2 c bus must be made via the simd register . note that the sima register also has the name simc2 which is used by the spi function. the simen bit, sim2~sim0 bits and simdbnc1~simdbnc0 bits in register simc0 are used by the i 2 c interface. the simtoc register is used for the i 2 c time-out control. register name bit 7 6 5 4 3 2 1 0 simc0 sim ? sim1 sim0 simdbnc1 simdbnc0 simen simicf simc1 hcf haas hbb htx txak srw iamwu rxak simd d7 d ? d ? d4 d3 d ? d1 d0 sima a ? a ? a4 a3 a ? a1 a0 simtoc simtoen simtof simtos ? simtos4 simtos3 simtos ? simtos1 simtos0
rev. 1.40 1?8 de?e??e? 0?? ?01? rev. 1.40 1 ? 9 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver the simd register is used to store the data being transmitted and received. the same register is used by bot h t he spi a nd i 2 c fun ctions. be fore t he de vice wri tes da ta t o t he i 2 c bus, t he a ctual da ta t o be transmitted must be placed in the simd register . after the data is received from the i 2 c bus, the device can read it from the simd register . any transmission or reception of data from the i 2 c bus must be made via the simd register. ? simd register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d ? d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w for x x x x x x x x x unknow n the sima register is also used by the spi interface but has the name simc2. the sima register is the location where the 7-bit slave address of the slave device is stored. bits 7~1 of the sima register defne the device slave address. bit 0 is not defned. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the sima register , the slave device will be selected. note that the sima register is the same register address as simc2 which is used by the spi interface. ? sima register bit 7 6 5 4 3 2 1 0 na ? e a ? a ? a4 a3 a ? a1 a0 r/w r/w r/w r/w r/w r/w r/w r/w for 0 0 0 0 0 0 0 b it 7~1 a6~a0 : i 2 c slave address a6~a0 is i 2 c slave address bit 7~ bit 1. bit 0 unimplemented, read as 0 there are also two control registers for the i 2 c interface, simc0 and simc 1 . the simc0 register is used to control the enable/disable function and to set the data transmission clock frequency . the simc1 register contains the relevant fags which are used to indicate the i 2 c communication status .
rev. 1.40 130 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 131 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver ? simc0 register bit 7 6 5 4 3 2 1 0 na ? e sim ? sim1 sim0 simdbnc1 simdbnc0 simen simicf r/w r/w r/w r/w r/w r/w r/w r/w for 1 1 1 0 0 0 0 %lw a sim2~sim0 6,0 2shudwl 0rgh rwuro 63, pdvwhu prgh 63, forfn lv i sys /4 63 pdhu ph 63 fof l sys /16 63 pdhu ph 63 fof l sys /64 63 pdhu ph 63 fof l 68 63 pdhu ph 63 fof l 37 53 fpsduh pdf uhtxhf 63 odyh ph odyh ph 8 xh ph 7hh l hxs h yhudoo shudl ph h 6 xfl hoo d hohfl l h u 63 xfl h duh xh fuo h 63 dhu6ody h hohfl d h 63 dhu fof uhtxhf 7h 63 fof l d xfl h hp fof ex fd d o eh f h eh xuf h u p f 68 u h p tm 1 h 63 6o dyh h l hohfh h h fof loo eh xssolh e d hhudo dhu hylfh l 8lpsohphh uhd d l a simdbnc1~simdbnc0 , herxfh 7 lph 6hohfwlr 1 r gherxfh vvwhp forfn gherxfh vvwhp forfn gherxfh vvwhp forfn gherxfh lw simen 6,0 rwuro lvdeoh deoh 7kh l w l v w kh ryh udoo r rii f rwuro iru w kh 6,0 l whuidfh : kh w kh 6,0 1 l w l v fohduhg wr hur wr glvdeoh wkh 6,0 lwhuidfh wkh 6, 62 6 dg 66 ru 6 dg 6/ olhv zloo orvh wkhlu 63, ru , ixfwlr dg wkh 6,0 rshudwl fxuuhw zloo eh uhgxfhg wr d pllp xp ydoxh :kh wkh lw lv klk wkh 6,0 lwhuidfh lv hdeohg , i wkh 6,0 lv frxuhg wr rshudwh dv d 63, lwhuidfh yld wkh 6,0a6,0 lwv wkh frwhwv ri wkh 63, frwuro uhlvwhuv zloo uhpdl dw wkh suhylrxv vhwwlv zkh wkh 6,01 lw fkdhv iurp orz wr klk dg vkrxog wkhuhiruh eh uvw llwldol v hg e wkh dssolfdwlr surudp ,i wkh 6,0 lv frxuhg wr rshudwh dv d , lwhuidfh yld wkh 6,0a6,0 lwv dg wkh 6,01 lw fkdhv iurp orz wr klk wkh frwhwv ri wkh , frwuro lwv vxfk dv 7 dg 7 zloo uhpdl dw wkh suhylrxv vhwwlv dg vkrxog wkhuhiruh eh uvw llwldol v hg e w kh d ssolfdwlr surud p zkl oh w kh uh ohydw , dv vxf k d v 6 65: dg 5 zloo eh vhw wr wkhlu ghidxow vwdwhv lw simicf 63, ,frpsohwhg od hvfulehg l wkh 63, uhlvwhu vhfwlr
rev. 1.40 130 de?e??e? 0?? ?01? rev. 1.40 131 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver ? simc1 register bit 7 6 5 4 3 2 1 0 na ? e hcf haas hbb htx txak srw iamwu rxak r/w r r r r/w r/w r r/w r for 1 0 0 0 0 0 0 1 %lw hcf , xv gdwd wudvihu frpsohwlr d d dd l ehl udhuuh psohl d l dd udhu 7h od l h dd udhu od 7l od loo eh hu h dd l ehl udhuuh 8s fpsohl d l dd udhu h od loo l d d lhuuxs loo eh hhudh l haas , xv dgguhvv pdwfk d 1 rw dgguhvv pdwfk gguhvv pdwfk 7kh 6 d l v w kh d gguhvv p dwfk d 7 klv d l v xvh g w r gh whuplh l i w kh vo dyh ghylfh dgguhvv lv wkh vdph dv wkh pdvwhu wudvplw dgguhvv ,i wkh dgguhvvhv pdwfk wkh wklv lw zloo eh klk li wkhuh lv r pdwfk wkh wkh d zloo eh orz lw hbb , xv exv d , xv lv rw exv , xv lv exv 7kh iod lv wkh , exv iod 7klv iod zloo eh zkh wkh , exv lv exv zklfk zloo rffxu zkh d 67 57 vldo lv ghwhfwhg 7kh d zloo eh vhw wr zkh wkh exv lv iuhh zklfk zloo rffxu zkh d 6723 vldo lv ghwhfwhg lw htx , vodyh ghylfh wudvplwwhu uhfhlyhu vhohfwlr s odyh hylfh l h uhfhlyhu s odyh hylfh l h udplhu l txak , xv wudvplw dfnrzohgh d s odyh h dfohh d s odyh h dfohh d 7h 7 l l h udpl dfohh od hu h odyh hylfh uhfhls l dd l l loo eh udplh h ex h fof up h odyh hylfh 7h odyh hylfh px dod fohdu h 7 l hu ehuh xuhu dd l uhfhlyh l srw , 6odyh 5hdg:ulwh d s odyh hylfh xo eh l uhfhlyh ph s odyh hylfh xo eh l udpl ph 7h 65 : od l h 6o dyh 5 hd:ulh od 7 l od hhuplh hhu h pdhu hylfh lh udpl u uhfhlyh dd up h ex :h h udplh duh d odyh duh l pdf d l h h 6 d l h l h odyh hylfh loo fhf h 65 : d hhuplh hhu l xo eh l udpl ph u uhfhlyh ph h 65 : d l l h pdhu l uhtxhl uhd dd up h ex h odyh hylfh xo eh l udpl ph :h h 65 : od l hu h pdhu loo ulh dd h ex huhuh h odyh hylfh xo eh l uhfhlyh ph uhd l dd l iamwu , gguhvv 0dwfk : dnhxs rwuro dldeoh edeoh C px eh fohduh e h dssolfdl suudp dhu dhxs 7l l xo eh h hdeoh h duh pdf dh xs up h 6/3 u / h h m :8 l d ehh h ehuh hhul hlhu h 6/3 u / ph hdeoh h duh pdf dh xs h l l px eh fohduh e dssolfdl suudp dhu dhxs hxuh fuuhfl hylfh shudl
rev. 1.40 13 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 133 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bit 0 rxak : i 2 c bus receive acknowledge fag 0: s lave receive s acknowledge fag 1: s lave do not receive acknowledge fag the r xak fl ag i s t he r eceiver a cknowledge f lag. w hen t he r xak f lag i s 0, i t means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. when the slave device in the transmit mode, the slave device checks the rxak fag to determine if the master receiver wishes to receive the next byte. t he sl ave t ransmitter wi ll t herefore c ontinue se nding out da ta unt il t he rxak fag is 1. when this occurs, the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. i 2 c bus communication communication on the i 2 c bus requires four separate steps, a st art signal, a slave device address transmission, a data transmission and finally a st op signal. when a st art signal is placed on the i 2 c bus, all devices on the bus will receive this signal and be notifed of the imminent arrival of data on the bus. the frst seven bits of the data will be the slave address with the frst bit being the msb. if the address of the slave device matches that of the transmitted address, the haas bit in the simc1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the slave device must frst check the condition of the haas bit and simt of bit to de termine whe ther t he i nterrupt sourc e ori ginates from a n a ddress m atch or i 2 c communication time-out or from the completion of an 8-bit data transfer . during a data transfer , note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the sr w bit. this bit will be checked by the slave device to determine whether to go into transmit or receive mode. before any transfer of data to or from the i 2 c bus, the microcontroller must initialize the bus, the following are steps to achieve this: ? step 1 set the sim2~sim0 bits and simen bit in the simc0 register to 110 and 1 repectively to enable the i 2 c bus. ? step 2 write the slave address of the device to the i 2 c bus address register sima. ? step 3 set the related interrupt enable bit of the interrupt control register to enable the sim interrupt.

? ? ? ? ? ? ?- ?? ? ? ? ?? ? ? ? ? ?- i 2 c bus initialisation flow chart
rev. 1.40 13? de?e??e? 0?? ?01? rev. 1.40 133 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver i 2 c bus start signal the st art signal can only be generated by the master device connec ted to the i 2 c bus and not by the slave device. this st art signal will be detected by all devices connected to the i 2 c bus. when detected, t his i ndicates t hat t he i 2 c bus i s busy a nd t herefore t he hbb bi t wi ll be se t. a st art condition occurs when a high to low transition on the sda line takes place when the scl line remains high. slave address the t ransmission o f a st art si gnal b y t he m aster wi ll b e d etected b y a ll d evices o n t he i 2 c b us. to determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the st art signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the maste r matche s the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal will be generated. the next bit following the address, which is the 8th bit, defnes the read/write status and will be saved to the sr w bit of the simc1 register . the slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the slave device will also set the status fag haas when the addresses match. as a n i 2 c bus i nterrupt c an c ome fro m t hree sourc es, whe n t he progra m e nters t he i nterrupt subroutine, the haas bit and simt of bit should be examined to see whether the interrupt source has come from a matching slave address or i 2 c communication time-ou t or from the completion of a data byte transfer . when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simd register , or in the receive mode where it must implement a dummy read from the simd register to release the scl line. i 2 c bus read/write signal the sr w bit in the simc1 register defnes whether the slave device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the slave device should exam ine this bit to determine if it is to be a transmitter or a receiver . if the sr w fag is 1 then this indicates that the master device wishes to read data from the i 2 c bus, therefore the slave device must be setup to send data to the i 2 c bus as a transmitter . if the sr w fag is 0 then this indicates that the master wishes to send data to the i 2 c bus, therefore the slave device must be setup to read data from the i 2 c bus as a receiver. i 2 c bus slave address acknowledge signal after the mas ter has trans mitted a calling addres s, any s lave device on the i 2 c bus , w hose own internal address matches the calling address, must generate an acknowledge signal. the acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a st op signal must be transmitted by the master to end the communication. when the haas fag is high, the addresses have matched and the slave device must check the sr w fag to determine if it is to be a transmitter or a receiver . if the sr w fag is high, the slave device should be setup to be a transmitter so the htx bit in the simc1 register should be set to 1. if the sr w fag is low , then the microcontroller slave device should be setup as a receiver and the htx bit in the simc1 register should be cleared to 0.
rev. 1.40 134 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 13? de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver i 2 c bus data and acknowledge signal the t ransmitted da ta i s 8-bi t wi de a nd i s t ransmitted a fter t he sl ave de vice ha s a cknowledged receipt of its slave address. the order of serial bit transmission is the msb frst and the lsb last. after receipt of 8-bit of data, the receiver must transmit an acknowledge signal, level 0, before it can receive the next data byte. if the slave transmitter does not receive an acknowledge bit signal from the master receiver , then the slave transmitter will release the sda line to allow the master to send a st op signal to release the i 2 c bus. the corresponding data will be stored in the simd register. if setup as a transmitter , the slave device must frst write the data to be transmitted into the simd register . if setup as a receive r, the slave device must read the transmitted data from the simd register. when the s lave receiver receives the data byte, it mus t generate an acknow ledge bit, know n as txak, on the 9th clock. the slave device, which is setup as a transmit ter will check the rxak bit in the simc1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master.
? ? ? ? ? ? ? ? - ?
- ? ? note: *when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simd register , or in the receive mode where it must implement a dummy read from the simd register to release the scl line. i 2 c communication timing diagram
rev. 1.40 134 de?e??e? 0?? ?01? rev. 1.40 13 ? de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver
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?? ? ?? i 2 c bus isr flow chart i 2 c interface time-out function in order to reduce the problem of i 2 c lockup due to reception of erroneous clock sources, clock, a time-out function is provided. if the clock source to the i 2 c is not received then after a fxed time period, the i 2 c circuitry and registers will be reset.
? ? ? ? ?? ? ? - ?
- ? i 2 c time-out the time-out counter starts counting on an i 2 c bus st art and address match condition, and is c leared b y a n sc l f alling e dge. b efore t he n ext sc l f alling e dge a rrives, i f t he t ime e lapsed i s greater t han t he t ime-out se tup b y t he si mtoc r egister, t hen a t ime-out c ondition wi ll o ccur. t he time-out function will stop when an i 2 c stop condition occurs.
rev. 1.40 13 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 137 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver when an i 2 c time-out counter overfow occurs, the counter will stop and the simt oen bit will be cleared to zero and the simt of bit will be set high to indicate that a time-out condition as occurred. the time-out condition will also generate an interrupt which uses the i 2 c interrupt vector . when an i 2 c time-out occurs, the i 2 c internal circuitry will be reset and the registers will be reset into the following condition. register after i 2 c time-out simd ? sima ? simc0 no ? hange simc1 reset to por ? ondition the simt of fag can be cleared by the application program. there are 64 time-out periods which can be selected using bits in the simtoc register. the time-out time is given by the formula: ((1~64) 32)/f sub this gives a range of about 1ms to 64ms. ? simtoc register bit 7 6 5 4 3 2 1 0 na ? e simtoen simtof simtos ? simtos4 simtos3 simtos ? simtos1 simtos0 r/w r/w r/w r/w r/w r/w r/w r/w r/w for 0 0 0 0 0 0 0 0 bit 7 simtoen : sim i 2 c t ime-out control 0: disable 1: enable bit 6 simtof : sim i 2 c t ime-out fag 0: no time-out occurred 1: time-out o ccurred this bit is set by time-out and clear ed by application program. bit 5~0 simtos5~simtos0 : sim i 2 c t ime-out period selection the i 2 c t ime-out clock source is f sub /32. the i 2 c t ime-out period is equal to (simtos [ 5: 0]+1) (32/f sub )
rev. 1.40 13? de?e??e? 0?? ?01? rev. 1.40 137 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver uart interface the device s conta in an integrated full-duplex asynchronous serial communications uar t interface that enables communication with external devices that contain a serial interface. the uart function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. the uar t function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. the integrated uart function contains the following features: ? full-duplex, universal asynchronous receiver and t ransmitter (uart) communication ? 8 or 9 bits character length ? even, odd or no parity options ? one or two stop bits ? baud rate generator with 8-bit prescaler ? parity, framing, noise and overrun error detection ? support for interrupt on address detect (last character bit=1) ? transmitter and receiver enabled independently ? 2-byte deep fifo receive data buffer ? transmit and receive multiple interrupt generation sources: transmitter empty transmitter idle receiver full receiver overrun address mode detect rx pin wake-up interrupt (rx enable, rx falling edge) uart external pin interfacing to communicate with an external serial interface, the internal uar t has two external pins known as tx and rx. the tx and rx pins are the uar t transmitter and receiver pins respectively . along with the uar ten bit, the txen and rxen bits, if set, will automati cally setup these i/o or other pin-shared functional pins to their respective tx output and rx input conditions and disable any pull-high resistor option which may exist on the tx or rx pin s. when the tx or rx pin function is disable d by clea ring the uar ten and txen or rxen bit, the tx or rx pin can be used as a general purpose i/o or other pin-shared functional pin .
rev. 1.40 138 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 139 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver uart data transfer scheme the block diagram s hows the overall data trans fer s tructure arrangement for the u art interface . the a ctual da ta t o be t ransmitted from t he mcu i s fi rst t ransferred t o t he t xr re gister by t he application program. the data will then be transferred to the t ransmit shift register from where it will be shifted out, lsb frst, onto the tx pin at a rate controlled by the baud rate generator . only the txr register is mapped onto the mcu data memory , the transmit shift register is not mapped and is therefore inaccessible to the application program. data to be received by the uar t is accepted on the external rx pin, from where it is shifted in, lsb fi rst, t o t he re ceiver shi ft r egister a t a ra te c ontrolled by t he b aud ra te ge nerator. w hen the shift register is full, the data will then be transferred from the shift register to the internal rxr register, where it is buf fered and can be manipulated by the application program. only the rxr register i s m apped ont o t he mcu da ta me mory, t he re ceiver shift re gister i s not m apped a nd i s therefore inaccessible to the application program. it should be noted that the actual register for data transmission and reception , although referred to in the text, and in application programs, as separate txr and rxr registers, only exists as a single shared register in the data memory . this shared register known as the txr _ rxr register is used for both data transmission and data reception. msb lsb ?????????? t?ans?itte? shift registe? msb lsb ?????????? re?eive? shift registe? tx pin rx pin baud rate gene?ato? tx r registe? rx r registe? buffe? mcu data bus clk clk uart data transfer scheme uart status and control registers there are fve control registers associated with the uar t function. the usr, ucr1 and ucr2 registers c ontrol t he o verall f unction o f t he uar t, wh ile t he b rg r egister c ontrols t he b aud r ate. the actua l data to be transmitted and received on the serial interface is managed through the txr _ rxr data register. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 usr perr nf ferr oerr ridle rxif tidle txif ucr1 uarten bno pren prt stops txbrk rx8 tx8 ucr ? txen rxen brgh adden wake rie tiie teie txr_ rxr txrx7 txrx ? txrx ? txrx4 txrx3 txrx ? txrx1 txrx0 brg brg7 brg ? brg ? brg4 brg3 brg ? brg1 brg0 uart register list
rev. 1.40 138 de?e??e? 0?? ?01? rev. 1.40 139 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver usr register the usr register is the status register for the uart, which can be read by the program to determine the present status of the uar t. all fags within the usr register are read only . further explanation on each of the fags is given below . bit 7 6 5 4 3 2 1 0 na ? e perr nf ferr oerr ridle rxif tidle txif r/w r r r r r r r r por 0 0 0 0 1 0 1 1 bit 7 perr : parity error fag 0: no parity error is detected 1: parity error is detected the perr fag is the parity error fag. when this read only fag is 0, it indicates a parity error has not been detected. when the fag is 1, it indicates that the parity of the received word is incorrect. this error fag is applicable only if parity mode (odd or even) is selected. the fag can also be cleared by a software sequence which involves a read to the status register usr followed by an access to the rxr data register. bit 6 nf : noise fag 0: no noise is detected 1: noise is detected the n f fag is the noise fag. when this read only fag is 0, it indicates no noise condition. when the fag is 1, it indicates that the uar t has detected noise on the receiver input. the nf fag is set during the same cycle as the rxif fag but will not be set in the case of as overrun. the n f fag can be cleared by a softw are sequence which will involve a read to the status register usr followed by an access to the rxr data register. bit 5 ferr : framing error fag 0: no framing error is detected 1: framing error is detected the ferr fag is the framing error fag. when this read only fag is 0, it indicates that t here i s n o f raming e rror. w hen t he fa g i s 1, i t i ndicates t hat a f raming e rror has been detected for the current character . the fag can also be cleared by a software sequence which will involve a read to the status register usr followed by an access to the rxr data register. bit 4 oerr : overrun error fag 0: no overrun error is detected 1: overrun error is detected the oerr flag is the overrun error flag which indicates when the receiver buf fer has overfowed. when this read only fag is 0, it indicates that there is no overrun error. when the fag is 1, it indica tes that an overrun error occurs which will inhibit further t ransfers t o t he rxr rec eive da ta re gister. t he fa g i s c leared by a soft ware sequence, which is a read to the status register usr followed by an access to the rxr data register. bit 3 ridle : receiver status 0: data reception is in progress (data being received) 1: no data reception is in progress (receiver is idle) the ridle fag is the receiver status fag. when this read only fag is 0, it indicates that the receiver is between the init ial detection of the start bit and the completion of the st op b it. w hen t he fa g i s 1, i t i ndicates t hat t he r eceiver i s i dle. b etween t he completion of the stop bit and the detection of the next start bit, the ridle bit is 1 indicating that the uart receiver is idle and the rx pin stays in logic high condition.
rev. 1.40 140 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 141 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bit 2 rxif : receive rxr data register status 0: rxr data register is empty 1: rxr data register has available data the rxif fag is the receive data register status fag. when this read only fag is 0, it indicates that the rxr read data register is empty . when the fag is 1, it indicates that t he r xr r ead d ata r egister c ontains n ew d ata. w hen t he c ontents o f t he sh ift register are trans ferred to the rx r register , an interrupt is generated if rie=1 in the ucr2 register . if one or more errors are detected in the received word, the appropriate receive-related fags nf , ferr, and/or perr are set within the same clock cycle. the rxif fag is clear ed when the usr register is read with rxif set, followed by a read from the rxr register, and if the rxr register has no data available. bit 1 tidle : t ransmission idle 0: data transmission is in progress (data being transmitted) 1: no data transmission is in progress (transmitter is idle) the tidle flag is known as the transmission complete flag. when this read only fag i s 0, i t i ndicates t hat a t ransmission i s i n p rogress. t his fa g wi ll b e se t t o 1 when the txif fag is 1 and when there is no transmit data or break character being transmitted. when tidle is equal to 1, the tx pin becomes idle with the pin state in logic high condition. the tidle fag is cleared by reading the usr register with tidle set and then writing to the txr register . the fag is not generated when a data character or a break is queued and ready to be sent. bit 0 txif : t ransmit txr data register status 0: character is not transferred to the transmit shift register 1: character has transferred to the transmit shift register (txr data register is empty) the txif fag is the transmit data register empty fag. when this read only fag is 0, it indicat es that the character is not transferred to the transmitter shift register . when the fag is 1, it indicates that the transmitter shift register has received a character from the txr data register . the txif flag is cleared by reading the uar t status register (usr) with txif set and then writing to the txr data register . note that when t he t xen b it i s se t, t he t xif fa g b it wi ll a lso b e se t si nce t he t ransmit d ata register is not yet full. ucr1 register the ucr1 register together with the ucr2 register are the two uart control registers that are used to set the various options for the uar t function, such as overall on/of f control, parity control, data transfer bit length etc. further explanation on each of the bits is given below . bit 7 6 5 4 3 2 1 0 na ? e uarten bno pren prt stops txbrk rx8 tx8 r/w r/w r/w r/w r/w r/w r/w r w por 0 0 0 0 0 0 x 0 x unknown bit 7 uarten : uart function enable control 0: disable uart. tx and rx pins are as i/o or other pin-shared functional pins 1: enable uart. tx and rx pins function as uart pins the uar ten bit is the uar t enable bit. when this bit is equal to 0, the uar t will be di sabled a nd t he rx pi n a s we ll a s t he t x pi n wi ll be a s ge neral purpose i/ o or other pin-shared functional pins. when the bit is equal to 1, the uar t will be enabled and the tx and rx pins will function as defned by the txen and rxen enable control bits.
rev. 1.40 140 de?e??e? 0?? ?01? rev. 1.40 141 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver when the uar t is disabled, it will empty the buf fer so any character remaining in the buf fer will be discarded. in addition, the value of the baud rate counter will be reset. if the uar t is disabled, all error and status fags will be reset. also the txen, rxen, txbrk, rxif , oerr, ferr, perr and nf bits will be cle ared, while the tidle, t xif a nd ridl e bi ts wi ll be se t. ot her c ontrol bi ts i n uc r1, uc r2 a nd brg registers will remain unaf fected. if the uar t is active and the uar ten bit is cleared, all pending transmis sions and receptions will be terminated and the module will be reset as defined above. when the uar t is re-enabled, it will restart in the same confguration. bit 6 bno : number of data transfer bits selection 0: 8-bit data transfer 1: 9-bit data transfer this bit is used to select the data length format, which can have a choice of either 8-bit or 9-bit format. when this bit is equal to 1, a 9-bit data length format will be selected. if the bit is equal to 0, then an 8-bit data length format will be selected. if 9-bit data length format is selected, then bits rx8 and tx8 will be used to store the 9th bit of the received and transmitted data respectively. note: 1. if bno=1 (9-bit data transfer), parity function is enabled, the 9th bit of data is the parity bit which will not be transferred to rx8. 2. if bno=0 (8-bit data transfer), parity function is enabled, the 8th bit of data is the parity bit which will not be transferred to rx7. bit 5 pren : parity function enable control 0: parity function is disabled 1: parity function is enabled this is the parity enable bit. when this bit is equal to 1, the parity function will be enabled. if the bit is equal to 0, then the parity function will be disabled. bit 4 prt : parity type selection bit 0: even parity for parity generator 1: odd parity for parity generator this bit is the parity type selection bit. when this bit is equal to 1, odd parity type will be selected. if the bit is equal to 0, then even parity type will be selected. bit 3 stops : number of s top bits selection 0: one stop bit format is used 1: t wo stop bits format is used this bit determines if one or two stop bits are to be used for the tx pin . when this bit is equal to 1, two stop bits are used. if this bit is equal to 0, then only one stop bit is used. bit 2 txbrk : t ransmit break character 0: no break character is transmitted 1: break characters transmit the txbrk bit is the t ransmit break character bit. when this bit is 0, there are no break characters and the tx pin operates normally . when the bit is 1, there are transmit break characters and the transmitter will send logic zeros. when this bit is equal to 1, after the buf fered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the txbrk bit is reset. bit 1 rx8 : receive data bit 8 for 9-bit data transfer format (read only) this bi t i s onl y use d i f 9-b it da ta t ransfers a re use d, i n whi ch c ase t his bi t l ocation will st ore t he 9 th b it o f t he r eceived d ata k nown a s r x8. t he b no b it i s u sed t o determine whether data transfers are in 8-bit or 9-bit format. bit 0 tx8 : t ransmit data bit 8 for 9-bit data transfer format (write only) this bi t i s onl y use d i f 9-b it da ta t ransfers a re use d, i n whi ch c ase t his bi t l ocation will store the 9th bit of the transmitted data known as tx8. the bno bit is used to determine whether data transfers are in 8-bit or 9-bit format.
rev. 1.40 14 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 143 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver ucr2 register the ucr2 register is the second of the two uart control registers and serves several purposes. one of its main functio ns is to control the basic enable/disable operation of the uar t t ransmitter and receiver as well as enabling the various uar t interrupt sources. the register also serves to control the baud rate speed, receiver wake-up enable and the address detect enable. further explanation on each of the bits is given below . bit 7 6 5 4 3 2 1 0 na ? e txen rxen brgh adden wake rie tiie teie r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 txen : uart t ransmitter enabled control 0: uart transmitter is disabled 1: uart transmitter is enabled the bit named txen is the t ransmitter enable bit. when this bit is equal to 0, the transmitter will be disabled with any pending data transmissions being aborted. in addition the buf fers will be reset. in this situation the tx pin will be used as an i/o or other pin-shared functional pin. if the tx en bit is equal to 1 and the u arten bit is als o equal to 1, the transmitter will be enabled and the tx pin will be controlled by the uar t. clearing the txen bit during a transmission will cause the data transmission to be aborted and will reset the transmitter . if this situation occurs, the tx pin will be used as an i/o or other pin-shared functional pin. bit 6 rxen : uart receiver enabled control 0: uart receiver is disabled 1: uart receiver is enabled the bi t na med rxe n i s t he re ceiver e nable bi t. w hen t his bi t i s e qual t o 0, t he receiver will be disabled with any pending data receptions being aborted. in addition the receive buf fers will be reset. in this situation the rx pin will be used as an i/o or other pin-shared functional pin. if the rxen bit is equal to 1 and the uar ten bit is also equal to 1, the receiver will be enabled and the rx pin will be controlled by the uar t. clearing the rxen bit during a reception will cause the data reception to be aborted and will reset the receiv er. if this situation occurs, the rx pin will be used as an i/o or other pin-shared functional pin. bit 5 brgh : baud rate speed selection 0: low speed baud rate 1: high speed baud rate the bit named brgh selects the high or low speed mode of the baud rate generator . this bit, together with the value placed in the baud rate register brg, controls the baud rate of the uar t. if this bit is equal to 1, the high speed mode is selected. if the bit is equal to 0, the low speed mode is selected. bit 4 adden : address detect function enable control 0: address detect ion function is disabled 1: address detect ion function is enabled the bit named adden is the address detect function enable control bit. when this bit is equal to 1, the address detect function is enabled. when it occurs, if the 8th bit, whi ch c orresponds t o rx7 i f bno= 0 or t he 9t h bi t, whi ch c orresponds t o rx8 if bno=1, has a value of 1, then the received word will be identifed as an address, rather than data. if the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8th or 9th bit depending on the value of bno. if the address bit known as the 8th or 9th bit of the received word is 0 with the address detect function being enabled, an interrupt will not be generated and the received data will be discarded.
rev. 1.40 14? de?e??e? 0?? ?01? rev. 1.40 143 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bit 3 wake : rx pin falling edge wake-up uart function enable control 0: rx pin wake-up uart function is disabled 1: rx pin wake-up uart function is enabled this bit is used to control the wake-up uar t function when a falling edge on the rx pin occurs. note that this bit is only available when the uart clock source is switched off. there will be no rx pin wake-up uar t function if the uar t clock exists. if the wake bit is set to 1 as the uar tn clock is switched of f, a uar tn wake-up request will be initiated when a falling edge on the rx pin occurs. when this request happens and the corresponding interrupt is enabled, an rx pin wake-up uar t interrupt will be generated to inform the mcu to wake up the uar t function by switching on the uart clock via the application program. otherwise, the uar t function can not resume even if there is a falling edge on t he rx pin when the w ake bit is c leared to 0. bit 2 rie : receiver interrupt enable control 0: receiver related interrupt is disabled 1: receiver related interrupt is enabled this bit enables or disables the rece iver interrupt. if this bit is equal to 1 and when the receiver overrun fag oerr or receive data available fag rxif is set, the uar t interrupt request fag will be set. if this bit is equal to 0, the uar t interrupt request fag will not be infuenced by the condition of the oerr or rxif fags. bit 1 tiie : t ransmitter idle interrupt enable control 0: t ransmitter idle interrupt is disabled 1: t ransmitter idle interrupt is enabled this bit enables or disables the transmitter idle interrupt. if this bit is equal to 1 and when the transmitter idle fag tidle is set, due to a transmitter idle condition, the uart interrupt request fag will be set. if this bit is equal to 0, the uar t interrupt request fag will not be infuenced by the condition of the tidle fag. bit 0 teie : t ransmitter empty interrupt enable control 0: t ransmitter empty interrupt is disabled 1: t ransmitter empty interrupt is enabled this bit enables or disables the transmitter empty interrupt. if this bit is equal to 1 and when the transmitter empty fag txif is set, due to a transmitter empty condition, the uar t i nterrupt re quest fl ag wi ll be set . if t his bi t i s e qual t o 0, t he uar t interrupt request fag will not be infuenced by the condition of the txif fag. txr_rxr register the txr_rxrn register is the data register which is used to store the data to be transmitted on the txn pin or being received from the rx n pin. bit 7 6 5 4 3 2 1 0 na ? e txrx7 txrx ? txrx ? txrx4 txrx3 txrx ? txrx1 txrx0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x unknown bit 7~0 txrx7~txrx0 : uart t ransmit/receive data bit 7 ~ bit 0
rev. 1.40 144 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 14? de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver baud rate generator to setup the speed of the serial data communication, the uar t function contains its own dedicated baud rate generator . the baud rate is controlled by its own internal free running 8-bit timer , the period of which is determined by two factors. the frst of these is the value placed in the baud rate register brg and the se cond is the val ue of t he brgh bit wi th t he cont rol regi ster ucr2. the brgh bit decides if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. the value in the brg register , n, which is used in the following baud rate calculation formula determines the division factor . note that n is the decimal value placed in the brg register and has a range of between 0 and 255. ucr2 brgh bit 0 1 baud rate (br) f sys / [ ? 4 (n+1)] f sys / [1 ? (n+1)] by programming the brgh bit which allows selection of the related formula and programming the required value in the brg register , the required baud rate can be setup. note that because the actual baud rate is determ ined using a discrete value, n, placed in the brg register , there will be an error associated between the actual and requested value. the following example shows how the brg register value n and the error value can be calculated. brg register bit 7 6 5 4 3 2 1 0 na ? e brg7 brg ? brg ? brg4 brg3 brg ? brg1 brg0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x unknown bit 7~0 brg7~brg0 : baud rate values by progra mming t he brgh bi t i n ucr2 re gister whi ch a llows se lection of t he related formula described above and programming the required value in the brg register, the required baud rate can be setup. calculating the baud rate and error values for a clock frequency of 4 mhz, and with brgh set to 0 determine the brg register value n, the actual baud rate and the error value for a desired baud rate of 4800 . from the above table the desired baud rate br = f sys / [64 (n+1)] re-arranging this equation gives n = [f sys / (br64)] - 1 giving a value for n = [ 4 000000 / (480064) ] - 1 = 12.0208 to obtain the closest value, a decim al value of 12 should be placed into the brg register . this gives an actual or calculated baud rate value of br = 4 000000 / [64 (12 + 1)] = 4808 therefore the error is equal to ( 4808 - 48 00) / 48 00 = 0.16%
rev. 1.40 144 de?e??e? 0?? ?01? rev. 1.40 14 ? de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver the following table shows actual values of baud rate and error values for the two values of brgh. baud rate k/bps f sys =8mhz baud rates for brgh=0 baud rates for brgh=1 brg kbaud error (%) brg kbaud error (%) 0.3 1. ? 103 1. ? 0 ? 0.1 ? ? .4 ? 1 ? .404 0.1 ? ? 07 ? .404 0.1 ? 4.8 ?? 4.808 0.1 ? 103 4.808 0.1 ? 9. ? 1 ? 9. ? 1 ? 0.1 ? ? 1 9. ? 1 ? 0.1 ? 19. ? ? 17.88 ? 7 - ? .99 ?? 19. ? 31 0.1 ? 38.4 ? 41. ?? 7 8. ? 1 1 ? 38.4 ?? 0.1 ? ? 7. ? 1 ?? . ? 00 8. ? 1 8 ?? . ??? -3. ?? 11 ? . ? 0 1 ?? 8. ? 1 3 1 ?? 8. ? 1 ?? 0 1 ?? 0 0 baud rates and error values uart setup and control for data transfer , the uar t functio n utilizes a non-return-to-zero, more commonly known as nrz, format. this is composed of one start bit, eight or nine data bits, and one or two stop bits. parity is supported by the uar t hardware, and can be setup to be even, odd or no parity . for the most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, n, 1, is used as the default setti ng, which is the setting at power -on. the number of data bits and stop bits, along with t he pa rity, a re set up by program ming t he c orresponding bno, pr t, pre n, a nd st ops bi ts in the ucr1 register . the baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator , while the data is transmitted and received lsb frst. although the uar t transmitter and receiver are functionally independent, they both use the same data format and baud rate. in all cases stop bits will be used for data transmission. enabling/disabling the uart interface the basic on/of f function of the internal uar t function is controlled using the uar ten bit in the ucr1 register . if the uar ten, txen and rxen bits are set, then these two uar t pins will act as n ormal t x o utput p in a nd r x i nput p in r espectively. i f n o d ata i s b eing t ransmitted o n t he t x pin, then it will default to a logic high value. clearing the uar ten bit will disable the tx and rx pins and allow these two pins to be used as normal i/o or other pin-shared functional pins. when the uar t functi on is disabled the buf fer will be reset to an empty condition, at the same time discarding any remai ning residual data. disabling the uar t will also reset the error and status fags with bits txen, rxen, txbrk, rxif , oerr, ferr, perr and nf being cleared while bits tidle, txif and ridle will be set. the remaining control bits in the ucr1, ucr2 and brg registers will remain unaf fected. if the uar ten bit in the ucr1 register is cleared while the uart is active, then all pending transmissions and receptions will be immediate ly suspended and the uar t will be reset to a condition as defned above. if the uart is then subsequently re-enabled, it will restart again in the same confguration.
rev. 1.40 14 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 147 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver data, parity and stop bit selection the format of the data to be transferred is composed of various factors such as data bit length, parity on/off, parity type, address bits and the number of stop bits. these factors are determined by the setup of various bits within the ucr1 register . the bno bit controls the number of data bits which can be set to either 8 or 9, the pr t bit controls the choice of odd or even parity , the pren bit controls the parity on/of f function and the st ops bit decides whether one or two stop bits are to be used. the following table shows various formats for data transmission. the address bit identifes the frame as an address character . the number of stop bits, which can be either one or two, is independent of the data length and are only to be used for t ransmitter. there is only one stop bit for receiver. start bit data bits address bits parity bits stop bit example of 8-bit data formats 1 8 0 0 1 1 7 0 1 1 1 7 1 0 1 example of 9-bit data formats 1 9 0 0 1 1 8 0 1 1 1 8 1 0 1 transmitter receiver data format the following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats.
8-bit data format
9-bit data format uart transmitter data word lengths of either 8 or 9 bits can be selected by programming the bno bit in the ucr1 register. when bno bit is set, the word length will be set to 9 bits. in this case the 9th bit, which is the msb, needs to be stored in the tx8 bit in the ucr1 register . at the transmitter core lies the transmitter shift register , more commonly known as the tsr, whose data is obtained from the transmit data register , which is known as the txr register . the data to be transmitted is loaded into this txr register by the application program. the tsr register is not written to with new data until the st op bit from the pre vious transm ission has been se nt out. as soon as thi s st op bit has been transmitted, the tsr can then be loaded with new data from the txr register , if it is available. it should be noted that the tsr register , unlike many other registers, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write operations. an act ual transmission of data will normally be enabled when the txen bit is set, but the data will not be transmitted until the txr register has been loaded with data and the baud rate generator ha s defned a shi ft c lock sourc e. however , t he t ransmission c an a lso be i nitiated by frst loading d ata i nto t he t xr r egister, a fter wh ich t he t xen b it c an b e se t. w hen a t ransmission o f data begins, the tsr is normally empty , in which case a transfer to the txr register will result in an immediate transfer to the tsr. if during a transmission the txen bit is cleared, the transmission will imm ediately cease and the transmitter will be reset. the tx output pin will then return to the i/ o or other pin-shared function.
rev. 1.40 14? de?e??e? 0?? ?01? rev. 1.40 147 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver transmitting data when the uar t is transmitting data, the data is shifted on the tx pin from the shift register , with the l east si gnificant bi t fi rst. in t he t ransmit m ode, t he t xr re gister form s a buf fer be tween t he internal bu s a nd t he t ransmitter shi ft re gister. it shou ld be no ted t hat i f 9- bit da ta fo rmat ha s be en selected, then the msb will be take n from the tx8 bit in the ucr1 register . the steps to initiate a data transfer can be summarized as follows: ? make the correct selection of the bno, prt, pren and stops bits to defne the required word length, parity type and number of stop bits. ? setup the brg register to select the desired baud rate. ? set the txen bit to ensure that the uart transmitter is enabled and the tx pin is used as a uart transmitter pin. ? access the usr register and write the data that is to be transmitted into the txr register. note that this step will clear the txif bit. this sequence of events can now be repeated to send additional data. it should be noted that when txif is 0 , data will be inhibited from being written to the txr register . clearing the txif fag is always achieved using the following software sequence: ? a usr register access ? a txr register write execution the read-only txif fag is set by the uar t hardware and if set indic ates that the txr register is empty and that other data can now be written into the txr register without overwriting the previous data. if the teie bit is set then the txif fag will generate an interrupt. during a data transmission, a write instruction to the txr register will place the data into the txr register , which will be copied to the shift register at the end of the present transmission. when there is no data transmission in progress, a write instruction to the txr register will place the data directly into the shift register , resulting in the commencement of data transmission, and the txif bit being immediately set. when a frame transmission is complete, which happens after stop bits are sent or after the break frame, the tidle bit will be set. t o clear the tidle bit the following software sequence is used: ? a usr register access ? a txr register write execution note that both the txif and tidle bits are cleared by the same software sequence. transmit break if the txbrk bit is set then break characters will be sent on the next transmission. break character transmission consists of a start bit, followed by 13n 0 bits and stop bits, where n=1, 2, etc. if a break character is to be transmitted then the txbrk bit must be frst set by the application program and then cleared to generate the stop bits. t ransmitting a break character will not generate a transmit interrupt. note that a break condition length is at least 13 bits long. if the txbrk bit is continually kept at a logic high level then the transmitter circuitry will transmit continuous break characters. after t he a pplication p rogram h as c leared t he t xbrk b it, t he t ransmitter wi ll fn ish t ransmitting t he last break character and subsequently send out one or two stop bits. the automatic logic highs at the end of the last break character will ensure that the start bit of the next frame is recognized.
rev. 1.40 148 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 149 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver uart receiver the uart is capable of receiving word lengths of either 8 or 9 bits can be selected by programming the bno bit in the ucr register . if the bno bit is set, the word length will be set to 9 bits with the msb being stored in the rx8 bit of the ucr1 register . at the receive r core lies the receive serial shift register , commonly known as the rsr. the data which is received on the rx external input pin is sent to the data recovery block. the data recovery block operating speed is 16 times that of the baud rate , while the main receive serial shifter operates at the baud rate . after the rx pin is sampled for the stop bit, the received data in rsr is transferred to the receive data register , if the register is empty. the data which is received on the external rx input pin is sampled three times by a majority detect circuit to determine the logic level that has been placed onto the rx pin. it should be noted that the rsr register , unlike many other registers, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write operations. receiving data when the uar t receiver is receiv ing data, the data is serially shifted in on the external rx input pin to the shift register , with the lea st signifcant bit lsb frst . the rxr register is a two byte deep fifo data buf fer, where two bytes can be held in the fifo while a third byte can continue to be received. note that the application program must ensure that the data is read from rxr before the third byte has been completely shifted in, otherwise this third byte will be discarded and an overrun error oerr will be subsequently indicated. the steps to initiate a data transfer can be summarized as follows: ? make the correct selection of bno, prt and pren bits to defne the word length and parity type. ? setup the brg register to select the desired baud rate. ? set the rxen bit to ensure that the uart receiver is enabled and the rx pin is used as a uart receiver pin. at this point the receiver will be enabled which will begin to look for a start bit. when a character is received , the following sequence of events will occur: ? the rxif bit in the usr register will be set when rxr register has data available, at least one character can be read. ? when the contents of the shift register have been transferred to the rxr register and if the rie bit is set, then an interrupt will be generated. ? if during reception, a frame error, noise error, parity error, or an overrun error has been detected, then the error fags can be set. the rxif bit can be cleared using the following software sequence: ? a usr register access ? an rxr register read execution
rev. 1.40 148 de?e??e? 0?? ?01? rev. 1.40 149 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver receive break any break character received by the uar t will be managed as a framing error . the receiver will count and expect a certain number of bit times as specifed by the value s programmed into the bno and one stops bit. if the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specifed by bno and one stop bit . the rxif bit is set, ferr is set, zeros are loaded into the receive data register , interrupts are generated if appropriate and the ridle bit is set. if a long break signal has been detected and the receiver has received a start bit, the data bits and the invalid stop bit, which sets the ferr fag, the receiver must wait for a valid stop bit before looking for the next start bit. the receiver will not make the assumption that the break condition on the line is the next start bit. a break is regarded as a character that contains only zeros with the ferr fag set. the break character will be loaded into the buf fer and no further data will be receiv ed until stop bits are received. it should be noted that the ridle read only fag will go high when the stop bits have not yet been received. the reception of a break character on the uart registers will result in the following: ? the framing error fag, ferr, will be set. ? the receive data register, rxr, will be cleared. ? the oerr, nf, perr, ridle or rxif fags will possibly be set. idle status when the receiver is reading data, which means it will be in between the detection of a start bit and the readin g of a stop bit, the receiver status fag in the usr register , otherwise known as the ridle fag, will have a zero value. in between the reception of a stop bit and the detection of the next start bit, the ridle fag will have a high value, which indicates the receiver is in an idle condition. receiver interrupt the read only receive interrupt fag rxif in the usr register is set by an edge generated by the receiver. an i nterrupt i s ge nerated i f rie bi t i s 1, whe n a word i s t ransferred from t he re ceive shift re gister, rsr, t o t he re ceive da ta re gister, rxr. an ove rrun e rror c an a lso ge nerate a n interrupt if rie is 1. managing receiver errors several types of reception errors can occur within the uart module, the following section describes the various types and how they are managed by the uart. overrun error C oerr fag the rxr register is composed of a two byte deep fifo data buf fer, where two bytes can be held in the fifo register , while a third byte can continue to be received. before this third byte has been entirely shifted in, the data should be read from the rxr register . if this is not done, the overrun error fag oerr will be consequently indicated. in the event of an overrun error occurring, the following will happen: ? the oerr fag in the usr register will be set. ? the rxr contents will not be lost. ? the shift register will be overwritten. ? an interrupt will be generated if the rie bit is set. the o err flag can be cleared by an acces s to the u sr regis ter follow ed by a read to the rx r register.
rev. 1.40 1 ? 0 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 1?1 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver noise error C nf flag over-sampling i s u sed f or d ata r ecovery t o i dentify v alid i ncoming d ata a nd n oise. i f n oise i s detected within a frame the following will occur: ? the read only noise fag, nf, in the usr register will be set on the rising edge of the rxif bit. ? data will be transferred from the shift register to the rxr register. ? no interrupt will be generated. however this bit rises at the same time as the rxif bit which itself generates an interrupt. note t hat t he nf fa g i s r eset b y a usr r egister r ead o peration f ollowed b y a n r xr r egister r ead operation. framing error C ferr flag the read only framing error fag, ferr, in the usr register , is set if a zero is detected instead of stop bits. if two stop bits are select ed, only the frst stop bit is detecte d, it must be high. if the frst stop bit is low , the ferr fag will be set. the ferr fag is buf fered along with the received data and is cleared on any reset. parity error C perr flag the read only parity error fag, perr, in the usr register , is set if the parity of the received word is incorrect. this error fag is only applicable if the parity is enabled, pren bit is 1, and if the parity type, odd or e ven i s se lected. t he re ad onl y pe rr fl ag i s buf fered a long wi th t he re ceived da ta bytes. it is cleared on any reset. it should be noted that the ferr and perr fags are buf fered along with the corresponding word and should be read before reading the data word. uart module interrupt structure several i ndividual uar t c onditions c an ge nerate a uar t i nterrupt. w hen t hese c onditions e xist, a low pulse will be generated to get the attention of the microcontroller . these conditions are a transmitter data register empty , trans mitter idle, receiver data available, receiver overrun, addres s detect and an rx pin wake-up. when any of these conditions are created, if its corresponding interrupt cont rol is enabled and the sta ck is not ful l, the progra m wil l jump to it s corresponding interrupt vector w here it can be s erviced before returning to the main program. four of thes e conditions h ave t he c orresponding usr r egister fa gs wh ich wi ll g enerate a uar t i nterrupt i f i ts associated i nterrupt e nable c ontrol b it i n t he uc r2 r egister i s se t. t he t wo t ransmitter i nterrupt conditions have their own corresponding enable control bits, while the two receiver interrupt conditions have a shared enable control bit. these enable bits can be used to mask out individual uart interrupt sources. the address det ect condit ion, whic h is al so a uar t i nterrupt source, does not have an associa ted flag, but will generate a uar t interrupt when an address detect condition occurs if its function is enabled by setting the adden bit in the ucr2 register . an rx pin wake-up, which is also a uart interrupt source, does not have an associated fag, but will generate a uar t interrupt if the microcontroller i s woke n up from idl e0 or sl eep m ode by a fa lling e dge on t he rx pi n, i f t he wake and rie bits in the ucr 2 register are set. note that in the event of an rx wake-up interrupt occurring, there will be a certain period of delay , commonly known as the system start-up t ime, for the oscillator to restart and stabilize before the system resumes normal operation.
rev. 1.40 1?0 de?e??e? 0?? ?01? rev. 1.40 1 ? 1 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver note t hat t he usr r egister f lags a re r ead o nly a nd c annot b e c leared o r se t b y t he a pplication program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the cas e for some of the other interrupts. the flags will be cleared automatically whe n c ertain a ctions a re t aken by t he uar t, t he de tails of whi ch a re gi ven i n t he uart regi ster se ction. the overal l uar t i nterrupt ca n be disable d or ena bled by t he rel ated interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether the interrupt requested by the uart module is masked out or allowed. t?ans?itte? e?pty flag txif usr registe? t?ans?itte? idle flag tidle re?eive? ove??un flag oerr re?eive? data availa?le rxif adden rx pin wake-up wake 0 1 0 1 0 1 rx7 if bno=0 rx8 if bno=1 ucr? registe? or rie 0 1 tiie 0 1 teie 0 1 uart inte??upt request flag uartf ucr? registe? uarte intc? registe? emi intc0 registe? uart interrupt scheme address detect mode setting t he addre ss de tect mode bi t, adde n, i n t he ucr2 re gister, e nables t his spe cial m ode. if this bit is enabled then an additional qualifier will be placed on the generation of a receiver data a vailable interrupt, which is requested by the rxif fag. if the adden bit is 1 , then when data is available, an interrupt will only be generated, if the highest received bit has a high value. note that the related interrupt enable control bit and the emi bit must also be enabled for correct interrupt generation. this highest address bit is the 9th bit if bno bit is 1 or the 8th bit if bno bit is 0 . if this bit is high, then the received word will be defned as an address rather than data. a data a vailable interrupt will be generated every time the last bit of the received word is set. if the adden bit is 0 , then a receiver data a vailable interrupt will be generated each time the rxif fag i s se t, i rrespective o f t he d ata l ast b it st atus. t he a ddress d etect m ode a nd p arity e nable a re mutually exclusive functions. therefore if the address detect mode is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity enable bit pren to zero. adden bit 9 if bno=1, bit 8 if bno=0 uart interrupt generated 0 0 1 1 0 1 adden bit function
rev. 1.40 1 ?? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 1?3 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver uart power down and wake-up when the the device system clock is switched of f , the uar t will cease to function. if the device executes the halt instruction and switches of f the system clock while a transmission is still in progres s, then the trans mission w ill be paus ed until the u art clock s ource derived from the microcontroller is activated. in a similar way , if the device executes the halt instruction and switches of f the system clock while receiving data, then the reception of data will likewise be paused. when the device enters the idle or sleep mode, note that the usr, ucr1, ucr2, transmit and recei ve registers, as well as the brg register will not be af fected. it is recommended to make sure first that the ua rt data transmis sion or reception has been finished before the microcontroller enters the idle or sleep mode. the uar t function contains a rece iver rx pin wake-up function, which is enabled or disabled by the w ake bit in the ucr2 register . if this bit, along with the uar t enable bit, uar ten, the receiver enable bit, rxen and the receiver interrupt bit, rie, are all set before the device enters the idle0 or sleep mode, then a falling edge on the rx pin will wake up the uart function from the idle0 or sleep mode. note that as it takes certain system clock cycles after a wake-up, before normal microcontroller operation resumes, any data received during this time on the rx pin will be ignored. for a uar t wake-up interrupt to occur , in addition to the bits for the wake-up being set, the global interrupt enable bit, emi, and the uart interrupt enable bit, u ar t e, must also be set. if these two bits are not set then only a wake up event will occur and no interrupt will be generated. note also that as it takes certain system clock cycles after a wake-up before normal microcontroller resumes, the uart interrupt will not be generated until after this time has elapsed.
rev. 1.40 1?? de?e??e? 0?? ?01? rev. 1.40 1 ? 3 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver interrupts interrupts are an important part of any microcontroller s ystem. when an external event or an internal function such as a t ouch action or t imer/event counter overfow requires microcontroller attention, their corres ponding interrupt w ill enforce a temporary s uspension of the main program allowing the microcontroller to direct attention to their respective needs. the device s contain several external interrupt and internal interrupt functions. t he external interrupt is generated by the action of the external int pin and t ouch keys , while the internal interrupts are generated by various internal functions such as t imer modules , t ime base s , sim, lvd, eeprom, a/d converter and uart . interrupt registers overall interrupt control, w hich bas ically means the s etting of reques t flags w hen certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is control led by a series of registers, located in the special purpose data memory , as shown in the accompanying table. the registers fall into two categories. the frst is the intc0~intc 3 registers which setup the primary interrupts, the second is the integ register to setup the external interrupt trigger edge type. each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/disable bit or f for request fag. function enable bit request flag notes glo ? al emi int pin inte intf tou ? h key module tkme tkmf sim sime simf uart uarte uartf eeprom dee def lvd lvde lvdf ti ? e base tbne tbnf n=0 o ? 1 a/d conve ? te ? ade adf tm ctmpne ctmpnf n=0 ptmpne ptmpnf n=1 o ? ? ctmane ctmanf n=0 ptmane ptmanf n=1 o ? ? interrupt register bit naming conventions interrupt register contents name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 integ ints1 ints0 intc0 tb0f tkmf intf tb0e tkme inte emi intc1 ptma1f ptmp1f ctma0f ctmp0f ptma1e ptmp1e ctma0e ctmp0e intc ? uartf def simf tb1f uarte dee sime tb1e intc3 ptma ? f ptmp ? f adf lvdf ptma ? e ptmp ? e ade lvde
rev. 1.40 1 ? 4 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 1?? de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver integ register bit 7 6 5 4 3 2 1 0 na ? e ints1 ints0 r/w r/w r/w por 0 0 b it 7 ~ 2 unimplemented, read as 0 b it 1 ~ 0 ints1, ints0 : defnes int interrupt active edge 00 : disabled interrupt 0 1: rising edge interrupt 10 : falling edge interrupt 11 : dual edge interrupt intc0 register bit 7 6 5 4 3 2 1 0 na ? e tb0f tkmf intf tb0e tkme inte emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 b it 7 unimplemented, read as 0 b it 6 tb0f : time base 0 i nterrupt r equest fag 0: no request 1: interrupt request b it 5 tkmf : t ouch key module interrupt request fag 0: no request 1: interrupt request b it 4 intf : int pin interrupt request fag 0: no request 1: interrupt request b it 3 tb0e : t ime base 0 i nterrupt control 0: disable 1: enable b it 2 tkme : t ouch key module i nterrupt control 0: disable 1: enable b it 1 inte : int pin i nterrupt control 0: disable 1: enable b it 0 emi : global interrupt control 0: disable 1: enable
rev. 1.40 1?4 de?e??e? 0?? ?01? rev. 1.40 1 ?? de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver intc1 register bit 7 6 5 4 3 2 1 0 na ? e ptma1f ptmp1f ctma0f ctmp0f ptma1e ptmp1e ctma0e ctmp0e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ptma1f : ptm1 ccra comparator interrupt request fag 0: no request 1: interrupt request b it 6 ptmp1 f : ptm1 ccrp comparator interrupt request fag 0: no request 1: interrupt request b it 5 ctma0f : ctm0 ccra comparator interrupt request fag 0: no request 1: interrupt request b it 4 ctmp0f: ctm0 ccrp comparator interrupt request fag 0: no request 1: interrupt request bit 3 ptma1e : ptm1 ccra comparator interrupt control 0: disable 1: enable b it 2 ptmp1e : ptm1 ccrp comparator interrupt control 0: disable 1: enable b it 1 ctma0e : ctm0 ccra comparator interrupt control 0: disable 1: enable b it 0 ctmp0e : ctm0 ccrp comparator interrupt control 0: disable 1: enable intc2 register bit 7 6 5 4 3 2 1 0 na ? e uartf def simf tb1f uarte dee sime tb1e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 uartf : uart interrupt request fag 0: no request 1: interrupt request b it 6 def : data eeprom i nterrupt r equest flag 0: no request 1: interrupt request b it 5 simf : sim i nterrupt r equest flag 0: no request 1: interrupt request b it 4 tb1f: t ime base 1 i nterrupt r equest flag 0: no request 1: interrupt request b it 3 uarte : uart interrupt request control 0: disable 1: enable
rev. 1.40 1 ?? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 1?7 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver b it 2 dee : data eeprom control 0: disable 1: enable b it 1 sime : sim i nterrupt control 0: disable 1: enable b it 0 tb1e : time base 1 i nterrupt control 0: disable 1: enable intc3 register bit 7 6 5 4 3 2 1 0 na ? e ptma ? f ptmp ? f adf lvd f ptma ? e ptmp ? e ade lvd e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ptma2f : ptm2 ccra comparator interrupt request fag 0: no request 1: interrupt request b it 6 ptmp2f : ptm2 ccrp comparator interrupt request fag 0: no request 1: interrupt request b it 5 adf : a/d converter i nterrupt r equest flag 0: no request 1: interrupt request b it 4 lvd f: lvd i nterrupt r equest flag 0: no request 1: interrupt request b it 3 ptma2e : ptm2 ccra comparator i nterrupt control 0: disable 1: enable b it 2 ptmp2e : ptm2 ccrp comparator i nterrupt control 0: disable 1: enable b it 1 ade : a/d converter i nterrupt control 0: disable 1: enable b it 0 lvd e : lvd i nterrupt control 0: disable 1: enable
rev. 1.40 1?? de?e??e? 0?? ?01? rev. 1.40 1 ? 7 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver interrupt operation when the conditions for an interrupt event occur , such as a t ouch key counter overflow , a tm comparator p or comparator a match , etc, the relevant interrupt request fag will be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. if the enable bit is set high then the program will jump to its releva nt vector ; if the enable bit is zero then although the interrup t request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector . the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . the microcontroller will then fetch its next instruction from this interrupt vector . the instruction at this vector will usually be a jmp which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated w ith a reti, w hich retrieves the original p rogram counter address from the st ack a nd a llows t he m icrocontroller t o c ontinue wi th n ormal e xecution a t t he p oint wh ere t he interrupt occurred. the va rious i nterrupt e nable bi ts, t ogether wi th t heir a ssociated re quest fl ags, a re shown i n t he accompanying diagrams with their order of priority . every interrupt source ha s its own individual vector. once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically . this will prevent any further interrupt nesting from occurring. however , if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is a pplied. all o f t he i nterrupt r equest fa gs wh en se t wi ll wa ke-up t he d evice i f i t i s i n sl eep o r idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode.
rev. 1.40 1 ? 8 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 1?9 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver int pin tou?h key module intf tkmf inte tkme emi 04 h emi ?4 h ?8 h inte??upt na?e request flags ena?le bits maste? ena?le vector emi auto disa?led in isr p?io?ity high low ctm 0 a ctma 0f ctma 0e xxe ena?le bits xxf request flag ? auto ?eset in isr legend emi 08 h sim sim f sim e emi 10 h emi 14 h ti?e base 1 tb 1f tb 1e ti?e base 0 tb 0f tb 0e emi 0 ch eeprom def dee emi 18 h 1 ch ctm 0 p ctmp 0f ctmp 0e emi ?0 h ptm 1 p ptmp1f ptmp1e emi ptm 1 a ptma1f ptma1e emi emi ? ch uart uart f uart e emi 30 h lvd lvdf lvde emi 34 h a/d adf ade 38 h 3 ch ptm ? p ptmp?f ptmp?e emi ptm ? a ptma?f ptma?e emi interrupt structure external interrupt the e xternal i nterrupt is c ontrolled by si gnal t ransitions on t he pi n int . an e xternal i nterrupt request will take place when the external interrupt request flag, intf , is set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pin. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, inte, must frst be set. additionally the correc t i nterrupt edge t ype must be se lected usi ng t he int eg regi ster t o ena ble t he ext ernal interrupt function and to choose the trigger edge type. as the external interrupt pin is pin-shared with i/o pin, it can only be confgured as external interrupt pin if its external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register . when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector , will take place. when the interrupt is serviced, the external interrupt request fag, intf, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on the external interrupt pin will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function.
rev. 1.40 1?8 de?e??e? 0?? ?01? rev. 1.40 1 ? 9 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver a/d converter interrupt the a/d converter interrupt is controlled by the termination of an a/d conversion process. an a/ d converter interrupt request will take place when the a/d converter interrupt request fag, adf , is se t, wh ich o ccurs wh en t he a/ d c onversion p rocess f inishes. t o a llow t he p rogram t o b ranch to its respective interrupt vector address, the global interrupt enable bit, emi, and a/d interrupt enable bi t, ade , m ust frst be se t. w hen t he i nterrupt i s e nabled, t he st ack i s not ful l a nd t he a/ d conversion process has ended, a subroutine call to the a/d converter interrupt vector , will take place. when the interrupt is serviced, the a/d converter interrupt fag, adf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. time base interrupts the function of the t ime base interrupt is to provide regular time signal in the form of an internal interrupt. it is controlled by the overflow signal from its timer function. when th is happens its interrupt request flags tb n f wil l be set . t o all ow the program to branch t o its inte rrupt vect or address, the global interrupt enable bit, emi and t ime base enable bit, tb n e, must frst be set. when the interrup t is enabled, the stack is not full and the t ime base overfows, a subroutine call to its vector location will take place. when the interrupt is serviced, the interrupt request fag, tb n f, will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the t ime base interrupt is to provide an interrupt signal at fxed time periods. each time base clock source originate s from an independent internal prescaler . each 15-bit prescaler can source from f sys , f sys /4, f sub or f h , selected by clkseln1~clkseln0 bits in the pscr register. pscr register bit 7 6 5 4 3 2 1 0 na ? e clksel11 clksel10 clksel01 clksel00 r/w r/w r/w r/w r/w por 0 0 0 0 b it 7 ~6 unimplemented, read as 0 b it 5~4 clksel11 ~ clksel10 : t ime base 1 prescaler clock source selection 00: f sys 01: f sys /4 10: f sub 11: f h b it 3 ~2 unimplemented, read as 0 b it 1~0 clksel01 ~ clksel00 : t ime base 0 prescaler clock source selection 00: f sys 01: f sys /4 10: f sub 11: f h
rev. 1.40 1 ? 0 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 1?1 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver tbc register bit 7 6 5 4 3 2 1 0 na ? e tb1on tb1 ? tb1 1 tb10 tb0on tb0 ? tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 tb1on : t ime base 1 enable/disable control 0: disable 1: enable b it 6~4 tb12 ~ tb10 : select t ime base 1 time-out period 0 00: 2 8 /f psc 0 01: 2 9 /f psc 0 10: 2 10 /f psc 0 11: 2 11 /f psc 100: 2 12 /f psc 101: 2 13 /f psc 110: 2 14 /f psc 111: 2 15 /f psc b it 3 tb0on : t ime base 0 enable/disable control 0: disable 1: enable b it 2~0 tb02 ~ tb00 : select t ime base 1 time-out period 0 00: 2 8 /f psc 0 01: 2 9 /f psc 0 10: 2 10 /f psc 0 11: 2 11 /f psc 100: 2 12 /f psc 101: 2 13 /f psc 110: 2 14 /f psc 111: 2 15 /f psc f sys /4 clks el n[1: 0 ] f su b f sys p?es?ale? tb non f psc ti?e base n inte??upt f h tb n[?: 0 ] time base structure (n=0 or 1) tm interrupts the compact and periodic type tms each has two internal interrupts, the internal comparator a or comparator p , which generate s a tm interrupt when a compare match condition occurs. for each of t he compac t and pe riodic t ype tms, t here are t wo i nterrupt request fa gs, ctmp0f/ct ma0f and pt mpnf/ptmanf, and two enabl e bit s, ctmp0e /ctma0e and pt mpne/ptmane. a tm interrupt request will take place when any of the tm request fags are set, a situation which occur s when a tm comparator p or a macth situation happens . to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, the respective tm interrupt enable bit must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs , a subroutine call to the relevant tm interrupt vector location , will take place. when the tm interrupt is serviced, the tm interrupt request fag will be automatically reset and the emi bit will be automatically cleared to disable other interrupts.
rev. 1.40 1?0 de?e??e? 0?? ?01? rev. 1.40 1 ? 1 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver eeprom interrupt an eeprom interrupt request will take place when the eeprom interrupt request fag, def, is set, which occurs when an eeprom w rite cycle ends. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and eeprom interrupt enable bit, dee, must frst be set. when the interrupt is enabled, the stack is not full and an eeprom w rite cycle ends, a subroutine call to the respective eeprom interrupt vect or, will take place. when the eeprom interrupt is serviced, the def fag will be automatically cleared and the emi bit will be automatically cleared to disable other interrupts. lvd interrupt an l vd interrupt request will take place when the l vd interrupt request fag, l v d f, is set, which occurs when the low v oltage detector function detects a low power supply voltage. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and low v oltage interrupt enable bit, l v d e, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the lvd interrupt vector, will take place. when the low v oltage interrupt is serviced, the l vdf fag will be automatically cleared and the emi bit will be automatically cleared to disable other interrupts. touch key interrupt for a t ouch key interrupt to occur, the global interrupt enable bit, emi, and the t ouch key interrupt enable tkme must be frst set. an actual t ouch key interrupt will take place when the t ouch key request fag. tkmf , is set, a situation that will occur when the time slot counter overfows. when the interrupt is enabled, the stack is not full and the t ouch key time slot counter overfow occurs, a subroutine call to the relevant timer interrupt vector , will take place. when the interrupt is serviced, the t ouch key interrupt request fag, tkmf , will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. serial interface module interrupt the serial interface module interrupt is also known as the sim interr upt. a sim interrupt request will take place when the sim interrupt request fag, sim f, is set, which occurs when a byte of data has been received or transmitted by the spi or i 2 c interface , or an i 2 c address match occurs, or an i 2 c communication time-out occurs . t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the sim interface interrupt enable bit, sim e, must frst be set. when the interrupt is enabled, the stack is not full and any these conditions are created , a subroutine call to the respective interrupt vector , will take place. when the sim interface interrupt is serviced, the sim interrupt request fag, sim f, will be automatically cleared and the emi bit will be automatically cleared to disable other interrupts.
rev. 1.40 1 ?? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 1?3 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver uart interrupt several i ndividual uar t c onditions c an ge nerate a uar t i nterrupt. w hen t hese c onditions e xist, a low pulse will be generated to get the attention of the microcontroller . these conditions are a transmitter data register empty , trans mitter idle, receiver data available, receiver overrun, addres s detect and an rx pin wake-up. t o allow the program to branch to the respective interrupt vector addresses, the global interrupt enable bit, emi, and uar t interrupt enable bit, uar t e, must frst be set. when the interrupt is enabled, the stack is not full and any of these conditions are created, a subroutine call to the uar t interrupt vector will take place. when the interrupt is serviced, the uart interrupt fag, uar t f, will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. however , the usr register fags will be cleared automatically when certain actions are taken by the uart, the details of which are given in the uart section. interrupt wake-up function each of the int errupt funct ions has the capa bility of waki ng up the mi crocontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on t he e xternal i nterrupt pi n or a l ow powe r sup ply vol tage m ay c ause t heir re spective interrupt fag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no effect on the interrupt wake-up function. programming considerations by disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately . if only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every i nterrupt h as t he c apability o f wa king u p t he m icrocontroller wh en i t i s i n sl eep o r i dle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator , status register or other registers are altered by the interrupt service program, t heir c ontents shoul d be sa ved t o t he m emory a t t he be ginning of t he i nterrupt se rvice routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts.
rev. 1.40 1?? de?e??e? 0?? ?01? rev. 1.40 1 ? 3 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver scom and sseg function for lcd the devices have the capability of driving external lcd panels. the common pins for lcd driving, scom0~scom3, sseg0~sseg19, are pin shared w ith certain pin s on the i/o port s . the lcd signals (com and seg) are generated using the application program. device coms segs bs8 ? b1 ? a-3 scom0~scom3 sseg0~sseg1 ? bs8 ? c1 ? a-3 sseg0~sseg19 bs8 ? d ? 0a-3 lcd operation an external lcd panel can be driven using th e device s by confguring the i/o pins as common pins and confguring the i/o pins as segment pins. the lcd driver function is controlled using the lcd control registers which in addition to controlling the overall on/of f function also controls the scom and sseg operating current . this enables the lcd com and seg driver to generate the necessary v ss , (1/3)v dd , (2/3)v dd voltage and v dd levels for lcd 1/3 bias operation. the lcden bit in the slcdc0 register is the overall master control for the lcd driver , however this bit is used in conjunction with the comnen and segnen bits to select which i/o port pins are used for lcd driving. note that the port control register does not need to frst setup the pins as outputs to enable the lcd driver operation. lcd driver structure the acco mpanying waveform diagram shows a typical 1/3 bias lcd waveform generated using the application program. note that the depiction of a 1 in the diagram illustrates an illuminated lcd pixel. the com signal polarity generated on pins scom0~scom3, whether 0 or 1, are generated using the corresponding i/o data register bits , which are bits pa0~pa2, pa4 in the pa register.
rev. 1.40 1 ? 4 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 1?? de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver note: the logical values shown in the diagram are the pa i/o register bit values, pa0~pa2, pa4. 1/3 bias lcd waveform a cyclic lcd waveform includes two frames, known as frame 0 and frame 1 for which the following offers a functional explanation. in frame 0 to select frame 0 clear the frame bit to 0. in frame 0, the com signal output can have a value of v dd , or have a v bias value of (1/3)v dd . the seg signal can have a value of v ss , or have a v bias value of (2/3)v dd . in frame 1 in frame 1, the com signal output can have a value of v ss , or have a v bias value of (2/3)v dd . the seg signal can have a value of v dd have a vbias value of (1/3)v dd . the com0~comn waveform is controlled by the application program using the frame bit, and the corresponding i/o data register for the respective com pin to determine whether the com0~comn output has a value of either v dd , v ss or v bias . the seg0~segm waveform is controlled in a similar way usi ng t he fr ame bi t a nd t he c orresponding i/ o da ta re gister fo r t he re spective se g pi n t o determine whether the seg0~segn output has a value of either v dd , v ss or v bias .
rev. 1.40 1?4 de?e??e? 0?? ?01? rev. 1.40 1 ?? de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver lcd bias control the lcd com and seg driver enable a range of selections to be provided to suit the requirement of the lcd panel which are being used. the bias resistor choice is implemented using the isel1 and isel0 bits in the slcdc0 register. slcdc0 register bit 7 6 5 4 3 2 1 0 na ? e frame isel1 isel0 lcden com3en com ? en com1en com0en r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 frame : fram 0 or frame 1 output selection 0: frame 0 1: frame 1 bit 6 ~5 isel1~isel0 : scom and sseg operating current selection (v dd =5v) 00 : 8.3a 0 1: 16.7a 10: 50 a 11: 100 a bit 4 lcden : scom and sseg module on/off control 0: disable 1: enable the scomn and ssegm lines can be enabled using comnen and segmen if lcden=1. when lcden=0, then the scomn and ssegm outputs will be fxed at a v ss level. bit 3 com3en : scom3 or other function selection 0: other function 1: scom3 bit 2 com2en : scom2 or other function selection 0: other function 1: scom2 bit 1 com1en : scom1 or other function selection 0: other function 1: scom1 bit 0 com0en : scom0 or other function selection 0: other function 1: scom0
rev. 1.40 1 ?? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 1?7 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver s lcdc1 register bit 7 6 5 4 3 2 1 0 na ? e seg7en seg ? en seg ? en seg4en seg3en seg ? en seg1en seg0en r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 seg7en~seg0en : sseg7 ~ sseg0 or other function selection 0: other function 1: sseg7~sseg0 slcdc2 register bit 7 6 5 4 3 2 1 0 na ? e seg1 ? en seg14en seg13en seg1 ? en seg11en seg10en seg9en seg8en r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 seg15en~seg8en : sseg15 ~ sseg8 or other function selection 0: other function 1: sseg15~sseg8 slcdc3 register bs86c16a-3/BS86D20A-3 only bit 7 6 5 4 3 2 1 0 na ? e seg19en seg18en seg17en seg1 ? en r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3~0 seg19en~seg16en : sseg19 ~ sseg16 or other function selection 0: other function 1: sseg19~sseg16 low voltage detector C lvd each device has a low v oltage detector function, also known as l vd. this enable s the device to monitor the power supply voltage, v dd , and provide s a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low v oltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name l vdc. three bits i n t his r egister, vl vd2~vlvd0, a re u sed t o se lect o ne o f fve fx ed v oltages b elow wh ich a low volta ge condition will be detemined. a low voltage condition is indicated when the l vdo bit is set. if the l vdo bit is low , this indicates that the v dd voltage is above the preset low voltage value. the l vden bit is used to control the overall on/of f function of the low voltage detector . setting the bit high will enable the low voltage detector . clearing the bit to zero will switch of f the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch of f the circuit when not in use, an important consideration in power sensitive battery powered applications.
rev. 1.40 1?? de?e??e? 0?? ?01? rev. 1.40 1 ? 7 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver lvdc register bit 7 6 5 4 3 2 1 0 na ? e lvdo lvden vlvd ? vlvd1 vlvd0 r/w r r/w r/w r/w r/w por 0 0 0 0 0 b it 7 ~ 6 unimplemented, read as 0 b it 5 lvdo : lvd output flag 0: no low v oltage detect 1: low v oltage detect b it 4 lvden : low v oltage detector control 0: disable 1: enable b it 3 unimplemented, read as 0 b it 2~0 vl vd2 ~ vlvd0 : select lvd v oltage 000: 2.0v 001: 2.2v 010: 2.4v 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.0v note: the v lvr of these two devices is fxed at 2.55v , so the v lvd should be set to 2.7v~4.0v. lvd operation the low v oltage detector function operates by comparing the power supply voltage, v dd , with a pre-specifed volta ge level stored in the l vdc register . this has a range of between 2. 7 v and 4.0v . when the power supply voltage, v dd , falls below this pre-determined value, the l vdo bit will be set high indicating a low power supply voltage condition. the low v oltage detector function is supplied by a reference voltage which will be automatically enabled. when the device is in sleep mode the low voltage detector will be automatically disabled even if the l vden bit is high . after enabling the low v oltage detector , a time delay t lvds should be allowed for the circuitry to stabilise before reading the l vdo bit. note also that as the v dd voltage may rise and fall rather slowly , at the voltage nears that of v lvd , there may be multiple bit lvdo transitions. lvd operation the low v oltage detector also has its own interrupt, providing an alte rnative means of low voltage detection, in addition to polling the l vdo bit. the interrupt will only be generated after a delay of t lvd a fter t he l vdo b it ha s be en se t hi gh by a l ow vo ltage c ondition. in t his c ase, t he l v d f interrupt request fag will be set, causing an interrupt to be generated if v dd falls below the preset lvd voltage. this will cause the device to wake-up from the sleep or idle mode, however if the low v oltage detector wake up function is not required then the l v d f fag should be frst set high before the device enters the sleep or idle mode.
rev. 1.40 1 ? 8 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 1?9 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver confguration options confguration options reer to certa in options ithin the c that are programmed into the device during the programming process during the development process these options are selected using the t ide sotare development tools s these options are programmed into the device using the harda re programm ing tools once they are sel ected they cannot e changed la ter using the application program ll options must e defned or proper system unction the details o hich are shon in the tale no. options oscillator option 1 low speed syste ? os ? illato ? sele ? tion C f sub : lirc lxt ? hirc f ? equen ? y sele ? tion: 8mhz 1 ? mhz 1 ? mhz 1rwh 7kh orz vshhg vvwhp rvfloodwru vhohfwlrq lv rqo iru wkh %?& dqg %?' :khq wkh +??& kdv ehhq frqjxudwhg dw d iuhtxhqf vkrzq lq wklv wdeoh wkh +??&? dqg +??&? %lwv lv uhfrpphqghg wr eh vhwxs wr vhohfw wkh vdph iuhtxhqf wr nhhs wkh +??& iuhtxhqf dffxudf vshglhg lq wkh & fkdudfwhulvwlfv application circuit vdd vss key 1 0.1 uf i/ o pins sim pins v dd key ? key n uart pins scom & sseg pins xt 1 xt ? osc ci??uit see os?illato? se?tion an 0~ an 7
rev. 1.40 1?8 de?e??e? 0?? ?01? rev. 1.40 1 ? 9 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. in the case of holtek microcontroller , a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator , most instructions would be i mplemented wi thin 0.5 s a nd bra nch or c all i nstructions woul d be i mplemented wi thin 1s. although instructions which require one more cycle to implement are generally limited to the jmp , call, ret , reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. e xamples of suc h i nstructions would be "clr pcl" or "mov pcl, a". for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the ac cumulator. one of t he m ost i mportant da ta t ransfer a pplications i s t o re ceive da ta from t he input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. w ithin t he hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.40 170 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 171 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within t he hol tek m icrocontroller i nstruction se t. as wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he ac cumulator wh ich m ay i nvolve a dditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. dif ferent rotate instructions exist depending on program requirements. rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he ca rry bit from where it can be examined and the necessary serial bit set high or low . another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or t o a su broutine usi ng t he cal l i nstruction. t hey di ffer i n t he se nse t hat i n t he c ase of a subroutine call, the program mus t return to the ins truction immediately w hen the s ubroutine has been carried out. this is done by placing a return ins truction " ret" in the s ubroutine w hich w ill cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping of f point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these i nstructions a re t he ke y t o de cision m aking a nd bra nching wi thin t he progra m pe rhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the abili ty to provide single bit operations on data memory is an extremely fexible feature of all holtek m icrocontrollers. t his fe ature i s e specially use ful for out put port bi t progra mming whe re individual bits or port pins can be directly set high or low using either the "set [m].i" or "clr [m]. i" i nstructions r espectively. t he f eature r emoves t he n eed f or p rogrammers t o fr st r ead t he 8 -bit output port, manip ulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is take n care of automatically when these bit operation instructions are used. table read operations data st orage i s norm ally i mplemented by usi ng re gisters. however , whe n worki ng wi th l arge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory . t o overcome this problem, holtek microcontrollers allow an area of program memory to be set as a table where data can be directly stored. a set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the "hal t" i nstruction f or po wer-down o perations a nd i nstructions t o c ontrol t he o peration o f the w atchdog t imer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.40 170 de?e??e? 0?? ?01? rev. 1.40 171 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver instruction set summary the i nstructions re lated t o t he da ta m emory a ccess i n t he fol lowing t able c an be used whe n t he desired data memory is located in data memory sector 0. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a ? [ ? ] add data me ? o ? y to acc 1 z ? c ? ac ? ov ? sc addm a ? [ ? ] add acc to data me ? o ? y 1 note z ? c ? ac ? ov ? sc add a ? x add i ?? ediate data to acc 1 z ? c ? ac ? ov ? sc adc a ? [ ? ] add data me ? o ? y to acc with ca ?? y 1 z ? c ? ac ? ov ? sc adcm a ? [ ? ] add acc to data ? e ? o ? y with ca ?? y 1 note z ? c ? ac ? ov ? sc sub a ? x su ? t ? a ? t i ?? ediate data f ? o ? the acc 1 z ? c ? ac ? ov ? sc ? cz sub a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc 1 z ? c ? ac ? ov ? sc ? cz subm a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc with ? esult in data me ? o ? y 1 note z ? c ? ac ? ov ? sc ? cz sbc a ? x su ? t ? a ? t i ?? ediate data f ? o ? acc with ca ?? y 1 z ? c ? ac ? ov ? sc ? cz sbc a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc with ca ?? y 1 z ? c ? ac ? ov ? sc ? cz sbcm a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc with ca ?? y ? ? esult in data me ? o ? y 1 note z ? c ? ac ? ov ? sc ? cz daa [ ? ] de ? i ? al adjust acc fo ? addition with ? esult in data me ? o ? y 1 note c logic operation and a ? [ ? ] logi ? al and data me ? o ? y to acc 1 z or a ? [ ? ] logi ? al or data me ? o ? y to acc 1 z xor a ? [ ? ] logi ? al xor data me ? o ? y to acc 1 z andm a ? [ ? ] logi ? al and acc to data me ? o ? y 1 note z orm a ? [ ? ] logi ? al or acc to data me ? o ? y 1 note z xorm a ? [ ? ] logi ? al xor acc to data me ? o ? y 1 note z and a ? x logi ? al and i ?? ediate data to acc 1 z or a ? x logi ? al or i ?? ediate data to acc 1 z xor a ? x logi ? al xor i ?? ediate data to acc 1 z cpl [ ? ] co ? ple ? ent data me ? o ? y 1 note z cpla [ ? ] co ? ple ? ent data me ? o ? y with ? esult in acc 1 z increment & decrement inca [ ? ] in ?? e ? ent data me ? o ? y with ? esult in acc 1 z inc [ ? ] in ?? e ? ent data me ? o ? y 1 note z deca [ ? ] de ?? e ? ent data me ? o ? y with ? esult in acc 1 z dec [ ? ] de ?? e ? ent data me ? o ? y 1 note z rotate rra [ ? ] rotate data me ? o ? y ? ight with ? esult in acc 1 none rr [ ? ] rotate data me ? o ? y ? ight 1 note none rrca [ ? ] rotate data me ? o ? y ? ight th ? ough ca ?? y with ? esult in acc 1 c rrc [ ? ] rotate data me ? o ? y ? ight th ? ough ca ?? y 1 note c rla [ ? ] rotate data me ? o ? y left with ? esult in acc 1 none rl [ ? ] rotate data me ? o ? y left 1 note none rlca [ ? ] rotate data me ? o ? y left th ? ough ca ?? y with ? esult in acc 1 c rlc [ ? ] rotate data me ? o ? y left th ? ough ca ?? y 1 note c
rev. 1.40 17 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 173 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver mnemonic description cycles flag affected data move mov a ? [ ? ] move data me ? o ? y to acc 1 none mov [ ? ] ? a move acc to data me ? o ? y 1 note none mov a ? x move i ?? ediate data to acc 1 none bit operation clr [ ? ].i clea ? ? it of data me ? o ? y 1 note none set [ ? ].i set ? it of data me ? o ? y 1 note none branch operation jmp add ? ju ? p un ? onditionally ? none sz [ ? ] skip if data me ? o ? y is ze ? o 1 note none sza [ ? ] skip if data me ? o ? y is ze ? o with data ? ove ? ent to acc 1 note none sz [ ? ].i skip if ? it i of data me ? o ? y is ze ? o 1 note none snz [ ? ] skip if data me ? o ? y is not ze ? o 1 note none snz [ ? ].i skip if ? it i of data me ? o ? y is not ze ? o 1 note none siz [ ? ] skip if in ?? e ? ent data me ? o ? y is ze ? o 1 note none sdz [ ? ] skip if de ?? e ? ent data me ? o ? y is ze ? o 1 note none siza [ ? ] skip if in ?? e ? ent data me ? o ? y is ze ? o with ? esult in acc 1 note none sdza [ ? ] skip if de ?? e ? ent data me ? o ? y is ze ? o with ? esult in acc 1 note none call add ? su ?? outine ? all ? none ret retu ? n f ? o ? su ?? outine ? none ret a ? x retu ? n f ? o ? su ?? outine and load i ?? ediate data to acc ? none reti retu ? n f ? o ? inte ?? upt ? none table read operation tabrd [ ? ] read table (specifc page) to tblh and data memory ? note none tabrdl [ ? ] read ta ? le (last page) to tblh and data me ? o ? y ? note none itabrd [ ? ] increment table pointer tblp frst and read table to tblh and data memory ? note none itabrdl [ ? ] increment table pointer tblp frst and read table (last page) to tblh and data me ? o ? y ? note none miscellaneous nop no ope ? ation 1 none clr [ ? ] clea ? data me ? o ? y 1 note none set [ ? ] set data me ? o ? y 1 note none clr wdt clea ? wat ? hdog ti ? e ? 1 to ? pdf swap [ ? ] swap ni ?? les of data me ? o ? y 1 note none swapa [ ? ] swap ni ?? les of data me ? o ? y with ? esult in acc 1 none halt ente ? powe ? down ? ode 1 to ? pdf 1rwh )ru vnls lqvwuxfwlrqv li wkh uhvxow ri wkh frpsdulvrq lqyroyhv d vnls wkhq xs wr wkuhh ffohv duh uhtxluhg li qr vnls wdnhv sodfh rqo rqh ffoh lv uhtxluhg q lqvwuxfwlrq zklfk fkdqjhv wkh frqwhqwv ri wkh 3&/ zloo dovr uhtxluh ffohv iru h[hfxwlrq )ru wkh &/? :'7 lqvwuxfwlrq wkh 7 ? dqg 3') djv pd eh di ihfwhg e wkh h[hfxwlrq vwdwxv 7kh 7 ? dqg 3') djv duh fohduhg diwhu wkh &/? :'7 lqvwuxfwlrqv lv h[hfxwhg ?wkhuzlvh wkh 7 ? dqg 3') djv uhpdlq xqfkdqjhg
rev. 1.40 17? de?e??e? 0?? ?01? rev. 1.40 173 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver extended instruction set the extended instructions are used to support the full range address access for the data memory . when the accessed data memory is located in any data memory sections except sector 0, the extended instructi on can be used to access the data memory instead of using the indirect addressing access to improve the cpu frmware performance. mnemonic description cycles flag affected arithmetic ladd a ? [ ? ] add data me ? o ? y to acc ? z ? c ? ac ? ov ? sc laddm a ? [ ? ] add acc to data me ? o ? y ? note z ? c ? ac ? ov ? sc ladc a ? [ ? ] add data me ? o ? y to acc with ca ?? y ? z ? c ? ac ? ov ? sc ladcm a ? [ ? ] add acc to data ? e ? o ? y with ca ?? y ? note z ? c ? ac ? ov ? sc lsub a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc ? z ? c ? ac ? ov ? sc ? cz lsubm a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc with ? esult in data me ? o ? y ? note z ? c ? ac ? ov ? sc ? cz lsbc a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc with ca ?? y ? z ? c ? ac ? ov ? sc ? cz lsbcm a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc with ca ?? y ? ? esult in data me ? o ? y ? note z ? c ? ac ? ov ? sc ? cz ldaa [ ? ] de ? i ? al adjust acc fo ? addition with ? esult in data me ? o ? y ? note c logic operation land a ? [ ? ] logi ? al and data me ? o ? y to acc ? z lor a ? [ ? ] logi ? al or data me ? o ? y to acc ? z lxor a ? [ ? ] logi ? al xor data me ? o ? y to acc ? z landm a ? [ ? ] logi ? al and acc to data me ? o ? y ? note z lorm a ? [ ? ] logi ? al or acc to data me ? o ? y ? note z lxorm a ? [ ? ] logi ? al xor acc to data me ? o ? y ? note z lcpl [ ? ] co ? ple ? ent data me ? o ? y ? note z lcpla [ ? ] co ? ple ? ent data me ? o ? y with ? esult in acc ? z increment & decrement linca [ ? ] in ?? e ? ent data me ? o ? y with ? esult in acc ? z linc [ ? ] in ?? e ? ent data me ? o ? y ? note z ldeca [ ? ] de ?? e ? ent data me ? o ? y with ? esult in acc ? z ldec [ ? ] de ?? e ? ent data me ? o ? y ? note z rotate lrra [ ? ] rotate data me ? o ? y ? ight with ? esult in acc ? none lrr [ ? ] rotate data me ? o ? y ? ight ? note none lrrca [ ? ] rotate data me ? o ? y ? ight th ? ough ca ?? y with ? esult in acc ? c lrrc [ ? ] rotate data me ? o ? y ? ight th ? ough ca ?? y ? note c lrla [ ? ] rotate data me ? o ? y left with ? esult in acc ? none lrl [ ? ] rotate data me ? o ? y left ? note none lrlca [ ? ] rotate data me ? o ? y left th ? ough ca ?? y with ? esult in acc ? c lrlc [ ? ] rotate data me ? o ? y left th ? ough ca ?? y ? note c data move lmov a ? [ ? ] move data me ? o ? y to acc ? none lmov [ ? ] ? a move acc to data me ? o ? y ? note none bit operation lclr [ ? ].i clea ? ? it of data me ? o ? y ? note none lset [ ? ].i set ? it of data me ? o ? y ? note none
rev. 1.40 174 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 17? de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver mnemonic description cycles flag affected branch lsz [ ? ] skip if data me ? o ? y is ze ? o ? note none lsza [ ? ] skip if data me ? o ? y is ze ? o with data ? ove ? ent to acc ? note none lsnz [ ? ] skip if data me ? o ? y is not ze ? o ? note none lsz [ ? ].i skip if ? it i of data me ? o ? y is ze ? o ? note none lsnz [ ? ].i skip if ? it i of data me ? o ? y is not ze ? o ? note none lsiz [ ? ] skip if in ?? e ? ent data me ? o ? y is ze ? o ? note none lsdz [ ? ] skip if de ?? e ? ent data me ? o ? y is ze ? o ? note none lsiza [ ? ] skip if in ?? e ? ent data me ? o ? y is ze ? o with ? esult in acc ? note none lsdza [ ? ] skip if de ?? e ? ent data me ? o ? y is ze ? o with ? esult in acc ? note none table read ltabrd [ ? ] read ta ? le to tblh and data me ? o ? y 3 note none ltabrdl [ ? ] read ta ? le (last page) to tblh and data me ? o ? y 3 note none litabrd [ ? ] increment table pointer tblp frst and read table to tblh and data memory 3 note none litabrdl [ ? ] increment table pointer tblp frst and read table (last page) to tblh and data me ? o ? y 3 note none miscellaneous lclr [ ? ] clea ? data me ? o ? y ? note none lset [ ? ] set data me ? o ? y ? note none lswap [ ? ] swap ni ?? les of data me ? o ? y ? note none lswapa [ ? ] swap ni ?? les of data me ? o ? y with ? esult in acc ? none 1rwh )ru wkhvh h[whqghg vnls lqvwuxfwlrqv li wkh uhvxow ri wkh frpsdulvrq lqyroyhv d vnls wkhq xs wr irxu ffohv duh uhtxluhg li qr vnls wdnhv sodfh wzr ffohv lv uhtxluhg q h[whqghg lqvwuxfwlrq zklfk fkdqjhv wkh frqwhqwv ri wkh 3&/ uhjlvwhu zloo dovr uhtxluh wkuhh ffohv iru h[hfxwlrq
rev. 1.40 174 de?e??e? 0?? ?01? rev. 1.40 17 ? de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver instruction defnition adc a,[m] gg dwd 0 hpru wr && z lwk &duu hvfulswlr 7kh f rwhwv r i w kh v shflhg dwd 0 hpru ffxpxodwru d g w kh f duu dj d uh d gghg 7kh uh vxow lv v wruhg l w kh ffxpxodwru 2shudwlr && 8 && p & iihfwhg djv 29 = & & 6 & adcm a,[m] gg && wr dwd 0 hpru z lwk &duu hvfulswlr 7kh f rwhwv r i w kh v shflhg dwd 0 hpru ffxpxodwru d g w kh f duu dj d uh d gghg 7kh uh vxow lv v wruhg l w kh vs hflhg dwd 0 hpru 2shudwlr p 8 && p & iihfwhg djv 29 = & & 6 & add a,[m] gg dwd 0 hpru w r && hvfulswlr 7kh f rwhwv r i w kh v shflhg dwd 0 hpru d g w kh ffxpxodwru d uh d gghg 7kh uh vxow lv v wruhg l w kh ffxpxodwru 2shudwlr && 8 && p iihfwhg djv 29 = & & 6 & add a,x gg lp phgldwh gdwd wr hvfulswlr 7kh f rwhwv r i w kh ffxpxodwru d g w kh v shflhg lp phgldwh gdwd d uh d gghg 7kh uh vxow lv v wruhg l w kh ffxpxodwru 2shudwlr 8 iihfwhg dv 29 = 6 addm a,[m] gg && wr dwd 0 hpru hvfulswlr 7kh f rwhwv r i w kh v shflhg dwd 0 hpru d g w kh ffxpxodwru d uh d gghg 7kh uh vxow lv v wruhg l w kh vs hflhg dwd 0 hpru 2shudwlr p 8 && p iihfwhg djv 29 = & & 6 & and a,[m] /rjlfdo 1 dwd 0 hpru w r && hvfulswlr dwd l w kh ffxpxodwru d g w kh v shflhg dwd 0 hpru s huirup d e lwzlvh o rjlfdo 1 rshudwlr 7 kh uh vxow lv v wruhg l w kh ffxpxodwru 2shudwlr && 8 && 1 p iihfwhg djv = and a,x /rlfdo 1 lp phgldwh gdwd wr hvfulswlr dwd l w kh ffxpxodwru d g w kh v shflhg lp phgldwh gdwd s huirup d e lw z lvh o rlfdo 1 rshudwlr 7 kh uh vxow lv v wruhg l w kh ffxpxodwru 2shudwlr 8 1 iihfwhg dv = andm a,[m] /rjlfdo 1 && wr dwd 0 hpru hvfulswlr dwd l w kh v shflhg dwd 0 hpru d g w kh ffxpxodwru s huirup d e lwzlvh o rjlfdo 1 rshudwlr 7 kh uh vxow lv v wruhg l w kh dwd 0 hpru 2shudwlr p 8 && 1 p iihfwhg djv =
rev. 1.40 17 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 177 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver call addr subroutine c all description unconditionally c alls a s ubroutine a t t he s pecifed a ddress. th e p rogram c ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. t he sp ecifed a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. a s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. operation stack p rogram counter + 1 program c ounter a ddr affected f ag(s) none clr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none clr wdt clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re al l c leared. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df cpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z cpla [m] complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z daa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c
rev. 1.40 17? de?e??e? 0?? ?01? rev. 1.40 177 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver dec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z deca [m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z halt enter p ower down m ode description this i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. th e c ontents o f the d ata m emory a nd r egisters a re r etained. th e w dt a nd p rescaler a re c leared. th e p ower down f ag p df i s s et a nd t he w dt t ime-out f ag t o i s c leared. operation to 0 pdf 1 affected f ag(s) to, p df inc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z inca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z jmp addr jump u nconditionally description the c ontents o f t he p rogram c ounter a re re placed w ith t he sp ecifed a ddress. p rogram execution t hen c ontinues f rom t his n ew a ddress. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. operation program counter addr affected f ag(s) none mov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none mov a,x move im mediate data to a cc description the im mediate data s pecifed i s l oaded i nto t he a ccumulator. operation acc x affected f ag(s) none mov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none
rev. 1.40 178 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 179 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver nop no o peration description no o peration i s p erformed. e xecution c ontinues w ith t he n ext i nstruction. operation no operation affected f ag(s) none or a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z or a,x logical or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical o r operation. t he re sult is s tored in t he a ccumulator. operation acc a cc or x affected f ag(s) z orm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z ret return from s ubroutine description the p rogram c ounter is re stored f rom t he s tack. p rogram e xecution c ontinues a t t he re stored a ddress. operation program counter s tack affected f ag(s) none ret a,x return f rom su broutine and l oad im mediate data to a cc description the p rogram c ounter i s r estored f rom t he s tack a nd t he a ccumulator l oaded w ith t he s pecifed immediate data. p rogram e xecution c ontinues a t t he r estored a ddress. operation program counter s tack acc x affected f ag(s) none reti return from i nterrupt description the p rogram c ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he emi b it. e mi i s t he m aster i nterrupt g lobal e nable b it. i f a n i nterrupt w as p ending w hen t he reti instruction is e xecuted, t he p ending in terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. operation program counter s tack emi 1 affected f ag(s) none rl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none
rev. 1.40 178 de?e??e? 0?? ?01? rev. 1.40 179 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver rla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none rlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c rlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c rr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none rra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none rrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c
rev. 1.40 180 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 181 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver rrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c sbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c , s c, c z sbc a, x subtract im mediate data f rom a cc w ith carry description the immediate da ta a nd t he c omplement o f t he c arry f ag a re s ubtracted f rom t he accumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is negative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is p ositive o r z ero, t he c f ag will be se t t o 1 . operation acc a cc - [ m] - c affected f ag(s) ov, z , ac , c , s c, cz sbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c , s c, c z sdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none sdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none
rev. 1.40 180 de?e??e? 0?? ?01? rev. 1.40 181 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver set [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none siz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none siza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none snz [m].i skip i f d ata m emory i s no t 0 description if t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none snz [m] skip i f d ata m emory i s no t 0 description if t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m] 0 affected f ag(s) none sub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c , s c, c z
rev. 1.40 18 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 183 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver subm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c , s c, c z sub a,x subtract im mediate data f rom a cc description the im mediate data s pecifed b y t he c ode i s s ubtracted f rom t he c ontents o f t he a ccumulator. the re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c fag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? x affected f ag(s) ov, z , a c, c , s c, c z swap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none swapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none sz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none sza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none sz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none
rev. 1.40 18? de?e??e? 0?? ?01? rev. 1.40 183 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver tabrd [m] read ta ble ( specifc p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( specifc p age) a ddressed b y t he t able p ointer p air (tblp a nd t bhp) i s mo ved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none itabrd [m] increment ta ble p ointer l ow b yte fr st and r ead ta ble to t blh and d ata m emory description increment ta ble p ointer l ow b yte, t blp, fr st and t hen t he p rogram code addressed b y t he table p ointer ( tbhp and t blp) i s m oved to t he s pecifed d ata m emory and t he hi gh b yte moved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none itabrdl [m] increment t able p ointer l ow by te f rst a nd r ead t able (last p age) t o t blh a nd d ata m emory description increment ta ble p ointer l ow b yte, t blp, fr st and t hen t he l ow b yte of t he p rogram code (last p age) addressed b y t he ta ble p ointer ( tblp) i s m oved to t he s pecifed d ata m emory and the h igh by te mov ed t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none xor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z xorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z xor a,x logical x or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or x affected f ag(s) z
rev. 1.40 184 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 18? de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver extended instruction defnition the extended instructions are used to directly access the data stored in any data memory sections ladc a,[m] gg dwd 0 hpru wr && z lwk &duu hvfulswlr 7kh f rwhwv r i w kh v shflhg dwd 0 hpru ffxpxodwru d g w kh f duu dj d uh d gghg 7kh uh vxow lv v wruhg l w kh ffxpxodwru 2shudwlr && 8 && p & iihfwhg djv 29 = & & 6 & ladcm a,[m] gg && wr dwd 0 hpru z lwk &duu hvfulswlr 7kh f rwhwv r i w kh v shflhg dwd 0 hpru ffxpxodwru d g w kh f duu dj d uh d gghg 7kh uh vxow lv v wruhg l w kh vs hflhg dwd 0 hpru 2shudwlr p 8 && p & iihfwhg djv 29 = & & 6 & ladd a,[m] gg dwd 0 hpru w r && hvfulswlr 7kh f rwhwv r i w kh v shflhg dwd 0 hpru d g w kh ffxpxodwru d uh d gghg 7kh uh vxow lv v wruhg l w kh ffxpxodwru 2shudwlr && 8 && p iihfwhg djv 29 = & & 6 & laddm a,[m] gg && wr dwd 0 hpru hvfulswlr 7kh f rwhwv r i w kh v shflhg dwd 0 hpru d g w kh ffxpxodwru d uh d gghg 7kh uh vxow lv v wruhg l w kh vs hflhg dwd 0 hpru 2shudwlr p 8 && p iihfwhg djv 29 = & & 6 & land a,[m] /rjlfdo 1 dwd 0 hpru w r && hvfulswlr dwd l w kh ffxpxodwru d g w kh v shflhg dwd 0 hpru s huirup d e lwzlvh o rjlfdo 1 rshudwlr 7 kh uh vxow lv v wruhg l w kh ffxpxodwru 2shudwlr && 8 && 1 p iihfwhg djv = landm a,[m] /rjlfdo 1 && wr dwd 0 hpru hvfulswlr dwd l w kh v shflhg dwd 0 hpru d g w kh ffxpxodwru s huirup d e lwzlvh o rjlfdo 1 rshudwlr 7 kh uh vxow lv v wruhg l w kh dwd 0 hpru 2shudwlr p 8 && 1 p iihfwhg djv = lclr [m] &ohdu dwd 0 hpru hvfulswlr (dfk e lw r i w kh v shflhg dwd 0 hpru l v fo hduhg w r 2shudwlr p 8 iihfwhg djv 1rh lclr [m].i ohdu el w r i dwd 0 hpru hvfulswlr lw l r i w kh v shflhg dwd 0 hpru l v fo hduhg w r 2shudwlr pl 8 iihfwhg dv 1rh
rev. 1.40 184 de?e??e? 0?? ?01? rev. 1.40 18 ? de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver lcpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z lcpla [m] complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z ldaa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c ldec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z ldeca [m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z linc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z linca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z
rev. 1.40 18 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 187 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver lmov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none lmov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none lor a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z lorm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z lrl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none lrla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none lrlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c lrlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c
rev. 1.40 18? de?e??e? 0?? ?01? rev. 1.40 187 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver lrr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none lrra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none lrrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c lrrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c lsbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c , s c, c z lsbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c , s c, c z
rev. 1.40 188 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 189 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver lsdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none lsdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none lset [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none lset [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none lsiz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none lsiza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none lsnz [m].i skip i f d ata m emory i s no t 0 description if t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none
rev. 1.40 188 de?e??e? 0?? ?01? rev. 1.40 189 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver lsnz [m] skip i f d ata m emory i s no t 0 description if t he c ontent o f t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s this re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a two c ycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m] 0 affected f ag(s) none lsub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c , s c, c z lsubm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c , s c, c z lswap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none lswapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none lsz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none lsza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none
rev. 1.40 190 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 191 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver lsz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none ltabrd [m] read ta ble ( current p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( current p age) a ddressed b y t he t able p ointer ( tblp) is moved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none ltabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none litabrd [m] increment ta ble p ointer l ow b yte fr st and r ead ta ble to t blh and d ata m emory description increment ta ble p ointer l ow b yte, t blp, fr st and t hen t he p rogram code addressed b y t he table p ointer ( tbhp and t blp) i s m oved to t he s pecifed d ata m emory and t he hi gh b yte moved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none litabrdl [m] increment t able p ointer l ow by te f rst a nd r ead t able (last p age) t o t blh a nd d ata m emory description increment ta ble p ointer l ow b yte, t blp, fr st and t hen t he l ow b yte of t he p rogram code (last p age) addressed b y t he ta ble p ointer ( tblp) i s m oved to t he s pecifed d ata m emory and the h igh by te mov ed t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none lxor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z lxorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z
rev. 1.40 190 de?e??e? 0?? ?01? rev. 1.40 191 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver package information note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/carton information . additional supplementary information with regard to pa ckaging is listed below. click on the relevant section to be transferred to the relevant website page. ? package information (include outline dimensions, product t ape and reel specifcations) ? the operation instruction of packing materials ? carton information
rev. 1.40 19 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 193 de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver 20-pin sop (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.40 ? bsc b 0. ? 9 ? bsc c 0.01 ? 0.0 ? 0 c 0. ? 04 bsc d 0.104 e 0.0 ? 0 bsc f 0.004 0.01 ? g 0.01 ? 0.0 ? 0 h 0.008 0.013 0 8 symbol dimensions in mm min. nom. max. a 10.30 bsc b 7. ? 0 bsc c 0.31 0. ? 1 c 1 ? .80 bsc d ? . ?? e 1. ? 7 bsc f 0.10 0.30 g 0.40 1. ? 7 h 0. ? 0 0.33 0 8
rev. 1.40 19? de?e??e? 0?? ?01? rev. 1.40 193 de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver 24-pin sop(300mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.40 ? bsc b 0. ? 9 ? bsc c 0.01 ? 0.0 ? 0 c 0. ? 0 ? bsc d 0.104 e 0.0 ? 0 bsc f 0.004 0.01 ? g 0.01 ? 0.0 ? 0 h 0.008 0.013 0 8 symbol dimensions in mm min. nom. max. a 10.30 bsc b 7. ? bsc c 0.31 0. ? 1 c 1 ? .4 bsc d ? . ?? e 1. ? 7 bsc f 0.10 0.30 g 0.40 1. ? 7 h 0. ? 0 0.33 0 8
rev. 1.40 194 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.40 19? de?e??e? 0?? ?01? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver 28 -pin sop(300mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.40 ? bsc b 0. ? 9 ? bsc c 0.01 ? 0.0 ? 0 c 0.70 ? bsc d 0.104 e 0.0 ? 0 bsc f 0.004 0.01 ? g 0.01 ? 0.0 ? 0 h 0.008 0.013 0 8 symbol dimensions in mm min. nom. max. a 10.30 bsc b 7. ? bsc c 0.31 0. ? 1 c 17.9 bsc d ? . ?? e 1. ? 7 bsc f 0.10 0.30 g 0.40 1. ? 7 h 0. ? 0 0.33 0 8
rev. 1.40 194 de?e??e? 0?? ?01? rev. 1.40 19 ? de ? e ?? e ? 0 ?? ? 01 ? bs86b12a-3/bs86c16 a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver bs86b12a-3/bs86c1 6a-3/BS86D20A-3 touch a/d flash mcu with led/lcd driver copy ? ight ? ? 01 ? ? y holtek semiconductor inc. the info ?? ation appea ? ing in this data sheet is ? elieved to ? e a ?? u ? ate at the ti ? e of pu ? li ? ation. howeve ?? holtek assu ? es no ? esponsi ? ility a ? ising f ? o ? the use of the specifcations described. the applications mentioned herein are used solely fo ? the pu ? pose of illust ? ation and holtek ? akes no wa ?? anty o ? ? ep ? esentation that su ? h appli ? ations will ? e suita ? le without fu ? the ? ? odifi ? ation ? no ? ? e ? o ?? ends the use of its p ? odu ? ts fo ? appli ? ation that ? ay p ? esent a ? isk to hu ? an life due to ? alfun ? tion o ? othe ? wise. holtek's p ? odu ? ts a ? e not autho ? ized fo ? use as ?? iti ? al ? o ? ponents in life suppo ? t devi ? es o ? syste ? s. holtek ? ese ? ves the ? ight to alte ? its products without prior notifcation. for the most up-to-date information, please visit ou ? we ? site at http://www.holtek. ? o ? .tw.

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