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s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 1 ver. g sm59 r 02g1 0 9 /20 1 5 description .......................................................................................................................................................................... 3 features .............................................................................................................................................................................. 3 pin configuration ................................................................................................................................................................ 4 block diagram ................................................................................................................................................................... 10 pin description .................................................................................................................................................................. 11 special function register (sfr) ...................................................................................................................................... 13 function description ......................................................................................................................................................... 16 1. general features ..................................................................................................................................................... 16 1.1. embedded flash ......................................................................................................................................... 16 1.2. io pads ....................................................................................................................................................... 16 1.3. 2t/1t selection ........................................................................................................................................... 16 1.4. reset ........................................................................................................................................................ 17 1.4.1. hardware reset function ............................................................................................................. 17 1.4.2. software reset function .............................................................................................................. 17 1.4.3. time access key register (takey) ................................................................................................ 17 1.4.4. software reset register (swres) ................................................................................................. 17 1.4.5. reset status flag(rsts) ............................................................................................................... 18 1.4.6. example of software reset ............................................................................................................. 18 1.5. clocks ......................................................................................................................................................... 18 2. instruction set .......................................................................................................................................................... 19 3. memory structure ..................................................................................................................................................... 23 3.1. program memory ........................................................................................................................................ 23 3.2. data memory ............................................................................................................................................... 24 3.2.1. data memory - lower 128 byte (00h to 7fh) .................................................................................. 24 3.2.2. data memory - higher 128 byte (80h to ffh) ................................................................................ 24 4. cpu engine ............................................................................................................................................................. 25 4.1. accumulator ................................................................................................................................................ 25 4.2. b register ................................................................................................................................................... 25 4.3. program status word .................................................................................................................................. 26 4.4. stack pointer ............................................................................................................................................... 26 4.5. data pointer ................................................................................................................................................ 26 4.6. data pointer 1 ............................................................................................................................................. 27 4.7. interface control register ............................................................................................................................. 27 5. gpio ........................................................................................................................................................................ 28 6. timer 0 and timer 1 ................................................................................................................................................. 30 6.1. timer/counter mode control register (tmod) ............................................................................................. 30 6.2. timer/counter con trol register (tcon) ....................................................................................................... 31 6.3. peripheral frequency control register(pfcon) .......................................................................................... 31 6.4. mode 0 (13 - bit counter/timer) .................................................................................................................... 32 6.5. mode 1 (16 - bit counter/timer) .................................................................................................................... 32 6.6. mode 2 (8 - bit auto - reload counter/timer) .................................................................................................. 33 6.7. mode 3 (timer 0 acts as two independent 8 bit timers / counters) ........................................................... 33 7. timer 2 and capture/compare unit ......................................................................................................................... 34 7.1. t imer 2 function ........................................................................................................................................... 36 7.1.1. timer mode .................................................................................................................................... 36 7.1.2. event counter mode ....................................................................................................................... 36 7.1.3. gated timer mode .......................................................................................................................... 36 7.1.4. reload of timer 2 ........................................................................................................................... 36 7.2. compare function ........................................................................................................................................ 36 7.2.1. compare mode 0 ........................................................................................................................... 37 7.2.2. compare mode 1 ........................................................................................................................... 37 7.3. capture function .......................................................................................................................................... 38 7.3.1. capture mode 0 ............................................................................................................................. 38 7.3.2. capture mode 1 ............................................................................................................................. 38 8. serial interface 0 ...................................................................................................................................................... 39 8.1. serial interface 0 ......................................................................................................................................... 40 8.1.1. mode 0 ........................................................................................................................................... 40
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 2 ver. g sm59 r 02g1 0 9 /20 1 5 8.1.2. mode 1 ........................................................................................................................................... 41 8.1.3. mode 2 ........................................................................................................................................... 41 8.1.4. mode 3 ........................................................................................................................................... 41 8.2. multiprocessor communication of serial interface 0 ................................................................................... 42 8.3. baud rate generator .................................................................................................................................... 42 8.3.1. serial interface 0 modes 1 and 3 ................................................................................................... 42 9. watchdog timer ........................................................................................................................................................ 43 10. interrupt ........................................................................................................................................................... 46 11. power management unit ................................................................................................................................. 50 11.1. idle mode .................................................................................................................................................... 50 11.2. stop mode ................................................................................................................................................... 50 12. low voltage control ........................................................................................................................................ 51 13. in - system programming (internal isp) ........................................................................................................... 52 13.1. isp service program ............................................................................................................................... 52 13.2. lock bit (n) ............................................................................................................................................. 52 13.3. program the isp service program ......................................................................................................... 52 13.4. initiate isp service program ................................................................................................................... 53 13 .5. isp register ? takey, ifcon, ispfah, ispfal, ispfd and ispfc .................................................... 53 operating conditions ........................................................................................................................................................ 56 dc characteristics ............................................................................................................................................................ 56
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 3 ver. g sm59 r 02g1 0 9 /20 1 5 product list SM59R02G1w 28k p, SM59R02G1w 28s p, sm59r 02g1 w40pp , SM59R02G1w44jp, SM59R02G1w44qp, SM59R02G1w44 u p, SM59R02G1w48vp description the SM59R02G1 is a 1t (one machine cycle per clock) single - chip 8 - bit microcontroller. it has 8 k - byte embedded flash for program, and executes all asm51 instructions fully compatible with mcs - 51. SM59R02G1 contains 256 b on - chip ram, more than 4 2 gpios ( plcc 44, qfp 44 and lqfp 48) , various serial interfaces and many peripheral functions as described b elow. it can be programmed via writer s . its on - chip ice is convenient for users in verification during development stage. the high performance of SM59R02G1 can achieve complicated manipulation within short time. about one third of the instructions are pur e 1t, and the average speed is 8 times of traditional 8051, the fastest one among all the 1t 51 - series.its excellent emi and esd characteristics are advantageous for many different applications. ordering information SM59R02G1 ihhkl yww i: process identifie r { w = 2.7v ~ 5.5v} hh: pin count k: package type postfix {as table below } l:pb free identifier {no text is non - pb free ?p? is pb free} y : y ear code ww : week code (01 - 52) postfix package pin / pad configuration k 28l pdip page 4 s 28l sop page 5 p 40l pdip page 6 j 44l plcc page 7 q 44l p qfp page 8 v 48l lqfp page 9 features ? operating voltage: 2.7v ~ 5.5 v ? high speed architecture of 1 clock/machine cycle (1t), runs up to 25mhz ? 1t/2t can be switched on the fly ? instruction - set compatible with mcs - 5 1 ? 8 k bytes on - chip program memory. ? external ram addresses up to 64k bytes. standard 12t interface for external ram access. ? 256 bytes ram as standard 8052 ? dual 16 - bit data pointers (dptr0 & dptr1) ? one serial peripheral interfaces in full duplex mode (uart0) , additional baud rate generator for serial 0. ? three 16 - bit timers/counters. (timer 0 , 1, 2) ? 3 8 gpios(pdip 40) , 4 2 gpios(plcc 44/ p qfp 44 /lqfp 48) , gpios can select four type(quasi - bidirectional , push - pull , open drain , input - only) , default is quasi - bidirec tional(pull - up) ? external interrupt 0,1 with four priority level s ? programmable watchdog timer (wdt) ? 4 - channel 16 - bit compare /capture /load functions ? 22.1184mh z internal rc oscillator, with programmable clock divider ? configurable oscillator pin ? isp/iap func tions. ? isp service program space configurable in n*256 byte (n=0 to 4 ) size. ? eeprom function ? ale output select. ? lvr (lvr deglitch 500ns) ? enhanced user code protection ? power management unit for idle and power down modes
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 4 ver. g sm59 r 02g1 0 9 /20 1 5 pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 cc 0 / t 2 / p 1 . 0 cc 1 / t 2 ex / p 1 . 1 rxd 0 / p 1 . 2 vdd cc 2 / txd 0 / p 1 . 3 p 4 . 7 / reset ( default ) rxd 0 / p 3 . 0 txd 0 / p 3 . 1 int 0 / p 3 . 2 int 1 / p 3 . 3 t 0 / p 3 . 4 t 1 / p 3 . 5 xtal 2 / p 5 . 4 osc / xtal 1 / p 5 . 5 vss p 0 . 0 / ad 0 p 0 . 1 / ad 1 p 0 . 2 / ad 2 p 0 . 3 / ad 3 p 0 . 4 / ad 4 p 0 . 5 / ad 5 p 0 . 6 / ad 6 p 0 . 7 / ad 7 p 2 . 4 / a 12 p 2 . 3 / a 11 / cc 3 p 2 . 2 / a 10 / cc 2 p 2 . 1 / a 9 / cc 1 p 2 . 0 / a 8 / cc 0 syncmos sm 59 r 02 g 1 ihhkp yww ( 28 l pdip top view ) notes the pin reset/p4.7 factory default is reset, user must keep this pin at low during power - up. user can configure it to gpio (p4.7) by a flash programmer.
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 5 ver. g sm59 r 02g1 0 9 /20 1 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 cc 0 / t 2 / p 1 . 0 cc 1 / t 2 ex / p 1 . 1 rxd 0 / p 1 . 2 dd cc 2 / txd 0 / p 1 . 3 p 4 . 7 / reset ( deault ) rxd 0 / p 3 . 0 txd 0 / p 3 . 1 int 0 / p 3 . 2 int 1 / p 3 . 3 t 0 / p 3 . 4 t 1 / p 3 . 5 xtal 2 / p 5 . 4 sc / xtal 1 / p 5 . 5 ss p 0 . 0 / ad 0 p 0 . 1 / ad 1 p 0 . 2 / ad 2 p 0 . 3 / ad 3 p 0 . 4 / ad 4 p 0 . 5 / ad 5 p 0 . 6 / ad 6 p 0 . 7 / ad 7 p 2 . 4 / a 12 p 2 . 3 / a 11 / cc 3 p 2 . 2 / a 10 / cc 2 p 2 . 1 / a 9 / cc 1 p 2 . 0 / a 8 / cc 0 syncmos sm 59 r 02 g 1 ihhsp yww ( 28 l sop top view ) notes the pin reset/p4.7 factory default is reset, user must ke ep this pin at low during power - up. user can configure it to gpio (p4.7) by a flash programmer.
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 6 ver. g sm59 r 02g1 0 9 /20 1 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 cc0/t2/p1.0 cc1/t2ex/p1 .1 rxd0/p1.2 dd cc2/txd0/p1.3 cc3/p1.4 p1.5 p1.6 p1.7 p4.7/reset(deault ) rxd0/p3.0 txd0/p3.1 int0/p3.2 int1/p3.3 t0/p3.4 t1/p3.5 wr/p3.6 rd/p3.7 xtal2/p5.4 sc/xtal1/p5.5 ss p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 p4.6 ale/p4.5 p4.4 p2.7/a15 p2.6/a14 p2.5/a13 p2.4/a12 p2.3/a11/cc3 p2.2/a10/cc2 p2.1/a9/cc1 p2.0/a8/cc0 syncmos SM59R02G1ihhpp yww (40l pdip top view) notes 1. the pin reset/p4.7 factory default is reset, user must keep this pin at low during power - up. user can configure it to gpi o (p4.7) by a flash programmer. 2. to avoid accidentally entering isp - mode(refer to section 13.4), care must be taken not asserting pulse signal at p3.0 during power - up while p2.6 , p2.7 , p4.3 are set to high.
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 7 ver. g sm59 r 02g1 0 9 /20 1 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 21 39 38 37 36 35 34 33 32 31 30 29 40 41 42 43 44 p1.0/t2/cc0 p1.1/t2ex/cc1 p1.2/rxd0 p1.3//cc2/txd0 p1.4/cc3 p1.5 p1.6 p1.7 p4.7/reset(default ) rxd0/p3.0 txd0/p3.1 int0/p3.2 int1/p3.3 t0/p3.4 t1/p3.5 cc3/p4.3 wr/p3.6 rd/p3.7 xtal2/p5.4 xtal1/osc/p5.5 vss cc0/p4.0 a12/p2.4 cc3/a11/p2.3 cc2/a10/p2.2 cc1/kbi1/a9/p2.1 cc0/a8/p2.0 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 p4.6 ale/p4.5 p4.4 p2.7/a15 p2.6/a14 p2.5/a13 p4.1 vdd p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 syncmos SM59R02G1 ihhjp yww (44l plcc top view ) p4.2/cc2
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 8 ver. g sm59 r 02g1 0 9 /20 1 5 cc 0 /t2/p1.0 cc1/t2ex/p1.1 rxd0/p1.2 txd0/cc2/p1.3 cc3/p1.4 cc2/p4.2 p1.5 p1.6 p1.7 p4.7/reset(default ) rxd0/p3.0 txd0/p3.1 int0/p3.2 int1/p3.3 t0/p3.4 t1/p3.5 cc3/p4.3 p3.6/wr p3.7/rd xtal2/p5.4 osc/xtal1/p5.5 vss p4.0/cc0 p2.4/a12 p2.3/a11/cc3 p2.2/a10/cc2 p2.1/a9/cc1 p2.0/a8/cc0 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 p4.6 ale/p4.5 p4.4 p2.7/a15 p2.6/a14 p2.5/a13 p4.1/cc1 vdd ad0/p0.0 ad1/p0.1 ad2/p0.2 ad3/p0.3 1 2 3 4 5 6 7 8 9 10 11 13 14 15 12 22 21 20 19 18 17 16 24 23 33 32 31 30 29 28 27 26 25 43 44 34 35 36 38 39 40 41 42 37 syncmos SM59R02G1 ihhq(u)p yww (44l pqfp/lqfp top view)
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 9 ver. g sm59 r 02g1 0 9 /20 1 5 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 13 14 15 23 22 21 20 19 18 17 16 36 35 34 33 32 31 30 29 28 27 26 38 39 40 41 42 cc 0 / t 2 / p 1 . 0 cc 1 / t 2 ex / p 1 . 1 rxd 0 / p 1 . 2 txd 0 / cc 2 / p 1 . 3 cc 3 / p 1 . 4 cc 2 / p 4 . 2 p 1 . 5 p 1 . 6 p 1 . 7 p 4 . 7 / reset ( default ) rxd 0 / p 3 . 0 txd 0 / p 3 . 1 int 0 / p 3 . 2 int 1 / p 3 . 3 t 0 / p 3 . 4 t 1 / p 3 . 5 cc 3 / p 4 . 3 p 3 . 6 / w r p 3 . 7 / rd xtal 2 / p 5 . 4 osc / xtal 1 / p 5 . 5 vss p 4 . 0 / cc 0 p 2 . 4 / a 12 p 2 . 3 / a 11 / cc 3 p 2 . 2 / a 10 / cc 2 p 2 . 1 / a 9 / cc 1 p 2 . 0 / a 8 / cc 0 p 0 . 4 / ad 4 p 0 . 5 / ad 5 p 0 . 6 / ad 6 p 0 . 7 / ad 7 p 4 . 6 ale / p 4 . 5 p 4 . 4 p 2 . 7 / a 15 p 2 . 6 / a 14 p 2 . 5 / a 13 p 4 . 1 / cc 1 vdd ad 0 / p 0 . 0 ad 1 / p 0 . 1 ad 2 / p 0 . 2 ad 3 / p 0 . 3 37 25 24 12 n . c . n . c . n . c . n . c . syncmos sm 59 r 02 g 1 ihh v p yww ( 48 l lqfp top view )
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 10 ver. g sm59 r 02g1 0 9 /20 1 5 block diagram uart 0 flash 8 kbytes sram 256 bytes interrupt timer 0 / 1 timer 2 & ccu watchdog port 0 port 1 port 2 port 3 port 0 port 1 port 2 port 3 t 0 t 1 cc 0 ~ cc 3 t 2 t 2 ex rxd 0 txd 0 xtal 1 xtal 2 ale wr rd port 4 port 4 cpu max 810 reset port 5 port 5
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 11 ver. g sm59 r 02g1 0 9 /20 1 5 pin description 28l 40l pdip 44l plcc 44l qfp 48l lqfp symbol i/o description 1 39 42 p4.2/cc2 i/o bit 2 of port 4 & timer 2 compare/capture channel 2 1 1 2 4 0 43 p1.0/t2/cc0 i/o bit 0 of port 1 & timer 2 external input clock & timer 2 compare/capture channel 0 2 2 3 41 44 p1.1/t2ex/cc1 i/o bit 1 of port 1 & timer 2 capture trigger & timer 2 compare/capture channel 1 3 3 4 42 45 p1.2/rxd0 i/o bit 2 of port 1 & serial interface channel 0 receive data 4 4 5 43 46 p1.3/txd0/cc2 i/o bit 3 of port 1 & serial interface channel 0 transmit data & timer 2 compare/capture channel 2 5 6 44 47 p1.4/cc3 i/o bit 4 of port 1 & timer 2 compare/capture channel 3 48 nc 1 nc 6 7 1 2 p1.5 i/o bit 5 of port 1 7 8 2 3 p1.6 i/o bit 6 of port 1 8 9 3 4 p1.7 i/o bit 7 of port 1 5 9 10 4 5 reset (default) /p 4.7 i/o reset pin (default) & bit 7 of port 4 6 10 11 5 6 p3.0/rxd0 i/o bit 0 of port 3 & serial interface channel 0 receive/transmit data 12 6 7 p4.3/cc3 i/o bit 3 of port 4 & timer 2 compare/capture channel 3 7 11 13 7 8 p3.1/txd0 i/o bit 1 of port 3 & serial interface channel 0 transmit data or receive clock in mode 0 8 12 14 8 9 p3.2/#int0 i/o bit 2 of port 3 & external interrupt 0 9 13 15 9 10 p3.3/#int1 i/o bit 3 of port 3 & external interrupt 1 10 14 16 10 11 p3.4/t0 i/o bit 4 of port 3 & timer 0 external input 11 15 17 11 12 p3.5/t1 i/o bit 5 of port 3 & timer 1 external input 16 18 12 13 p3. 6/#wr i/o bit 6 of port 3 & external memory write signal 17 19 13 14 p3.7/#rd i/o bit 7 of port 3 & external memory read signal 12 18 20 14 15 xtal 2/p5.4 o crystal output & bit4 of port 5 13 19 21 15 16 xtal1/osc/p5.5 i crystal input& oscillator input& bit5 of port 5 14 20 22 16 17 vss i ground line 23 17 18 p4.0/cc0 i/o bit 0 of port 4 & timer 2 compare/capture channel 0 15 21 24 18 19 p2.0 /a8/cc0 i/o bit 0 of port 2 & bit 8 of external memory address& timer 2 compare/capture channel 0 16 22 25 19 20 p2.1 /a9/cc1 i/o bit 1 of port 2 & bit 9 of external memory address& timer 2 compare/capture channel 1 17 23 26 20 21 p2.2 /a10/cc2 i/o bit 2 of port 2 & bit 10 of external memory address & timer 2 compare/capture channel 2 18 24 27 21 22 p2.3 /a1 1/cc3 i/o bit 3 of port 2 & bit 11 of external memory address & timer 2 compare/capture channel 3 19 25 28 22 23 p2.4 /a12 i/o bit 4 of port 2 & bit 12 of external memory address 24 nc 25 nc 26 29 23 26 p2.5 /a13 i/o bit 5 of port 2 & bit 13 of external memory address 27 30 24 27 p2.6 /a14 i/o bit 6 of port 2 & bit 14 of external memory address 28 31 25 28 p2.7 /a15 i/o bit 7 of port 2 & bit 15 of external memory address 29 32 26 29 p4.4 i/o bit 4 of port 4 30 33 27 30 ale/p4.5 i/o address latch enable & bit 5 of port 4 34 28 31 p4.1cc1 i/o bit 1 of port 4 & timer 2 compare/capture channel 1 31 35 29 32 p4.6 i/o bit 6 of port 4 20 32 36 30 33 p0.7/ad7 i/o bit 7 of port 0 & bit 7 of external memory address/ data
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 12 ver. g sm59 r 02g1 0 9 /20 1 5 28l 40l p dip 44l plcc 44l qfp 48l lqfp symbol i/o description 21 33 37 31 34 p0.6/ad6 i/o bit 6 of port 0 & bit 6 of external memory address/ data 22 34 38 32 35 p0.5/ad5 i/o bit 5 of port 0 & bit 5 of external memory address/ data 23 35 39 33 36 p0.4/ad4 i/o b it 4 of port 0 & bit 4 of external memory address/ data 24 36 40 34 37 p0.3/ad3 i/o bit 3 of port 0 & bit 3 of external memory address/ data 25 37 41 35 38 p0.2/ad2 i/o bit 2 of port 0 & bit 2 of external memory address/ data 26 38 42 36 39 p0.1/ad1 i/ o bit 1 of port 0 & bit 1 of external memory address/ data 27 39 43 37 40 p0.0/ad0 i/o bit 0 of port 0 & bit 0 of external memory address/ data 28 40 44 38 41 vdd i power supply
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 13 ver. g sm59 r 02g1 0 9 /20 1 5 special function register (sfr) a map of the special function registers is show n as below: hex \ bin x000 x001 x010 x011 x100 x101 x110 x111 bin/hex f8 - - ff f0 b - takey f7 e8 p4 - - - - - - - ef e0 acc ispfah ispfal ispfd ispfc - lvc swres e7 d8 p5 pfcon p3m0 p3m1 p4m0 p4m1 p5m0 p5m1 df d0 psw ccen2 p0m0 p0 m1 p1m0 p1m1 p2m0 p2m1 d7 c8 t2con cccon crcl crch tl2 th2 - - cf c0 ircon ccen ccl1 cch1 ccl2 cch2 ccl3 cch3 c7 b8 ien1 ip1 s0relh - - - - - bf b0 p3 - - - - - wdtc wdtk b7 a8 ien0 ip0 s0rell - - - - - af a0 p2 rsts - - - - - - a7 98 s0con s0buf ie n2 - - - - - 9f 90 p1 aux aux2 - - - - ircon2 97 88 tcon tmod tl0 tl1 th0 th1 ifcon 8f 80 p0 sp dpl dph dpl1 dph1 - pcon 87 hex \ bin x000 x001 x010 x011 x100 x101 x110 x111 bin/hex note: special function registers reset values and description for sm5 9r02g1 register location reset value description p0 80h ffh port 0 sp 81h 07h stack pointer dpl 82h 00h data pointer 0 low byte dph 83h 00h data pointer 0 high byte dpl1 84h 00h data pointer 1 low byte dph1 85h 00h data pointer 1 high byte pcon 87h 4 0h power control tcon 88h 00h timer/counter control tmod 89h 00h timer mode control tl0 8ah 00h timer 0, low byte tl1 8bh 00h timer 1, low byte th0 8ch 00h timer 0, high byte th1 8dh 00h timer 1, high byte ifcon 8fh 00h interface control register p1 90h ffh port 1 aux 91h 00h auxiliary register
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 14 ver. g sm59 r 02g1 0 9 /20 1 5 register location reset value description aux2 92h 00h auxiliary 2 register ircon2 97h 00h interrupt request control register s0con 98h 00h serial port 0, control register s0buf 99h 00h serial port 0, data buffer ien2 9ah 00h interrupt enable register 2 p2 a0h ffh port 2 rsts a1h 00h reset status flag register ien0 a8h 00h interrupt enable register 0 ip0 a9h 00h interrupt priority register 0 s0rell aah 00h serial port 0, reload register, low byte p3 b0h ffh port 3 wdtc b6h 04h watchdog timer control register wdtk b7h 00h watchdog timer refresh key. ien1 b8h 00h interrupt enable register 1 ip1 b9h 00h interrupt priority register 1 s0relh bah 00h serial port 0, reload register, high byte irco n c0h 00h interrupt request control register ccen c1h 00h compare/capture enable register ccl1 c2h 00h compare/capture register 1, low byte cch1 c3h 00h compare/capture register 1, high byte ccl2 c4h 00h compare/capture register 2, low byte cch2 c5h 0 0h compare/capture register 2, high byte ccl3 c6h 00h compare/capture register 3, low byte cch3 c7h 00h compare/capture register 3, high byte t2con c8h 00h timer 2 control cccon c9h 00h compare/capture control crcl cah 00h compare/reload/capture regis ter, low byte crch cbh 00h compare/reload/capture register, high byte tl2 cch 00h timer 2, low byte th2 cdh 00h timer 2, high byte psw d0h 00h program status word ccen2 d1h 00h compare/capture enable 2 register p0m0 d2h 00h port 0 output mode 0 p0m1 d3h 00h port 0 output mode 1 p1m0 d4h 00h port 1 output mode 0 p1m1 d5h 00h port 1 output mode 1 p2m0 d6h 00h port 2 output mode 0 p2m1 d7h 00h port 2 output mode 1 p5 d8h ffh port 5 pfcon d9h 00h peripheral frequency control register p3m0 dah 00h port 3 output mode 0 p3m1 dbh 00h port 3 output mode 1
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 15 ver. g sm59 r 02g1 0 9 /20 1 5 register location reset value description p4m0 dch 00h port 4 output mode 0 p4m1 ddh 00h port 4 output mode 1 p5m0 deh 00h port 5 output mode 0 p5m1 dfh 00h port 5 output mode 1 acc e0h 00h accu mulator ispfah e1h ffh isp flash address - high register ispfal e2h ffh isp flash address - low register ispfd e3h ffh isp flash data register ispfc e4h 00h isp flash control register lvc e6h 20h low voltage control register swres e7h 00h software reset register p4 e8h ffh port 4 b f0h 00h b register takey f7h 00h time access key register
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 16 ver. g sm59 r 02g1 0 9 /20 1 5 function description 1. general features SM59R02G1 is an 8 - bit micro - controller all of its functions and the detailed meanings of sfr will be given in the following sections . 1.1. embedded flash the program can be loaded into the embedded 8 kb flash memory via its writer or in - system programm ing (isp) . 1.2. io pads the SM59R02G1 has six i/o ports: port 0, port 1, port 2, port 3, port 4, and port 5. ports 0, 1, 2, 3, 4 are 8 - bit ports and port 5 is a 2 - bit port (only bit 4 and bit 5) . these are: quasi - bidirectional (standard 8051 port outputs), push - pull, open drain, and input - only. as description in section 5 . the xtal2 and xtal1 can define as p5.4 and p5.5 by writer or isp . w hen user use external osc as system clock and input into xtal1 , only xtal2 can be defined as p5.4 . all the pads for p0 ~ p5 are with slew rate to reduce emi. the other way to reduce emi is to disable the ale output if unused. this is selected by its sfr. the io pads can withstand 4kv esd in human body mode guaranteeing the SM59R02G1 ?s quality in hig h electro - static environments. 1.3. 2t/1t selection the conventional 52 - series mcus are 12t, i.e., 12 oscillator clocks per machine cycle. SM59R02G1 is a 2 t or 1t mcu, i.e., its machine cycle is two - clock or one - clock. in the other words, it can execute one instruction within two clocks or only one clock. the difference between 2t mode and 1t mode are given in the example in fig. 1 - 1 . fig . 1 - 1 (a): the waveform of internal instruction signal in 2t mode fig . 1 - 1 (b): the waveform of internal instruction signal in 1t mode the default is in 2t mode, and it can be changed to 1t mode if ifcon [7] (at address 8fh) is set to high any time. not every instruc tion can be executed with one machine cycle. the exact machine cycle number for all the instructions are given in the next section.
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 17 ver. g sm59 r 02g1 0 9 /20 1 5 1.4. reset 1.4.1. hardware reset function SM59R02G1 provides internal reset circuit inside the internal reset time can set by write r or isp internal reset time 25ms (default) 200ms 100ms 50ms 16ms 8ms 4ms 1.4.2. software reset function SM59R02G1 provides one software reset mechanism to reset whole chip. to perform a software reset, the firmware must write three specific values 5 5h, aah and 5ah sequentially to the takey register to enable the software reset register (swres) write attribute. after swres register obtain the write authority, the firmware can write ffh to the swres register. the hardware will decode a reset signal tha t ?or? with the other hardware reset. the swres register is self - reset at the end of the software reset procedure. mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset software reset function takey time access key register f 7h takey [7:0] 00h swres software reset register e7h swres [7:0] 00h rsts reset status flag register a1h - - - pdrf wdtf swrf lvrf porf 00h 1.4.3. time access key register (takey) mnemonic: takey address: f7h 7 6 5 4 3 2 1 0 reset takey [7:0] 00h softwar e reset register (swres) is read - only by default; software must write three specific values 55h, aah and 5ah sequentially to the takey register to enable the swres register write attribute. that is: mov takey, #55h mov takey, #aah mov takey, #5ah 1.4.4. software reset register (swres) mnemonic: swres address: e7h 7 6 5 4 3 2 1 0 reset swres [7:0] 00h swres [7:0]: software reset register bit. these 8 - bit is self - reset at the end of the reset procedure. swres [7:0] = ffh, software reset. swres [7:0] = 00h ~ fe h, mcu no action.
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 18 ver. g sm59 r 02g1 0 9 /20 1 5 1.4.5. reset status flag(rsts) mnemonic: rsts address: a1h 7 6 5 4 3 2 1 0 reset - - - pdrf wdtf swrf lvrf porf 00h pdrf: pad reset flag. when mcu is reset by reset pad, pdrf flag will be set to one by hardware. this flag clear by softwar e. wdtf: watchdog timer reset flag. when mcu is reset by watchdog, wdtf flag will be set to one by hardware. this flag clear by software. swrf: software reset flag. when mcu is reset by software, swrf flag will be set to one by hardware. this flag clear by software. lvrf: low voltage reset flag. when mcu is reset by lvr, lvrf flag will be set to one by hardware. this flag clear by software. porf: power on reset flag. when mcu is reset by por, porf flag will be set to one by hardware. this flag clear by software. 1.4.6. example of software reset mov takey, #55h mov takey, #aah mov takey, #5ah ; enable swres write attribute mov swres, #ffh ; software reset mcu 1.5. clocks the default clock is the 22.1184mhz internal osc . this clock is used during the initializati on stage. the major work of the initialization stage is to determine the clock so urce used in normal operation. the internal clock sources are from the internal osc with difference frequency division as given in table 1 - 1 , the clock source can set by wr iter table 1 - 1: selection of clock source clock source external crystal ex ternal osc into xtal1 22.1184 mhz from internal osc (default) 11.0592 mhz from internal osc 5.5296 mhz from internal osc 2.7648 mhz from internal osc 1.3824 mhz from internal os c t he internal osc have 2 variance at room temperature .
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 19 ver. g sm59 r 02g1 0 9 /20 1 5 2. instruction set all SM59R02G1 instructions are binary code compatible and perform the same functions as they do with the industry standard 8051. the following tables give a summary of the instr uction set cycles of the SM59R02G1 microcontroller core. table 2 - 1: arithmetic operations mnemonic description code bytes cycles add a,rn add register to accumulator 28 - 2f 1 1 add a,direct add direct byte to accumulator 25 2 2 add a,@ri add indirect ra m to accumulator 26- 27 1 2 add a,#data add immediate data to accumulator 24 2 2 addc a,rn add register to accumulator with carry flag 38 - 3f 1 1 addc a,direct add direct byte to a with carry flag 35 2 2 addc a,@ri add indirect ram to a with carry flag 3 6 - 37 1 2 addc a,#data add immediate data to a with carry flag 34 2 2 subb a,rn subtract register from a with borrow 98 - 9f 1 1 subb a,direct subtract direct byte from a with borrow 95 2 2 subb a,@ri subtract indirect ram from a with borrow 96- 97 1 2 su bb a,#data subtract immediate data from a with borrow 94 2 2 inc a increment accumulator 04 1 1 inc rn increment register 08 - 0f 1 2 inc direct increment direct byte 05 2 3 inc @ri increment indirect ram 06 - 07 1 3 inc dptr increment data pointer a3 1 1 dec a decrement accumulator 14 1 1 dec rn decrement register 18- 1f 1 2 dec direct decrement direct byte 15 2 3 dec @ri decrement indirect ram 16 - 17 1 3 mul ab multiply a and b a4 1 5 div divide a by b 84 1 5 da a decimal adjust accumulator d4 1 1
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 20 ver. g sm59 r 02g1 0 9 /20 1 5 table 2 - 2: logic operations mnemonic description code bytes cycles anl a,rn and register to accumulator 58 - 5f 1 1 anl a,direct and direct byte to accumulator 55 2 2 anl a,@ri and indirect ram to accumulator 56 - 57 1 2 anl a,#data and immediate data to accumulator 54 2 2 anl direct,a and accumulator to direct byte 52 2 3 anl direct,#data and immediate data to direct byte 53 3 4 orl a,rn or register to accumulator 48 - 4f 1 1 orl a,direct or direct byte to accumulator 45 2 2 orl a,@ri or indirect ram to accumulator 46 - 47 1 2 orl a,#data or immediate data to accumulator 44 2 2 orl direct,a or accumulator to direct byte 42 2 3 orl direct,#data or immediate data to direct byte 43 3 4 xrl a,rn exclusive or register to accumulator 68 - 6f 1 1 xrl a,direc t exclusive or direct byte to accumulator 65 2 2 xrl a,@ri exclusive or indirect ram to accumulator 66 - 67 1 2 xrl a,#data exclusive or immediate data to accumulator 64 2 2 xrl direct,a exclusive or accumulator to direct byte 62 2 3 xrl direct,#data exc lusive or immediate data to direct byte 63 3 4 clr a clear accumulator e4 1 1 cpl a complement accumulator f4 1 1 rl a rotate accumulator left 23 1 1 rlc a rotate accumulator left through carry 33 1 1 rr a rotate accumulator right 03 1 1 rrc a rotate accumulator right through carry 13 1 1 swap a swap nibbles within the accumulator c4 1 1
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 21 ver. g sm59 r 02g1 0 9 /20 1 5 table 2 - 3: data transfer mnemonic description code bytes cycles mov a,rn move register to accumulator e8 - ef 1 1 mov a,direct move direct byte to accumulator e5 2 2 mov a,@ri move indirect ram to accumulator e6 - e7 1 2 mov a,#data move immediate data to accumulator 74 2 2 mov rn,a move accumulator to register f8 - ff 1 2 mov rn,direct move direct byte to register a8 - af 2 4 mov rn,#data move immediate data to reg ister 78 - 7f 2 2 mov direct,a move accumulator to direct byte f5 2 3 mov direct,rn move register to direct byte 88 - 8f 2 3 mov direct1,direct2 move direct byte to direct byte 85 3 4 mov direct,@ri move indirect ram to direct byte 86- 87 2 4 mov direct,#d ata move immediate data to direct byte 75 3 3 mov @ri,a move accumulator to indirect ram f6 - f7 1 3 mov @ri,direct move direct byte to indirect ram a6 - a7 2 5 mov @ri,#data move immediate data to indirect ram 76 - 77 2 3 mov dptr,#data16 load data pointer with a 16 - bit constant 90 3 3 movc a,@a+dptr move code byte relative to dptr to accumulator 93 1 3 movc a,@a+pc move code byte relative to pc to accumulator 83 1 3 movx a,@ri move external ram (8 - bit addr.) to a e2 - e3 1 3 movx a,@dptr move external ram (16 - bit addr.) to a e0 1 3 movx @ri,a move a to external ram (8 - bit addr.) f2 - f3 1 4 movx @dptr,a move a to external ram (16 - bit addr.) f0 1 4 push direct push direct byte onto stack c0 2 4 pop direct pop direct byte from stack d0 2 3 xch a,rn exchan ge register with accumulator c8 - cf 1 2 xch a,direct exchange direct byte with accumulator c5 2 3 xch a,@ri exchange indirect ram with accumulator c6 - c7 1 3 xchd a,@ri exchange low - order nibble indir. ram with a d6 - d7 1 3
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 22 ver. g sm59 r 02g1 0 9 /20 1 5 table 2 - 4: program branches m nemonic description code bytes cycles acall addr11 absolute subroutine call xxx11 2 6 lcall addr16 long subroutine call 12 3 6 ret from subroutine 22 1 4 reti from interrupt 32 1 4 ajmp addr11 absolute jump xxx01 2 3 ljmp addr16 long iump 02 3 4 sjm p rel short jump (relative addr.) 80 2 3 jmp @a+dptr jump indirect relative to the dptr 73 1 2 jz rel jump if accumulator is zero 60 2 3 jnz rel jump if accumulator is not zero 70 2 3 jc rel jump if carry flag is set 40 2 3 jnc jump if carry flag is n ot set 50 2 3 jb bit,rel jump if direct bit is set 20 3 4 jnb bit,rel jump if direct bit is not set 30 3 4 jbc bit,direct rel jump if direct bit is set and clear bit 10 3 4 cjne a,direct rel compare direct byte to a and jump if not equal b5 3 4 cjne a ,#data rel compare immediate to a and jump if not equal b4 3 4 cjne rn,#data rel compare immed. to reg. and jump if not equal b8 - bf 3 4 cjne @ri,#data rel compare immed. to ind. and jump if not equal b6 - b7 3 4 djnz rn,rel decrement register and jump if not zero d8 - df 2 3 djnz direct,rel decrement direct byte and jump if not zero d5 3 4 nop no operation 00 1 1 table 2 - 5: boolean manipulation mnemonic description code bytes cycles clr c clear carry flag c3 1 1 clr bit clear direct bit c2 2 3 set b c set carry flag d3 1 1 setb bit set direct bit d2 2 3 cpl c complement carry flag b3 1 1 cpl bit complement direct bit b2 2 3 anl c,bit and direct bit to carry flag 82 2 2 anl c,/bit and complement of direct bit to carry b0 2 2 orl c,b it or direct bit to carry flag 72 2 2 orl c,/bit or complement of direct bit to carry a0 2 2 mov c,bit move direct bit to carry flag a2 2 2 mov bit,c move carry flag to direct bit 92 2 3
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 23 ver. g sm59 r 02g1 0 9 /20 1 5 3. memory structure the SM59R02G1 memory structure follow s general 8052 structure. it is 8 kb program memory. 3.1. program memory the SM59R02G1 has 8kb on - chip flash memory which can be used as general program memory or eeprom, on which include up to 1k byte specific isp service program memory space. the address range for the 8k byte is $0000 to $1fff. the address range for the isp service program is $1c00 to $1fff. the isp service program size can be partitioned as n blocks of 256 byte (n=0 to 4). when n=0 means no isp service program space available, total 8k by te memory used as program memory. when n=1 means address $1f00 to $1fff reserved for isp service program. when n=2 means memory address $1e00 to $1fff reserved for isp service program?etc. value n can be set and programmed into SM59R02G1 information bloc k by writer. i t can be used to record any data as eeprom. the procedure of this eeprom application function is described in the section 1 3 on internal isp. 1fff 1f00 1e00 1d00 1c00 0000 isp service program space, up to 1k 8k program memory space n=4 n=3 n=2 n=1 n=0 fig . 3 1: sm59r021 programmable flash
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 24 ver. g sm59 r 02g1 0 9 /20 1 5 3.2. data memory the SM59R02G1 ha s 256bytes on - chip sram, 256 bytes are the same as general 8052 internal memory structure. fig 3 - 2 (a) external memory access as read fig 3 - 2 (b) external memory access as write higher 128 bytes (accessed by indirect addressing mode only) lower 128 bytes (accessed by direct & indirect addressing mode ) sfr (accessed by direct addressing mode only) 00 7f 80 ff 80 ff fig . 3 3: ram architecture 3.2.1. data memory - lower 128 byte (00h to 7fh) data memory 00h to ffh is the same as 8052. the address 00h to 7fh can be accessed by direct and indirect addressing modes. address 00h to 1fh is register area. address 20h to 2fh is memory bit area. address 30h to 7fh is f or general memory area. 3.2.2. data memory - higher 128 byte (80h to ffh) the address 80h to ffh can be accessed by indirect addressing mode. address 80h to ffh is data area.
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 25 ver. g sm59 r 02g1 0 9 /20 1 5 4. cpu engine the SM59R02G1 engine is composed of four components: a. control unit b. arith metic ? logic unit c. memory control unit d. ram and sfr control unit the SM59R02G1 engine allows to fetch instruction from program memory and to execute using ram or sfr. the following paragraphs describe the main engine registers. mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset 8051 core acc accumulator e0h acc.7 acc.6 acc.5 acc.4 acc.3 acc.2 acc.1 acc.0 00h b b register f0h b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 00h psw program status word d0h cy ac f0 rs[1:0] ov psw.1 p 00h s p stack pointer 81h sp[7:0] 07h dpl data pointer low 0 82h dpl[7:0] 00h dph data pointer high 0 83h dph[7:0] 00h dpl1 data pointer low 1 84h dpl1[7:0] 00h dph1 data pointer high 1 85h dph1[7:0] 00h aux auxiliary register 91h brgs - - p 1 ur - - - dps 00 h ifcon interface control register 8fh its cdpr - - alec[1:0] - ispe 00h 4.1. accumulator acc is the accumulator register. most instructions use the accumulator to store the operand. mnemonic: acc address: e0h 7 6 5 4 3 2 1 0 reset acc.7 acc.6 acc05 acc. 4 acc.3 acc.2 acc.1 acc.0 00h acc[7:0]: the a (or acc) register is the standard 8052 accumulator. 4.2. b register the b register is used during multiply and divide instructions. it can also be used as a scratch pad register to store temporary data. mnemon ic: b address: f0h 7 6 5 4 3 2 1 0 reset b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 00h b[7:0]: the b register is the standard 8052 register that serves as a second accumulator.
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 26 ver. g sm59 r 02g1 0 9 /20 1 5 4.3. program status word mnemonic: psw address: d0h 7 6 5 4 3 2 1 0 reset cy ac f0 r s [1:0] ov f1 p 00h cy: carry flag. ac: auxiliary carry flag for bcd operations. f0: general purpose flag 0 available for user. rs[1:0]: register bank select, used to select working register bank. rs[1:0] bank selected location 00 bank 0 00h ? 07h 0 1 bank 1 08h ? 0fh 10 bank 2 10h ? 17h 11 bank 3 18h ? 1fh ov: overflow flag. f1: general purpose flag 1 available for user. p: parity flag, affected by hardware to indicate odd/even number of ?one? bits in the accumulator, i.e. even parity. 4.4. stack pointer the stack pointer is a 1 - byte register initialized to 07h after reset. this register is incremented before push and call instructions, causing the stack to start from location 08h. mnemonic: sp address: 81h 7 6 5 4 3 2 1 0 reset sp [7:0] 07h sp[7:0]: the stack pointer stores the scratchpad ram address where the stack begins. in other words, it always points to the top of the stack. 4.5. data pointer the data pointer (dptr) is 2 - bytes wide. the lower part is dpl, and the highest is dph. it can be loaded as a 2 - byte register (e.g. mov dptr, #data16) or as two separate registers (e.g. mov dpl,#data8). it is generally used to access the external code or data space (e.g. movc a, @a+dptr or movx a, @dptr respectively). mnemonic: dpl address: 82h 7 6 5 4 3 2 1 0 reset dpl [7:0] 00h dpl[7:0]: data pointer low 0 mnemonic: dph address: 83h 7 6 5 4 3 2 1 0 reset dph [7:0] 00h dph [7:0]: data pointer high 0
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 27 ver. g sm59 r 02g1 0 9 /20 1 5 4.6. data pointer 1 the dual data pointer accelerates the moves of data block. the standar d dptr is a 16 - bit register that is used to address external memory or peripherals. in the SM59R02G1 core the standard data pointer is called dptr, the second data pointer is called dptr1. the data pointer select bit chooses the active pointer. the data po inter select bit is located in lsb of aux register (dps). the user switches between pointers by toggling the lsb of aux register. all dptr - related instructions use the currently selected dptr for any activity. mnemonic: dpl1 address: 84h 7 6 5 4 3 2 1 0 reset dpl1 [7:0] 00h dpl1[7:0]: data pointer low 1 mnemonic: dph1 address: 85h 7 6 5 4 3 2 1 0 reset dph1 [7:0] 00h dph1[7:0]: data pointer high 1 mnemonic: aux address: 91h 7 6 5 4 3 2 1 0 reset brgs - - p 1 ur - - - dps 00h dps: data pointe r selects register. dps = 1 is selected dptr1. 4.7. interface control register mnemonic: ifcon address: 8fh 7 6 5 4 3 2 1 0 reset its cdpr - - alec[1:0] - ispe 00h its: instruction timing select. (default is 2t) its = 0, 2t instruction mode. its = 1, 1t instruction mode. cdpr: code protect (read only) alec[1:0]: ale output control register. alec[1:0] ale output 00 always output 01 no ale output 10 only read or write have ale output 11 reserved ispe: isp function enable bit ispe = 1, enable isp fu nction ispe = 0, disable isp function
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 28 ver. g sm59 r 02g1 0 9 /20 1 5 5. gpio the SM59R02G1 has six i/o ports: port 0, port 1, port 2, port 3, port 4, and port 5. ports 0, 1, 2, 3, 4 are 8 - bit ports and port 5 is a 2 - bit port (only bit 4 and bit 5) . these are: quasi - bidirectional (stand ard 8051 port outputs), push - pull, open drain, and input - only. two configuration registers for each port select the output type for each port pin. all i/o port pins on the SM59R02G1 may be configured by software to one of four types on a pin - by - pin basis, shown as below: mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset i/o port function register p0m0 port 0 output mode 0 d2h p0m0 [7:0] 00h p0m1 port 0 output mode 1 d3h p0m1[7:0] 00h p1m0 port 1 output mode 0 d4h p1m0[7: 0] 00h p1m1 port 1 output mode 1 d5h p1m1[7:0] 00h p2m0 port 2 output mode 0 d6h p2m0[7:0] 00h p2m1 port 2 output mode 1 d7h p2m1[7:0] 00h p3m0 port 3 output mode 0 dah p3m0[7:0] 00h p3m1 port 3 output mode 1 dbh p3m1[7:0] 00h p4m0 port 4 output mode 0 dch p4m0[7:0] 00h p4m1 port 4 output mode 1 ddh p4m1[7:0] 00h p5m0 port 5 output mode 0 deh - - p5m0[5:4] - - - - 00h p5m1 port 5 output mode 1 dfh - - p5m1[5:4] - - - - 00h pxm1.y pxm0.y port output mode 0 0 quasi - bidirectional (standard 8051 por t outputs) (pull - up) 0 1 push - pull 1 0 input only (high - impedance) 1 1 open drain the xtal2 and xtal1 can define as p5.4 and p5.5 by writer or isp . w hen user use external osc as system clock and input into xtal1 , o nly xtal2 can be defined as p5.4 . f or general - purpose applications, every pin can be assigned to either high or low independently as given below: mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset ports port 5 port 5 d8h - - p5.5 p5.4 - - - - f f h port 4 p ort 4 e8h p4.7 p4.6 p4.5 p4.4 p4.3 p4.2 p4.1 p4.0 ff h port 3 port 3 b0h p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 ffh port 2 port 2 a0h p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 ffh port 1 port 1 90h p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 ffh port 0 port 0 80h p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 ffh mnemonic: p0 address: 80h 7 6 5 4 3 2 1 0 reset p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 ffh p0.7~ 0: port0 [7] ~ port0 [0]
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 29 ver. g sm59 r 02g1 0 9 /20 1 5 mnemonic: p1 address: 90h 7 6 5 4 3 2 1 0 reset p1.7 p1.6 p1.5 p1.4 p1. 3 p1.2 p1.1 p1.0 ffh p1.7~ 0: port1 [7] ~ port1 [0] mnemonic: p2 address: a0h 7 6 5 4 3 2 1 0 reset p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 ffh p2.7~ 0: port2 [7] ~ port2 [0] mnemonic: p3 address: b0h 7 6 5 4 3 2 1 0 reset p3.7 p3.6 p3.5 p3.4 p 3.3 p3.2 p3.1 p3.0 ffh p3.7~ 0: port3 [7] ~ port3 [0] mnemonic: p4 address: e8h 7 6 5 4 3 2 1 0 reset p4.7 p4.6 p4.5 p4.4 p4.3 p4.2 p4.1 p4.0 ff h p4.7~ 0: port4 [7] ~ port4 [0] mnemonic: p5 address: d8h 7 6 5 4 3 2 1 0 reset - - p5.5 p5.4 - - - - f fh p5. 5 ~ 4 : port5 [ 5 ] ~ port5 [ 4 ]
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 30 ver. g sm59 r 02g1 0 9 /20 1 5 6. timer 0 and timer 1 the SM59R02G1 has three 16 - bit timer/counter registers: timer 0, timer 1 and timer 2. all can be configured for counter or timer operations. in timer mode, the timer 0 register or timer 1 regi ster is incremented every 1/12/96 machine cycles, which means that it counts up after every 1/12/96 periods of the clk signal. it?s dependent on sfr(pfcon). in counter mode, the register is incremented when the falling edge is observed at the correspondin g input pin t0or t1. since it takes 2 machine cycles to recognize a 1 - to - 0 event, the maximum input count rate is 1/2 of the oscillator frequency. there are no restrictions on the duty cycle, however to ensure proper recognition of 0 or 1 state, an input s hould be stable for at least 1 machine cycle. four operating modes can be selected for timer 0 and timer 1. two special function registers (tmod and tcon) are used to select the appropriate mode. mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset timer 0 and 1 tl0 timer 0 , low byte 8ah tl0[7:0] 00h th0 timer 0 , high byte 8ch th0[7:0] 00h tl1 timer 1 , low byte 8bh tl1[7:0] 00h th1 timer 1 , high byte 8dh th1[7:0] 00h tmod timer mode control 89h gate c/t m1 m0 gate c/ t m1 m0 00h tcon timer/counter control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h pfcon peripheral frequency control register d9h s0relps[1:0] t1ps[1:0] t0ps[1:0] 00h 6.1. timer/counter mode control register (tmod) mnemonic: tmod address: 89h 7 6 5 4 3 2 1 0 reset gate c/t m1 m0 gate c/t m1 m0 00h timer 1 timer 0 gate: if set, enables external gate control (pin int0 or int1 for counter 0 or 1, respectively). when int0 or int1 is high, and trx bit is set (see tcon register), a counter is incremented eve ry falling edge on t0 or t1 input pin c/t: selects timer or counter operation. when set to 1, a counter operation is performed, when cleared to 0, the corresponding register will function as a timer. m[1:0]: selects mode for timer/counter 0 or timer/coun ter 1. m1 m0 mode function 0 0 mode0 13 - bit counter/timer, with 5 lower bits in tl0 or tl1 register and 8 bits in th0 or th1 register (for timer 0 and timer 1, respectively). the 3 high order bits of tl0 and tl1 are hold at zero. 0 1 mode1 16 - bit counter /timer. 1 0 mode2 8 - bit auto - reload counter/timer. the reload value is kept in th0 or th1, while tl0 or tl1 is incremented every machine cycle. when tlx overflows, a value from thx is copied to tlx.
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 31 ver. g sm59 r 02g1 0 9 /20 1 5 1 1 mode3 if timer 1 m1 and m0 bits are set to 1, time r 1 stops. if timer 0 m1 and m0 bits are set to 1, timer 0 acts as two independent 8 bit timers / counters. 6.2. timer/counter control register (tcon) mnemonic: tcon address: 88h 7 6 5 4 3 2 1 0 reset tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h tf1: timer 1 o verflow flag set by hardware when timer 1 overflows. this flag can be cleared by software and is automatically cleared when interrupt is processed. tr1: timer 1 run control bit. if cleared, timer 1 stops. tf0: timer 0 overflow flag set by hardware when t imer 0 overflows. this flag can be cleared by software and is automatically cleared when interrupt is processed. tr0: timer 0 run control bit. if cleared, timer 0 stops. ie1: interrupt 1 edge flag. set by hardware, when falling edge on external pin int1 is observed. cleared when interrupt is processed. it1: interrupt 1 type control bit. selects falling edge or low level on input pin to cause interrupt. ie0: interrupt 0 edge flag. set by hardware, when falling edge on external pin int0 is observed. clear ed when interrupt is processed. it0: interrupt 0 type control bit. selects falling edge or low level on input pin to cause interrupt. 6.3. peripheral frequency control register(pfcon) mnemonic: pfcon address: d9h 7 6 5 4 3 2 1 0 reset - - s0relps[1:0] t1p s[1:0] t0ps[1:0] 00h t1ps[1:0]: timer1 prescaler select t1ps[1:0] prescaler 00 fosc/12 01 fosc 10 fosc/96 11 reserved t0ps[1:0]: timer0 prescaler select t0ps[1:0] prescaler 00 fosc/12 01 fosc 10 fosc/96 11 reserved
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 32 ver. g sm59 r 02g1 0 9 /20 1 5 6.4. mode 0 (13 - bit counter/ timer) 12 osc t 1 pin c / t = 0 c / t = 1 00 01 10 t 1 ps [ 1 : 0 ] tl 1 ( 5 bits ) th 1 ( 8 bits ) tf 1 gate 1 int 1 pin not or and tr 1 0 1 0 1 et 1 ea control if not higher priority interrupt processing jump 001 bh d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 tf 1 tl 1 th 1 96 6.5. mode 1 (16 - bit counter/timer) 12 osc t1 pin c/t = 0 c/t = 1 00 01 10 t1ps[1:0] tl1 (8 bits) th1 (8 bits) tf1 gate1 int1 pin not or and tr1 0 1 0 1 et1 ea control if not higher priority interrupt processing jump 001bh 96 d0d1d2d3d4d5d6d7 tf1 tl1 th1 d0d1d2d3d4d5d6d7
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 33 ver. g sm59 r 02g1 0 9 /20 1 5 6.6. mode 2 (8 - bit auto - reload counter/timer) t 1 pin c / t = 0 c / t = 1 t 1 ps [ 1 : 0 ] tl 1 ( 8 bits ) th 1 ( 8 bits ) tf 1 gate 1 int 1 pin not or and tr 1 0 1 0 1 et 1 ea auto reload 12 osc 00 01 10 96 control if not higher priority interrupt processing jump 001 bh 6.7. mode 3 (timer 0 acts as two independent 8 bit timers / counters) t1 pin c/t = 0 c/t = 1 t0ps[1:0] tl0 (8 bits) tf0 gate1 int1 pin not or and tr1 tr1 th0 (8 bits) tf1 interrupt request (001bh) 12 osc 00 01 10 96 control interrupt request (000bh)
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 34 ver. g sm59 r 02g1 0 9 /20 1 5 7. timer 2 and capture/compare unit timer 2 is not only a 16 - bit timer, also a 4 - channel unit with compare, capture and reload functions. it is very similar to the programmable counter array (pca) in some other mcus except pulse width modulation (pwm). mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset timer 2 and capture compare unit aux2 auxiliary register2 92h - - - - - - p42cc[1:0] 00h t2con timer 2 control c8h t2ps[2:0] t2r[1:0] - t2i[1:0] 00h cccon compa re/capture control c9h cci3 cci2 cci1 cci0 ccf3 ccf2 ccf1 ccf0 00h ccen compare/capture enable register c1h - cocam1[2:0] - cocam0[2:0] 00h ccen2 compare/capture enable 2 register d1h - cocam3[2:0] - cocam2[2:0] 00h tl2 timer 2, low byte cch tl2[7:0] 00h th2 timer 2, high byte cdh th2[7:0] 00h crcl compare/reload/ capture register, low byte cah crcl[7:0] 00h crch compare/reload/ capture register, high byte cbh crch[7:0] 00h ccl1 compare/capture register 1, low byte c2h ccl1[7:0] 00h cch1 compare/c apture register 1, high byte c3h cch1[7:0] 00h ccl2 compare/capture register 2, low byte c4h ccl2[7:0] 00h cch2 compare/capture register 2, high byte c5h cch2[7:0] 00h ccl3 compare/capture register 3, low byte c6h ccl3[7:0] 00h cch3 compare/capture reg ister 3, high byte c7h cch3[7:0] 00h mnemonic: aux2 address: 92h 7 6 5 4 3 2 1 0 reset - - - - - - p42cc[1: 0] 00h p42cc[1: 0] 00: capture/compare function on port1. 01: capture/compare function on port2 10: capture/compare function on port4 11: reserved
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 35 ver. g sm59 r 02g1 0 9 /20 1 5 mnemonic: t2con address: c8h 7 6 5 4 3 2 1 0 reset t2ps[2:0] t2r[1:0] - t2i[1:0] 00h t2ps [2:0] : prescaler select bit: t2ps = 000 ? timer 2 is clocked with the oscillator frequency. t2ps = 001 ? timer 2 is clocked with 1/2 of the oscillat or frequency. t2ps = 010 ? timer 2 is clocked with 1/4 of the oscillator frequency. t2ps = 011 ? timer 2 is clocked with 1/6 of the oscillator frequency. t2ps = 100 ? timer 2 is clocked with 1/8 of the oscillator frequency. t2ps = 101 ? timer 2 is clocked with 1/12 of the oscillator frequency. t2ps = 110 ? timer 2 is clocked with 1/24 of the oscillator frequency. t2r[1:0]: timer 2 reload mode selection t2r[1:0] = 0x ? reload disabled t2r[1:0] = 10 ? mode 0 t2r[1:0] = 11 ? mode 1 t2i[1:0]: timer 2 input se lection t2i[1:0] = 00 ? timer 2 stop t2i[1:0] = 01 ? input frequency from prescaler (t2ps[2:0]) t2i[1:0] = 10 ? timer 2 is incremented by external signal at pin t2 t2i[1:0] = 11 ? internal clock input is gated to the timer 2 mnemonic: c c con address: c9h 7 6 5 4 3 2 1 0 reset cci3 cci2 cci1 cci0 ccf3 ccf2 ccf1 ccf0 00h cci3: compare/capture 3 interrupt control bit. ?1? is enable. cci2: compare/capture 2 interrupt control bit. ?1? is enable. cci1: compare/capture 1 interrupt control bit. ?1? is enab le. cci0: compare/capture 0 interrupt control bit. ?1? is enable. ccf3: compare/capture 3 flag set by hardware. this flag can be cleared by software. ccf2: compare/capture 2 flag set by hardware. this flag can be cleared by software. ccf1: compare/cap ture 1 flag set by hardware. this flag can be cleared by software. ccf0: compare/capture 0 flag set by hardware. this flag can be cleared by software. compare/capture interrupt share t2 interrupt vector. mnemonic: ccen address: c1h 7 6 5 4 3 2 1 0 rese t - cocam1[2:0] - cocam0[2:0] 00h cocam1[2:0] 000: compare/capture disable 001: compare enable but no output on pin 010: compare mode 0 011: compare mode 1 100: capture on rising edge at pin cc1 101: capture on falling edge at pin cc1 110: capture on b oth rising and falling edge at pin cc1 111: capture on write operation into register cc1 cocam0[2:0] 000: compare/capture disable 001: compare enable but no output on pin 010: compare mode 0 011: compare mode 1
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 36 ver. g sm59 r 02g1 0 9 /20 1 5 100: capture on rising edge at pin cc0 101: capture on falling edge at pin cc0 110: capture on both rising and falling edge at pin cc0 111: capture on write operation into register cc0 mnemonic: ccen2 address: d1h 7 6 5 4 3 2 1 0 reset - cocam3[2:0] - cocam2[2:0] 00h cocam3[2:0] 000: compare/ capture disable 001: compare enable but no output on pin 010: compare mode 0 011: compare mode 1 100: capture on rising edge at pin cc3 101: capture on falling edge at pin cc3 110: capture on both rising and falling edge at pin cc3 111: capture on write op eration into register cc3 cocam2[2:0] 000: compare/capture disable 001: compare enable but no output on pin 010: compare mode 0 011: compare mode 1 100: capture on rising edge at pin cc2 101: capture on falling edge at pin cc2 110: capture on both rising and falling edge at pin cc2 111: capture on write operation into register cc2 7.1. timer 2 function timer 2 can operate as timer, event counter, or gated timer as explained later. 7.1.1. timer mode in this mode timer 2 can by incremented in various frequency tha t depending on the prescaler. the prescaler is selected by bit t2ps[2:0] in register t2con . 7.1.2. event counter mode in this mode, the timer is incremented when external signal t2 change value from 1 to 0. the t2 input is sampled in every cycle. timer 2 is inc remented in the cycle following the one in which the transition was detected. 7.1.3. gated timer mode in this mode, the internal clock which incremented timer 2 is gated by external signal t2. 7.1.4. reload of timer 2 reload (16 - bit reload from the crc register) can be executed in the following two modes: mode 0: reload signal is generate by a timer 2 overflows - auto reload mode 1: reload signal is generate by a negative transition at the corresponding input pin t2ex. 7.2. compare function in the four independent comp arators, the value stored in any compare/capture register is compared with the contents of the timer register. the compare modes 0 and 1 are selected by bit t2cm. in both compare modes, the results of comparison arrives at port 1 within the same machine cycle in which the internal compare signal is activated.
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 37 ver. g sm59 r 02g1 0 9 /20 1 5 7.2.1. compare mode 0 in mode 0, when the value in timer 2 equals the value of the compare register, the output signal changes from low to high. it goes back to a low level on timer overflow. in this mo de, writing to the port will have no effect, because the input line from the internal bus and the write - to - latch line are disconnected. the following figure illustrates the function of compare mode 0. fig . 7 - 1: compare mode 0 function crc or ccx contents of timer 2 reload value ccx output timer 2 = ccx value timer 2 overflow 7.2.2. compare mode 1 in compare mode 1, the transition of the output signal can be determined by software. a timer 2 overflow causes no output change. in this mode, both transitions of a signal can be controlled. fig . 7 - 2 shows a functional diagra m of a register/port configuration in compare mode 1. in compare mode 1, the value is written first to the ?shadow register?, when compare signal is active, this value is transferred to the output register. fig. 7 - 2: compare mode 1 function
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 38 ver. g sm59 r 02g1 0 9 /20 1 5 crc or ccx contents of timer 2 reload value ccx output timer 2 = ccx value ccx output output register shadow register 7.3. capture function actual timer/counter contents can be saved into registers ccx or crc upon an external event (mode 0) or a software write operation (mode 1). 7.3.1. capture mode 0 in mode 0, value capture of timer 2 is executed when: (a) ri sing edge on input cc0 - cc3 (b) falling edge on input cc0 - cc3 (c) both rising and falling edge on input cc0 - cc3 the contents of timer 2 will be latched into the appropriate capture register. 7.3.2. capture mode 1 in mode 1, value capture of timer 2 is caused by writing any value into the low - order byte of the dedicated capture register. the value written to the capture register is irrelevant to this function. the contents of timer 2 will be latched into the appropriate capture register.
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 39 ver. g sm59 r 02g1 0 9 /20 1 5 8. serial i nterface 0 as the conventional uart, the communication speed can be selected by configuring the baud rate in sfrs. these two serial buffers consists of two separate registers, a transmit buffer and a receive buffer. writing data to the sfr s0buf sets this data in seri al output buffer and starts the transmission. reading from the s0buf reads data from the serial receive buffer. the serial port can simultaneously transmit and receive data. it can also buffer 1 byte at receive, which prevents the receive data from being lost if the cpu reads the second byte before the transmission of the first byte is completed. mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset serial interface 0 pcon power control 87h smod - - - - - stop idle 4 0h aux auxiliary register 91h brgs - - p 1 ur - - - dps 00h s0con serial port 0 control register 98h sm0 sm1 sm20 ren0 tb80 rb80 ti0 ri0 00h s0rell serial port 0 reload register low byte aah s0rel .7 s0rel .6 s0rel .5 s0rel .4 s0rel .3 s0rel .2 s0rel .1 s0rel .0 00h s0r elh serial port 0 reload register high byte bah - - - - - - s0rel .9 s0rel .8 00h s0buf serial port 0 data buffer 99h s0buf[7:0] 00h pfcon peripheral frequency control register d9h s0relps[1:0] t1ps[1:0] t0ps[1:0] 00h mnemonic: aux address: 91h 7 6 5 4 3 2 1 0 reset brgs - - p 1 ur - - - dps 00h brgs: baud rate generator. brgs = 0 - baud rate generator from timer 1. brgs = 1 - baud rate generator by s0rel. p1ur: p1ur = 0 ? serial interface function on p3. p1ur = 1 ? serial interface function on p1. mnemonic: s0con address: 98h 7 6 5 4 3 2 1 0 reset sm0 sm1 sm20 ren0 tb80 rb80 ti0 ri0 00h sm0,sm1: serial port 0 mode selection. sm0 sm1 mode 0 0 0 0 1 1 1 0 2 1 1 3 the 4 modes in uart0, mode 0 ~ 3, are explained later. sm20: enables multiproc essor communication feature ren0: if set, enables serial reception. cleared by software to disable reception. tb80: the 9 th transmitted data bit in modes 2 and 3. set or cleared by the cpu depending on the function it performs such as parity check, mult iprocessor communication etc.
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 40 ver. g sm59 r 02g1 0 9 /20 1 5 rb80: in modes 2 and 3, it is the 9 th data bit received. in mode 1, if sm20 is 0, rb80 is the stop bit. in mode 0, this bit is not used. must be cleared by software. ti0: transmit interrupt flag, set by hardware after com pletion of a serial transfer. must be cleared by software. ri0: receive interrupt flag, set by hardware after completion of a serial reception. must be cleared by software. mnemonic: pfcon address: d9h 7 6 5 4 3 2 1 0 reset - - s0relps[1:0] t1ps[1:0] t0ps[1:0] 00h s0relps[1:0]: s0rel prescaler select s0relps[1:0] prescaler 00 fosc/64 01 fosc/32 t 1 ps[1:0]: timer 1 prescaler select t1ps[1:0] prescaler 00 fosc/12 01 fosc 10 fosc/96 11 reserved 8.1. serial interface 0 the serial interface 0 can operate in the following 4 modes: sm0 sm1 mode description board rate 0 0 0 shift register fosc/12 0 1 1 8 - bit uart variable 1 0 2 9 - bit uart fosc/32 or fosc/64 1 1 3 9 - bit uart variable h ere fosc is the crystal or oscillator frequency. 8.1.1. mode 0 pi n rxd0 serves as input and output. txd0 outputs the shift clock. 8 bits are transmitted with lsb first. the baud rate is fixed at 1/12 of the crystal frequency. reception is initialized in mode 0 by setting the flags in s0con as follows: ri0 = 0 and re n0 = 1. in the other modes, a start bit when ren0 = 1 starts receiving serial data. fig. 8 - 1: transmit mode 0 for serial 0
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 41 ver. g sm59 r 02g1 0 9 /20 1 5 fig. 8 - 2: receive mode 0 for serial 0 8.1.2. mode 1 here pin rxd0 serves as input, and txd0 serves as serial output. no external s hift clock is used, 10 bits are transmitted: a start bit (always 0), 8 data bits (lsb first), and a stop bit (always 1). on receive, a start bit synchronize s the transmission, 8 data bits are available by reading s0buf, and a stop bit sets the flag rb80 i n the sfr s0con. in mode 1, either internal baud rate generator or timer 1 can be use to specify the desired baud rate. fig. 8 - 3: transmit mode 1 for serial 0 fig. 8 - 4: receive mode 1 for serial 0 8.1.3. mode 2 this mode is similar to mode 1, but with tw o differences. the baud rate is fixed at 1/32 (smod=1) or 1/64(smod=0) of oscillator frequency, and 11 bits are transmitted or received: a start bit (0), 8 data bits (lsb first), a programmable bit 9 , and a stop bit (1). bit 9 can be used to control the parity of the serial interface: at transmission, bit tb80 in s0con is output as bit 9, and at receive, bit 9 affects rb80 in sfr s0con. 8.1.4. mode 3 the only difference between mode 2 and mode 3 is that: in mode 3, either internal baud rate generator or timer 1 can be use to specify baud rate. fig. 8 - 5: transmit modes 2 and 3 for serial 0
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 42 ver. g sm59 r 02g1 0 9 /20 1 5 fig. 8 - 6: receive modes 2 and 3 for serial 0 8.2. multiprocessor communication of serial interface 0 the feature of receiving 9 bits in modes 2 and 3 of serial interface 0 can be used fo r multiprocessor communication. in this case, the slave processors have bit sm20 in s0con set to 1. when the master processor outputs slave?s address, it sets the bit 9 to 1, causing a serial port recei ve interrupt in all the slaves. the sla ve processors compare the received b yte with their network address. if matched, the addressed slave will clear sm20 and receive the rest of the message, while other slaves will leave sm20 bit unaffected and ignore this message. after addressing the slave, the host will output the rest of the message with the bit 9 set to 0, so no serial port receive interrupt will be generated in unselected slaves. 8.3. baud rate generator 8.3.1. serial interface 0 modes 1 and 3 (a) when brgs = 0 (in sfr aux): t1ps[1:0] = 00 ( ) smod 2f baud rate 32 12 256 th1 osc = ? t1ps[1:0] = 01 ( ) smod 2f baud rate 32 256 th1 osc = ? t1ps[1:0] = 10 ( ) smod 2f baud rate 32 96 256 th1 osc = ? s0relps[1:0] = 00 ( ) smod osc 10 2f baud rate 64 2 s0rel = ? s0relps[1:0] = 01 ( ) smod osc 10 2f baud rate 32 2 s0rel = ?
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 43 ver. g sm59 r 02g1 0 9 /20 1 5 9. watchdog timer the watch dog timer (wdt) is an 8 - bit free - running counter that generate reset signal if the counter overflows. the wdt is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead loop or runaway. the wdt function can help user software recover from abnormal software condition. the wdt is different from timer0, timer1 and timer2 of general 8052. to prevent a wdt reset can be done by software periodically clearing the wdt counter. user should check wdtf bit of wdtc register whene ver un - predicted reset happened. after an external reset the watchdog timer is disabled and all registers are set to zeros . the watchdog timer has a free running on - chip rc oscillator (2 5 0khz). the wdt will keep on running even after the system clock has been turned off (for example, in sleep mode). during normal operation or sleep mode, a wdt time - out (if enabled) will cause the mcu to reset. the wdt can be enabled or disabled any time during the normal mode. please refer the wdte bit of wdtc register. th e default wdt time - out period is approximately 16.38 ms (wdtm [3:0] = 0100b) . the wdt has selectable divider input for the time base source clock. to select the divider input, the setting of bit3 ~ bit0 (wdtm [3:0]) of watch dog timer control register (wdt c) should be set accordingly. wdtm 2 250khz = wdtclk watchdog reset time = wdtclk 256 table 9 .1 wdt time - out period wdtm [3:0] divider (2 5 0 khz rc oscillator in) time period @ 2 5 0khz 0000 1 1. 02 ms 0001 2 2. 05 ms 0010 4 4.10 ms 0011 8 8. 19 ms 0100 16 16.38 ms (default) 0101 32 32.77ms 0110 64 65.54ms 0111 128 131.07ms 1000 256 262.14ms 1001 512 524.29ms 1010 1024 1.05s 1011 2048 2.10s 1100 4096 4.19s 1101 8192 8.39s 1110 16384 16.78s 1111 32768 33.55s when mcu is reset, the mc u will be read wdten control bit status. when wdten bit is set to 1, the watchdog function will be disabled no matter what the wdte bit status is. when wdten bit is clear to 0, the watchdog function will be enabled if wdte bit is set to 1 by program. user can to set wdten on the writer or i s p. the program can enable the wdt function by programming 1 to the wdte bit premise that wdten control bit is clear to 0. after wdte set to 1, the 8 bit - counter starts to count with the selected time base source clock w hich set by wdtm [3:0]. it will generate a reset signal when overflows. the wdte bit will be cleared to 0 automatically when mcu been reset, either hardware reset or wdt reset. once the watchdog is started it cannot be stopped. user can refreshed the watc hdog timer to zero by writing 0x55 to watch dog timer refresh key (wdtk) register. this will clear the content of the 8 - bit counter and let the counter re - start to count from the beginning. the watchdog timer must be refreshed regularly to prevent reset re quest signal from
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 4 4 ver. g sm59 r 02g1 0 9 /20 1 5 becoming active. when watchdog timer is overflow, the wdtf flag will set to one and automatically reset mcu. the wdtf flag can be clear by software or external reset or power on reset. 250khz rc oscillator wdtm 2 1 wdtc takey (55, aa, 5a) wdtm[3:0] wdten enable/disable wdt wdt counter wdtclk wdtk (0x55) refresh wdt counter 1. power on reset 2. external reset 3. software write ?0? wdtf set wdtf = 1 clear wdtf = 0 wdt time-out reset enable wdtc write attribute wdt time-out select wdt time-out interrupt cwdtr = 0 cwdtr = 1 fig. 9 - 1: watchdog ti mer block diagram mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset watchdog timer takey time access key register f7h takey [7:0] 00h wdtc watchdog timer control register b6h - cwdtr wdte - wdtm [3:0] 04h wdtk watchdog timer refresh key b7h wdtk[7:0] 00h rsts reset status flag register a1h - - - pdrf wdtf swrf lvrf porf 00h mnemonic: takey address: f7h 7 6 5 4 3 2 1 0 reset takey [7:0] 00h watchdog timer control register (wdtc) is read - only by default; software mu st write three specific values 55h, aah and 5ah sequentially to the takey register to enable the wdtc write attribute. that is: mov takey, #55h mov takey, #aah mov takey, #5ah mnemonic: wdtc address: b6h 7 6 5 4 3 2 1 0 reset - cwdtr wdte - wdtm [3:0] 04h cwdtr: 0: watchdog reset 1: watchdog interrupt wdte: control bit used to enable watchdog timer.
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 45 ver. g sm59 r 02g1 0 9 /20 1 5 the wdte bit can be used only if wdten is "0". if the wdten bit is "0", then wdt can be disabled / enabled by the wdte bit. 0: disable wdt. 1: enable wdt . the wdte bit is not used if wdten is "1". that is, if the wdten bit is "1", wdt is always disabled no matter what the wdte bit status is. the wdte bit can be read and written. wdtm [3:0]: wdt clock source divider bit. please see table 7.8.1 to reference the wdt time - out period. mnemonic: wdtk address: b7h 7 6 5 4 3 2 1 0 reset wdtk[7:0] 00h wdtk: watchdog timer refresh key. a programmer must write 0x55 into wdtk register, and then the watchdog timer will be cleared to zero. for example, if enable wdt and select time - out reset period is 327.68ms. first, programming the information block op3 bit7 wdten to ?0?. secondly, mov takey, #55h mov takey, #aah mov takey, #5ah ; enable wdtc write attribute. mov wdtc, #28h ; set wdtm [3:0] = 1000b. set wdte =1 to enable wdt ; function. . . mov wdtk, #55h ; clear wdt timer to 0. mnemonic: rsts address: b6h 7 6 5 4 3 2 1 0 reset - - - pdrf wdtf swrf lvrf porf 0 0 h wdtf: watchdog timer reset flag. when mcu is reset by watchdog, wdtf flag will be set to one by h ardware. this flag clear by software or external reset or power on reset.
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 46 ver. g sm59 r 02g1 0 9 /20 1 5 10. interrupt the SM59R02G1 provides 7 interrupt sources with four priority levels. each source has its own request flag(s) located in a special function register. each interrupt requ ested by the corresponding flag could individually be enabled or disabled by the enable bits in sfr?s ien0 , ien1 and ien2 . when the interrupt occurs, the engine will vector to the predetermined address as shown in table 10 .1. once interrupt service has be gun, it can be interrupted only by a higher priority interrupt. the interrupt service is terminated by a return from instruction reti. when an reti is performed, the processor will return to the instruction that would have been next when interrupt occurred . when the interrupt condition occurs, the processor will also indicate this by setting a flag bit. this bit is set regardless of whether the interrupt is enabled or disabled. each interrupt flag is sampled once per machine cycle, and then samples are pol led by hardware. if the sample indicates a pending interrupt when the interrupt is enabled, then interrupt request flag is set. on the next instruction cycle the interrupt will be acknowledged by hardware forcing an lcall to appropriate vector address. in terrupt response will require a varying amount of time depending on the state of microcontroller when the interrupt occurs. if microcontroller is performing an interrupt service with equal or greater priority, the new interrupt will not be invoked. in othe r cases, the response time depends on current instruction. the fastest possible response to an interrupt is 7 machine cycles. this includes one machine cycle for detecting the interrupt and six cycles for perform the lcall. table 1 0 - 1: interrupt vectors i nterrupt request flags interrupt vector address interrupt number *(use keil c tool) ie0 ? external interrupt 0 0003h 0 tf0 ? timer 0 interrupt 000bh 1 ie1 ? external interrupt 1 0013h 2 tf1 ? timer 1 interrupt 001bh 3 ri0/ti0 ? serial channel 0 interrupt 0023h 4 tf2/exf2 ? timer 2 interrupt 002bh 5 wdt interrupt 008bh 17 *see keil c about c51 user?s guide about interrupt function description mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset interrupt i en0 interrupt enable 0 register a8h ea - et2 es0 et1 ex1 et0 ex0 00h ien1 interrupt enable 1 register b8h exen 2 - - - - - - - 00h ircon interrupt request register c0h exf2 tf2 - - - - - - 00h ien2 interrupt enable 2 register 9ah - - - - - - iewd t - 00h ircon2 interrupt request register 2 97h - - - - - - wdti f - 00h ip0 interrupt priority level 0 a9h - - ip0.5 ip0.4 ip0.3 ip0.2 ip0.1 ip0.0 00h ip1 interrupt priority level 1 b9h - - ip1.5 ip1.4 ip1.3 ip1.2 ip1.1 ip1.0 00h
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 47 ver. g sm59 r 02g1 0 9 /20 1 5 interrupt enable 0 register( ien0) mnemonic: ien0 address: a8h 7 6 5 4 3 2 1 0 reset ea - et2 es0 et1 ex1 et0 ex0 00h ea: ea=0 ? disable all interrupt. ea=1 ? enable all interrupt. et2: et2=0 ? disable timer 2 overflow or external reload interrupt. et2=1 ? enable timer 2 overflo w or external reload interrupt. es0: es0=0 ? disable serial channel 0 interrupt. es0=1 ? enable serial channel 0 interrupt. et1: et1=0 ? disable timer 1 overflow interrupt. et1=1 ? enable timer 1 overflow interrupt. ex1: ex1=0 ? disable external interru pt 1. ex1=1 ? enable external interrupt 1. et0: et0=0 ? disable timer 0 overflow interrupt. et0=1 ? enable timer 0 overflow interrupt. ex0: ex0=0 ? disable external interrupt 0. ex0=1 ? enable external interrupt 0. interrupt enable 1 register(ien1) mn emonic: ien1 address: b8h 7 6 5 4 3 2 1 0 reset exen2 - - - - - - - 00h exen2: timer 2 reload interrupt enable. exen2 = 0 ? disable timer 2 external reload interrupt. exen2 = 1 ? enable timer 2 external reload interrupt. interrupt enable 2 register(i en2) mnemonic: ien2 address: 9ah 7 6 5 4 3 2 1 0 reset - - - - - - iewdt - 00h i ew dt: wdt interrupt enable.. iewdt = 0 ? disable wdt interrupt. iewdt = 1 ? enable wdt interrupt. interrupt request register(ircon) mnemonic: ircon address: c0h 7 6 5 4 3 2 1 0 reset exf2 tf2 - - - - - - 00h exf2: timer 2 external reloads flag. must be cleared by software. tf2: timer 2 overflows flag. must be cleared by software.
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 48 ver. g sm59 r 02g1 0 9 /20 1 5 interrupt request register 2(ircon2) mnemonic: ircon2 address: 97h 7 6 5 4 3 2 1 0 reset - - - - - - wdt if - 00h wdt if : wdt interrupt flag . priority level structure all interrupt sources are combined in groups: table 1 0 - 2 : priority level groups groups external interrupt 0 - timer 0 interrupt - external interrupt 1 wdt i nterrupt timer 1 interrupt - serial channel 0 interrupt - timer 2 interrupt - each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit in the special function register ip0 and one in ip1. if requests of the same priority level will be received simultaneously, an internal polling sequence determines which request is serviced first. mnemonic: ip0 address: a9h 7 6 5 4 3 2 1 0 reset - - ip0.5 ip0.4 ip0.3 ip0.2 ip0.1 ip0.0 00h mnemo nic: ip1 address: b9h 7 6 5 4 3 2 1 0 reset - - ip1.5 ip1.4 ip1.3 ip1.2 ip1.1 ip1.0 00h table 1 0 - 3 : priority levels ip1.x ip0.x priority level 0 0 level0 (lowest) 0 1 level1 1 0 level2 1 1 level3 (highest) table 1 0 - 4 : groups of priority bit gro up ip1.0, ip0.0 external interrupt 0 - ip1.1, ip0.1 timer 0 interrupt wdt interrupt ip1.2, ip0.2 external interrupt 1 - ip1.3, ip0.3 timer 1 interrupt - ip1.4, ip0.4 serial channel 0 interrupt - ip1.5, ip0.5 timer 2 interrupt -
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 49 ver. g sm59 r 02g1 0 9 /20 1 5 table 1 0 - 5 : pollin g sequence interrupt source sequence external interrupt 0 timer 0 interrupt wdt interrupt external interrupt 1 timer 1 interrupt serial channel 0 interrupt timer 2 interrupt po lling sequence
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 50 ver. g sm59 r 02g1 0 9 /20 1 5 11. power management unit power management unit serves two power management modes, idle and stop, for the users to do power saving function. mnemonic: pcon address: 87h 7 6 5 4 3 2 1 0 reset smod - - - - - stop idle 4 0h stop: stop mode control bit. setting this bit turning on the stop mode. stop bit is always read as 0 idle: idle mode control bit. setting this bit turning on the idle mode. idle bit is always read as 0 11.1. idle mode setting the idle bit of pcon register invokes the idle mode. the idle mode leaves internal clocks and peripherals running. power consum ption drops because the cpu is not active. the cpu can exit the idle state with any interrupts or a reset. 11.2. stop mode setting the stop bit of pcon register invokes the stop mode. all internal clocking in this mode is turn off. the cpu will exit this state from a no - clocked interrupt (external int0/1 ) or wdt interrupt or a reset (wdt , lvr ) condition. internally generated interrupts (timer, serial port ...) have no effect on stop mode since they require clocking activity.
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 51 ver. g sm59 r 02g1 0 9 /20 1 5 12. low voltage control mnemonic: lv c address: e6h 7 6 5 4 3 2 1 0 reset - - lvre n - - - - - 00h lvre n : external low voltage reset function enable bit. lvre n = 0 : disable external low voltage reset function. lvr en = 1 : enable external low voltage reset function. l vr - level symbol parameter min typ max units v lvr low voltage reset voltage level 1.9 2.1 2.3 v
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 52 ver. g sm59 r 02g1 0 9 /20 1 5 13. in - system programming ( internal isp) the SM59R02G1 can generate flash control signal by internal hardware circuit. users utilize flash control register, fl ash address register and flash data register to perform the isp function without removing the SM59R02G1 from the system. the SM59R02G1 provides internal flash control signals which can do flash program/chip erase/page erase/protect functions. user need to design and use any kind of interface which SM59R02G1 can input data. user then utilize isp service program to perform the flash program/chip erase/page erase/protect functions. 13.1. isp service program the isp service program is a user developed firmware prog ram which resides in the isp service program space. after user developed the isp service program, user then determine the size of the isp service program. user need to program the isp service program in the SM59R02G1 for the isp purpose. the isp service p rograms were developed by user so that it should includes any features which relates to the flash memory programming function as well as communication protocol between SM59R02G1 and host device which output data to the SM59R02G1 . for example, if user utili ze uart interface to receive/transmit data between SM59R02G1 and host device, the isp service program should include baud rate, checksum or parity check or any error - checking mechanism to avoid data transmission error. the isp service program can be initi ated under SM59R02G1 active or idle mode. it can not be initiated under power down mode. 13.2. lock bit (n) the lock bit n has two functions: one is for service program size configuration and the other is to lock the isp service program space from flash erase function. the isp service program space address range $1c00 to $1fff. it can be divided as blocks of n*256 byte. (n=0 to 4). when n=0 means no isp function, all of 8k byte flash memory can be used as program memory. when n=1 means isp service program occu pies 256 byte while the rest of 7 .75 k byte flash memory can be used as program memory. the maximum isp service program allowed is 1k byte when n=4. under such configuration, the usable program memory space is 7k byte. after n determined, SM59R02G1 will re serve the isp service program space downward from the top of the program address $ 1 fff. the start address of the isp service program located at $ 1 x00 while x is depending on the lock bit n. as shown in table 1 3 - 1 . the lock bit n function is different from the flash protect function. the flash erase function can erase all of the flash memory except for the locked isp service program space. if the flash not has been protected, the content of isp service program still can be read. if the flash has been protec ted, the overall content of flash program memory space including isp service program space can not be read. table 1 3 .1 isp code area . n isp service program address 0 no isp service program 1 256 bytes ( $ 1 f 00h ~ $ 1 f ffh ) 2 512 bytes ( $ 1 e00h ~ $ 1 f ffh ) 3 7 68 bytes ( $ 1 d00h ~ $ 1 f ffh ) 4 1.0 k bytes ( $ 1 c00h ~ $ 1 f ffh ) isp service program configurable in n*256 byte (n= 0 ~ 4 ) 13.3. program the isp service program after lock bit n is set and isp service program been programmed, the isp service program memory will b e protected (locked) automatically. the lock bit n has its own program/erase timing. it is different from the flash
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 53 ver. g sm59 r 02g1 0 9 /20 1 5 memory program/erase timing so the locked isp service program can not be erased by flash erase function. if user needs to erase the locked i sp service program, he can do it by writer only. user can not change isp service program when SM59R02G1 was in system. 13.4. initiate isp service program to initiate the isp service program is to load the program counter (pc) with start address of isp service program and execute it. there are four ways to do so: (1) blank reset. hardware reset with first flash address blank ($0000=#ffh) will load the pc with start address of isp service program. the hardware reset includes internal (power on reset) and external pa d reset. (2) execute jump instruction can load the start address of the isp service program to pc. (3) enters isp service program by hardware setting. user can force SM59R02G1 enter isp service program by setting p2.6, p2.7 ?active low? or p4.3 ? active low? duri ng hardware reset period. the hardware reset includes internal (power on reset) and external pad reset. in application system design, user should take care of the setting of p2.6, p2.7 or p4.3 at reset period to prevent SM59R02G1 from entering isp service program. (4) enter?s isp service program by hardware setting, the port3.0 will be detected the two clock signals during hardware reset period. the hardware reset includes internal (power on reset) and external pad reset. and detect 2 clock signals after hardwa re reset. during hardware reset period , t he hardware will detect the status of p2.6/p2.7/p4.3/p3.0. if they meet one of above conditions, chip will switch to isp mode automatically. after isp service program executed, user need to reset the SM59R02G1 , eit her by hardware reset or by wdt, or jump to the address $0000 to re - start the firmware program. there are 8 kinds of entry mechanisms for user different applications. this entry method will select on the writer or i s p. (1) first address blank. i .e. $0000 = 0 xff. and triggered by internal reset signal. (2) first address blank. i .e. $0000 = 0xff. and triggered by pad reset signal. (3) p2.6 = 0 & p2.7 = 0. and triggered by internal reset signal. (4) p2.6 = 0 & p2.7 = 0. and triggered by pad reset signal. (5) p4.3 = 0. and trigg ered by internal reset signal. (6) p4.3 = 0. and triggered by pad reset signal. (7) p3.0 input 2 clocks. and triggered by internal reset signal. (8) p3.0 input 2 clocks. and triggered by pad reset signal. 13.5. isp register ? takey, ifcon, ispfah, ispfal, ispfd and ispfc mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset isp function takey time access key register f7h takey [7:0] 00h ifcon interface control register 8fh its cdpr - - alec[1:0] - ispe 00h ispfah isp flash address - high reg ister e1h - - - ispfah [4:0] ffh ispfal isp flash address - low register e2h ispfal [7:0] ffh ispfd isp flash data register e3h ispfd [7:0] ffh ispfc isp flash control register e4h emf1 emf2 emf3 emf4 - ispf.2 ispf.1 ispf.0 00h
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 54 ver. g sm59 r 02g1 0 9 /20 1 5 mnemonic: takey address : f7h 7 6 5 4 3 2 1 0 reset takey [7:0] 00h isp enable bit (ispe) is read - only by default, software must write three specific values 55h, aah and 5ah sequentially to the takey register to enable the ispe bit write attribute. that is: mov takey, #55h m ov takey, #aah mov takey, #5ah mnemonic: ifcon address: 8fh 7 6 5 4 3 2 1 0 reset its cdpr - - alec[1:0] - ispe 00h the bit 0 (ispe) of ifcon is isp enable bit. user can enable overall SM59R02G1 isp function by setting ispe bit to 1, to disable overal l isp function by set ispe to 0. the function of ispe behaves like a security key. user can disable overall isp function to prevent software program be erased accidentally. isp registers ispfah, ispfal, ispfd and ispfc are read - only by default. software mu st be set ispe bit to 1 to enable these 4 registers write attribute. mnemonic: ispfah address: e1h 7 6 5 4 3 2 1 0 reset - - - ispfah4 ispfah3 ispfah2 ispfah1 ispfah0 ffh ispfah [ 4 :0]: flash address - high for isp function mnemonic: ispfal address: e2 h 7 6 5 4 3 2 1 0 reset ispfal7 ispfal6 ispfal5 ispfal4 ispfal3 ispfal2 ispfal1 ispfal0 ffh ispfal [7:0]: flash address - low for isp function the ispfah & ispfal provide the 1 3 - bit flash memory address for isp function. the flash memory address should not include the isp service program space address. if the flash memory address indicated by ispfah & ispfal registers overlay with the isp service program space address, the flash program/page erase of isp function executed thereafter will have no effect. mnemonic: ispfd address: e3h 7 6 5 4 3 2 1 0 reset ispfd7 ispfd6 ispfd5 ispfd4 ispfd3 ispfd2 ispfd1 ispfd0 ffh ispfd [7:0]: flash data for isp function. the ispfd provide the 8 - bit data register for isp function. mnemonic: ispfc address: e4h 7 6 5 4 3 2 1 0 reset emf1 emf2 emf3 emf4 - ispf[2] ispf[1] ispf[0] 00h emf1: entry mechanism (1) flag, clear by reset. (read only) emf2: entry mechanism (2) flag, clear by reset. (read only) emf3: entry mechanism (3) flag, clear by reset. (read only) em f4: entry mechanism (4) flag, clear by reset. (read only) ispf [2:0]: isp function select bit.
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 55 ver. g sm59 r 02g1 0 9 /20 1 5 ispf[2:0] isp function 000 byte program 001 chip protect 010 page erase 011 chip erase 100 write option 101 read option 110 erase option 111 finish fl ag one page of flash memory is 256 byte the option function can access the internal reset time select(description in section 1.4.1) clock source select(description in section 1.5) p4[4:7] pins function select(description in section 5) wdten control bit (description in section 9 ) or isp entry mechanisms select(description in section 1 3 ) . when chip pro tected or no isp service, option can only read. the choice isp function will start to execute once the software write data to ispfc register. to perform byte program/page erases isp function, user need to specify flash address at first. when performing page erase function, SM59R02G1 will erase entire page which flash address indicated by ispfah & ispfal registers located within the page. e.g. flash address: $xymn page erase function will erase from $xy00 to $xyff to perform the chip erase isp function , SM59R02G1 will erase all the flash program memory except the isp service program space. to perform chip protect isp function, the SM59R02G1 flash memory content will be read #00h. e.g. isp service program to do the byte program - to program #22h to the address $1005h mov takey, #55h mov takey, #aah mov takey, #5ah ; enable ispe write attribute mov ifcon, #01h ; enable SM59R02G1 isp function mov ispfah, #10h ; set flash address - high, 10h mov ispfal, #05h ; set flash address - low, 05h mov ispfd, #22h ; set flash data to be programmed, data = 22h mov ispfc, #00h ; start to program #22h to the flash address $1005h
s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 56 ver. g sm59 r 02g1 0 9 /20 1 5 operating conditions symbol description min. typ. max. unit. remarks ta operating temperature - 40 25 85 ambient temperature under bias v dd supply voltage 2.7 5.5 v dc characteristics t a = - 40 to 85 , v cc = 5.0v symbol parameter valid min max units conditions vil1 input low - voltage port 0,1,2,3,4,5 - 0.5 0.8 v vcc=5v vil2 input low - voltage res, xtal1 0 0.8 v vih1 input high - volta ge port 0,1,2,3,4,5 2.0 v cc + 0.5 v vih2 input high - voltage res, xtal1 70%vcc v cc + 0.5 v vol output low - voltage port 0,1,2,3,4,5 0.4 v iol=4.9ma vcc=5v voh1 output high - voltage using strong pull - up (1) port 0,1,2,3,4,5 90% v cc v ioh= - 4.6 ma voh2 output high - voltage using weak pull - up (2) port 0,1,2,3,4,5 2.4 v ioh= - 250ua 75% v cc v ioh= - 162 ua 90% v cc v ioh= - 73 ua iil logic 0 input current port 0,1,2,3,4,5 - 75 ua vin= 0.45v itl logical transition current port 0,1,2,3,4,5 - 650 ua vi n= 2.0v ili input leakage current port 0,1,2,3,4,5 10 ua 0.45v s m59 r02g1 8 - bit micro - controller 8kb with isp fl ash & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 61 57 ver. g sm59 r 02g1 0 9 /20 1 5 t a = - 40 to 85 , v cc = 3.0v symbol parameter valid min max units conditions vil1 input low - voltage port 0,1,2,3,4,5 - 0.5 0.8 v vcc=3.0v vil2 input low - voltage res, xtal1 0 0.8 v vih1 input high - voltage port 0,1,2,3,4,5 2.0 v cc + 0.5 v vih2 input high - voltage res, xtal1 70%vcc v cc + 0.5 v vol output low - voltage port 0,1,2,3,4,5 0.4 v iol= 3.2 ma vcc =3.0v voh1 output high - voltage using strong pull - up (1) port 0,1,2,3,4,5 90% v cc v ioh= - 2.3 ma voh2 output high - voltage using weak pull - up (2) port 0,1,2,3,4,5 2.4 v ioh= - 77 ua 90% v cc v ioh= - 33 ua iil logic 0 input current port 0,1,2,3,4,5 - 75 ua vin= 0.45v itl logical transition current port 0,1,2,3,4,5 - 650 ua vin=1.5v ili input leakage current port 0,1,2,3,4,5 10 ua 0.45v

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