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act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 1 power loss protection with 6a efuse features ? optimized for low voltage applications ? 2.6-to-7v operating input range ? 8v max input blocking voltage ? adjustable in-rush current control ? configurable input power failure level ? programmable up to 6a input current limit ? programmable 5v to 28v boost storage volt- age ? 28v@4a synchronous buck supports 100% duty cycle ? programmable up to 2.25mhz buck operating frequency for small inductor size ? power loss, vout power good, and storage cap power good indicators ? compatible with different types of storage caps: super caps, electrolytic, tantalum, poscap etc. ? autonomous health monitoring for detection of earlier storage capacitor failures ? configurable interrupts to inform host for any faults/status change ? efuse, boost, and buck uv/ov/oc protection ? thermal alert and protection ? thermal enhanced fcq fn 4x4-32 package applications ? solid state drives ? power backup systems ? industrial applications ? efuse ? hot plug devices general description the act4921 device is a highly integrated power loss protection ic. it provides backup storage power in the event of an input power failure. a built-in boost converter provides high voltage energy storage to minimize storage capacitor size requirements. the built-in buck converter regulates the storage voltage to a fixed output voltage. it contains internal, back-to- back efuse fets to provide bi-directional input to output isolation. the ic also provides hot swap and inrush current control. the act4921 is very flexible and can easily be configured with i 2 c and external components. it features programmable storage capacitor voltage to optimize the storage capacitor sizing and system run time. the internal health monitoring provide an extra layer of protection and improve system reliability and early capacitor failure notification. it automatically checks the storage capacitor health and notifies the user when the energy in the storage caps is not sufficient for backup power. the built-in synchronous buck converter maximizes energy transfer from the storage caps to the system. act4921 provides an i 2 c bus interface to allow mcu control and monitoring. there are supervisor monitors for the input voltage, output voltage, and storage voltage. it is available with the thermal enhanced qfn 4x4 32 pin package. 28v buck/boost controller caps health monitor/ adc input?2.6v\7v blocking?up?to?8v 2.6v\6v 5v-28v 40m? fet 25m? fet pmu system core/flash 5v-28v efuse 20m? inrush controller blocking fet
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 2 functional block diagram vref vout vin enb hsb bset sw str fb comp iset fet?controller bu ck/boost? controller ss nirq pg_str ref agnd main controller vins pgnd health? monitor q ls_boost q hs q ls_buck ov uv q efuse1 q efuse2 pli sda q block vb pg_vo en scl disch
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 3 ordering information part number input voltage storage voltage fsw bst_clim buck current limit package ACT4921QI301-T 3.3v 28v 1.125mhz 950ma 6a fcqfn4x4-32 act4921qixxx-t cmi option pin count package code product number tape and reel note 1: standard product options are identified in this table. contact factory for custom options, minimum order quantity req uired. note 2: all active-semi components are rohs compliant and with pb-free plating unless specified differently. the term pb-free means semiconductor products that are in compliance with current rohs (restriction of hazardous substances) standards. note 3: package code designator q represents qfn note 4: pin count designator i represents 32 pins
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 4 pin configuration ?? ?? iset sw nirq ref fb vout vout sw pg_str pgnd pg_vo sda pli comp vout pgnd scl vin vin vin en ss agnd 4 3 2 1 7 6 5 11 15 17 18 19 pgnd 20 21 12 13 14 disch 8 16 ?? vins agnd enb vb str hsb bset 22 23 32 31 29 30 28 24 exposed? pad 27 25 26 10 9 33 34 35 sw vb vout figure 1: pin configuration C top view C qfn4x4-32
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 5 pin descriptions pin name description 1 hsb high side bias, boot-strap pin. this provides power to the inte rnal high-side mosfet gate driver circuitry. co nnect a 47nf capacitor from hsb pin to sw pin 2 str storage capacitor input. connect the storage capacitors to str. str requires a minimum capacitor of 100f to pgnd. 3 pg_str power good indicator open-drain output for storage capacitor. s torage capacitor voltage is good when high, and pu lls low when the storage volta ge falls below 95% of the nominal voltage setting or when buck and boost circuits are disabled. this pin is referenced to agnd 4 pli power loss indicator open-drain output for vin. pli goes high w hen the efuse is turned on and goes low when the ic enters supplement mode. pli is referenced to agnd. 5 pg_vo power good indicator open-drain for vout. pg_vo goes high when the efuse is fully turned on, and pulls low when the fb voltage falls below 95% of v fb_ref in supplement mode. pg_vo is referenced to agnd 6 fb output voltage feedback. kelvin connect fb to the output c apacitor. 7 comp compensation input pin for the buck converter. 8 ref internal bias voltage output. connect a 1f capacitor bet ween ref and agnd. 9,10,29 pgnd power ground. connect to large ground plane on pcb 11 scl i 2 c clock input. needs an external pull up resistor. 12 sda i 2 c data input and output. needs an external pull up resistor. 13 nirq interrupt open-drain output. nirq goes low to indicate a fault condition. nirq is referenced to agnd. 14 enb boost circuit & blocking fet enable signal. pulled high interna lly. when it is pulled to agnd, boost and buck circuit is disabled, and blocking fet i s off. 15,16 agnd analo g ground. kelvin connect agnd to the pgnd plane. 17 en enable input. this is a digita l enable signal f or the ic. pulle d high internally. when high, the efuse turn on. when it is pulled to agnd, efuse turns off, the ic goes into supplement mode, and stays in hiz mode after supplement mo de ends. 18 ss soft start input. place a capacitor from ss to vss to control t he efuse startup voltage slew rate. 19 bset sets the storage capacitors boosted output voltage. place a re sistor from bset to agnd to set the desired voltage. 20 iset input current limit pin. connect a resistor from iset to agnd t o set the current limit. iset can also be monitored to measure the efuse current. 21 vins input voltage sense for under voltage and over voltage faults. a dual comparator on vins measures the input voltage to determine if it is under, voltage, over voltage, or within normal operating limits. connect a resistive voltage divider to vins to set the uv and ov limits. the uv threshold is 0.64v. th e ov threshold is set by the ics specific cmi. vins is referenced to agnd 22,23,24 vin power supply input. input to the efuse. connect a 0.1f capacit or between vin and pgnd as close to the ic as possible. 25,26,27,35 vout output for by-pass mode, in-rush, and efuse functionality. conn ect vout to the system load. 28,34 vb buck circuit output and boost ci rcuit input pin. it is isolated from vout with the internal blocking fet. place the inductor between vb and sw.
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 6 30 disch storage cap discharge pin. connect a resistor between dischg an d str to quickly discharge the storage caps whenever device enters the p or/uv state or when user forces str to discharge by setting the dischg_str[ ] bit. 31,32,33 sw switching pin. this is the boost converter switch node and the buck converter switch node. connect the inductor to sw. exposed pad pgnd power ground. connect to large ground plane on pcb with therma l vias.
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 7 absolute maximum ratings parameter value unit fb, ss, iset, ref, sda, scl, en, bset, nirq, vins, pli, pg_str, pg_vo, enb to agnd. -0.3 to 6 v vin to agnd -0.3 to 8 v vout to pgnd -0.3 to 6 v hsb to sw -0.3 to 6 v sw to pgnd -0.3 to str+1 v str, dischg to pgnd -0.3 to 30 v agnd to pgnd -0.3 to + 0.3 v dischg 500 ma esd rating (human body model), all pins 2 kv junction to ambient thermal resistance, dependent on board layo ut (note 1) 27 c /w operating ambient temperature range (t a ) -40 to 105 c operating junction temperature (tj), (note 2) -40 to 125 c storage temperature -40 to 150 c lead temperature (soldering 10s) 300 c note1: measured on active-semi evaluation kit note2: do not exceed these limits to prevent damage to the devi ce. exposure to absolute maximum rating conditions for long per iods may affect device reliability.
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 8 system characteristics (vin = 5v, t a = 25c, unless otherwise specified) parameter conditions min typ max unit input supply input supply voltage range vin 2.6 7 v input supply over voltage lock out (ovlo) 6 v input under voltage lock out (uvlo) vin rising (boost/efuse ena bled) 2.55 2.6 v input uvlo hysteresis vin falling 50 mv input operation current efuse enabled and soft start completed buck/storage regulator disabled storage health check disabled 3 ma efuse enabled and soft start completed buck/storage regulator disabled storage health check disabled 5.5 ma input current (shutdown) v en = 0v 20 a input under voltage lock out (uvlo) vin rising (boost/efuse ena bled) 2.55 2.6 v input current (shutdown) v en =0v 20 a thermal thermal warning sets nirq 120 c thermal shutdown C disables buck and boost 145 c thermal shutdown C disables efuse 155 c thermal comparators hysteresis 10 c set thresholds bset reference normal operation range, otherwise uses default boost output regulation setting 0.32 1.2 v bset current source bset = 1.0v (25c) 19.6 20 20.4 a bset current source temperature coefficient bset = 1.0v (25c C 125c) 0.0145 %/c str thresholds input under voltage lock out (str_uvlo) str falling 2.7 2.78 v input under voltage lock out (str_uvlo) str rising 3.08 v open drain outputs open drain resistance (nirq, pli, pg_vo, pg_str, sda) sinking current 500a 100 ? vins thresholds under voltage reference (vins_uv_ref) uv ref after por release 0.64 v
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 9 programmable overvoltage reference range (ins_ov_ref) ov ref after por release 0.82 1.32 v validation detection vins uv falling or ov falling (delay disabled) 10 s validation detection vins uv falling or ov falling (delay disabled) 125 ms validation detection vins uv rising or ov rising 40 ns hysteresis for reference 20 mv
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 10 internal buck regulator (vin = 5v, t a = 25c, unless otherwise specified) parameter conditions min typ max unit operating input voltage range 3 28 v typical output voltage 3.3 v programmable output voltage range using external resistor divid er 1.8 6 v standby supply current v out = 103%, regulator enabled, no load, not switch- ing 300 450 600 a feedback voltage 0.8 v output voltage accuracy v out = 3.3v, i out = 2a (continuous pwm mode) -1% v nom 1% v output voltage accuracy v out = 3.3v, i out = 1ma (pfm mode) average ripple voltage -1% v nom 1% v line regulation v out = 3.3v v in_b1 = 5.5v to 12v, pwm regulation 0.02 %/v load regulation v out = 3.3v pwm regulation 0.04 %/a undervoltage threshold v out falling buck_uv_th = 00 buck_uv_th = 01 buck_uv_th = 10 buck_uv_th = 11 60 70 80 90 %v nom power good threshold (pg_vo) v out falling 95 %v nom power good hysteresis (pg_vo) v out rising 2 %v nom overvoltage fault threshold v out rising 107 110 112.5 %v nom overvoltage fault hysteresis v out falling 3 %v nom programmable switching frequency range v out > 20% v nom 562 khz 1125 1500 2250 current limit, cycle-by-cycle settings bkilim_opt = 0 bkilim_opt = 1 3 6 a current limit, cycle-by-cycle tolerance at default bkilim_opt -10 +10 % at other bkilim_opt set point -15 +15 % current limit, shutdown above bkilim_opt threhsold 40 % high side on-resistance i sw = -3a, v str = 5v 46 m? low side on-resistance i sw = 3a, v str = 5v 32 m? sw leakage current v str = 5v, v sw = 0 or 3.3v 1 a
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 11 internal efuse (vin = 5v, t a = 25c, unless otherwise specified) parameter conditions min typ max unit normal mode operating voltage range 2.6 7 v efuse on-resistance i sw = -2a, vin= 3.3v or 5v, t j = 25c 20 m? i sw = -2a, vin= 3.3v or 5v, t j = 100c 25 m? blocking fet on-resistance i out = 2a, vin= 3.3v or 5v, t j = 25c 30 m? i out = 2a, vin= 3.3v or 5v, t j = 100c 38 m? programmable efuse current limit range vin = 5v, configured using iset pin, triggers nirq pin 1 6 a efuse current limit accuracy -10 +10 % blocking fet current limit vout-vb > 560mv or at initial startup 300 ma vout-vb < 560mv except at initial startup 1800 iset monitor current ratio iset current divided by efuse curren t 1/20,000 efuse overcurrent detection deglitch 10 s efuse overcurrent current shutdown shuts down after deglitch ti me and stays off for off time 6 a current limit restart time 100 ms efuse soft start c ss = 10nf 5.94 6.6 7.26 mv/us en input low v io = 1.8v 0.58 v en input high v io = 1.8v 1.22 v
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 12 storage boost regulator (vin = 5v, t a = 25c, unless otherwise specified) parameter conditions min typ max unit storage boost converter operating input voltage range 2.7 36 v programmable output voltage range 5.0 28 v peak switching current bst _clim = 00 bst _clim = 01 bst _clim = 10 bst _clim = 11 250 500 950 1500 ma standby supply current v str = 103%, regulator enabled, not switching 25 35 a output voltage accuracy v str = 28v, i out = 15ma (continuous pwm mode) -3% v nom 3% v power good threshold v str rising 99.5 %v nom power good hysteresis v str falling 2 %v nom undervoltage fault threshold v str falling str_uv_th = 00 str_uv_th = 01 str_uv_th = 10 str_uv_th = 11 85 87.5 90 92.5 %v nom undervoltage fault hysteresis v str rising 2 %v nom overvoltage fault threshold v str rising 110 %v nom overvoltage fault hysteresis v str falling 3 %v nom start period c str = 1mf, v str = 28v 200 ms minimum on-time 50 ns maximum off-time 9.7 s low side fet on-resistance i sw = 325ma 300 m? dischg leakage current 1 a enb input low v io = 1.8v 0.58 v enb input high v io = 1.8v 1.22 v
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 13 health monitor (vin = 5v, t a = 25c, unless otherwise specified) parameter conditions min typ max unit health monitor str operating voltage range 4.2 28 v sink current source 9 10 11 ma programmable health monitor current sink timer range 2 1280 ms programmable storage voltage threshold range configurable 0.2% steps 95 98 %
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 14 i 2 c interface electrical characteristics (vin = 5v, t a = 25c, unless otherwise specified.) parameter test conditions min typ max unit scl, sda input low v io = 1.8v 0.58 v scl, sda input high v io = 1.8v 1.22 v sda leakage current sda=5v 1 a sda output low i ol = 5ma 0.35 v scl clock frequency, f scl 1000 khz scl low period, t low 0.5 s scl high period, t high 0.26 s sda data setup time, t su 50 ns sda data hold time, t hd (note1) 0 ns start setup time, t st for start condition 260 ns stop setup time, t sp for stop condition 260 ns capacitance on scl or sda pin 10 pf sda rise time sda, t r device requirement 120 ns sda fall time sda, t f device requirement 120 ns note1: comply with i 2 c timings for 1mhz operation - fast mode plus. note2: no internal timeout for i 2 c operations, however, i 2 c communication state machine will be reset when entering uv/po r state. note3: this is an i 2 c system specification only. ris e and fall time of scl & sda no t controlled by the device. note4: device address is factory configurable to 7h1a, 7h3a, 7h5a. figure 2: i 2 c data transfer sda scl t st t su t hd t sp t scl start condition stop condition
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 15 functional description general act4921 provides protection, control, and supple- mental storage for power failure prevention systems. this functionality goes by many names: power loss protection (plp), power loss imminent (pli) and power failure protection (pfp). it provides a system with additional run time after a power failure to all the system to save critical data before shutting down. typi- cal applications include solid state disk drives (ssd) and servers. in normal operation when input power is good, the ic connects the input to the output through the efuse. this powers the system load from the sys- tem input power. if an input voltage fault occurs, the ic disconnects the input from the output and enters sup- plement mode, where output power comes from the high voltage storage capacitor power. the internal buck converter efficiently converts the storage voltage down to the regulated output voltage. all startup, storage ca- pacitor charging, and switching between normal and supplement mode operation is autonomous and does not require user intervention. during start up, the act4921 limits the output voltage dv/dt to minimize system level inrush currents. after softstart is complete, the ic charges the storage capac- itors with the internal boost converter. the ic automati- cally recharges the storage capacitors as needed. the ic contains extensive protection circuitry to protect against input voltage overvoltage and undervoltage, output voltage overload and short circuit, degraded stor- age capacitors, and thermal overload. the ic communicates with the host processor via i 2 c and gpios. the nirq pin indicates general faults which can be read by the host processor via i 2 c. a dedicated power failure pin, pli, automatically and immediately goes low to indicate a power loss condition. this gives the system advanced warning to complete all active tasks and shutdown. see the pin function section for additional pli pin functionality. the act4921 is highly flexible and contains many i 2 c configurable functions. the ics default functionality is defined by its default cmi (code matrix index), but much of this functionality can be changed via i 2 c. i 2 c functionality includes storage voltage setting, ov and uv fault thresholds, switching frequencies, pli pin func- tionality, health check settings, and current limits. the cmi options section shows the default settings for each available cmi option. contact sales@active-semi.com for additional information about other configurations. i 2 c serial interface to ensure compatibility with a wide range of systems, the act4921 uses standard i 2 c commands. it supports clock speeds up to 1mhz. the act4921 always oper- ates as a slave device, and can be factory configured to one of three 7-bit slave addresses. the 7-bit slave ad- dress is followed by an eighth bit, which indicates whether the transaction is a read-operation or a write- operation. refer to each specific cmi for the ics slave address 7-bit slave address 8-bit write address 8-bit read address 0x1ah 001 1010b 0x34h 0x35h 0x3ah 011 1010b 0x74h 0x75h 0x5ah 101 1010b 0xb4h 0xb5h the i 2 c packet processing state machine does not have a timeout function, however, any time the i 2 c state ma- chine receives a start bit command, it immediately re- sets the packet processing, even if it is in the middle of a valid packet. the i 2 c functionality is operational in all states except reset. i 2 c commands are communicated using the scl and sda pins. scl is the i 2 c serial clock input. sda is the data input and output. sda is open drain and must have a pull-up resistor. signals on these pins must meet timing requirements in the electrical characteristics table. for more information regarding the i 2 c 2-wire serial interface, refer to the nxp website: http://www.nxp.com . i 2 c registers the act4921 contains an array of internal registers that contain the ics basic instructions for setting up the ic configuration, output voltages, sequencing, fault thresholds, fault masks, etc. these registers are what give the ic its operating flexibility. the two types of registers are described below. basic volatile C these are r/w (read and write) and ro (read only). after the ic is powered, the user can modify the r/w register values to change ic functionality. changes in functionality include things like masking certain faults. the ro registers communicate ic status such as fault conditions. any changes to these registers are lost when power is recycled. the default values are fixed and cannot be changed by the factory or the end user.
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 16 basic non-volatile C these are r/w and ro. after the ic is powered, the user can modify the r/w register values to change ic functionality. changes in functionality include things like output voltage settings, startup delay time, and current limit thresholds. any changes to these registers are lost when power is recycled. the default values can be modified at the factory to optimize ic fun ctionality for specific applications. please consult sales@active-semi.com for custom options and minimum order quantities. when modifying only certain bits within a register, take care to not inadvertently change other bits. inadvertently changing register contents can lead to unexpected device behavior. state machine act4921 contains an internal state machine with seven internal states: uv/por, soft-start, normal, health check, supplement, supplement- disable, and shutdown. uv/por state the ic enters the uv/por state on power up. it also enters uv/por from supplement state in the following conditions: 1. when the input voltage drops below the vins_uv threshold. 2. when the storage capacitor voltage drops below 3.0v. 3. when the buck converter output voltage goes ov or uv. the user may force the ic into uv/por by writing a 1 into the force_pwroff bit, register 0x06h, bit 0. when entering uv/por from power up, all registers reset to their default state. the registers retain their existing values when the ic enters from supplement state or from shutdown efuse. the ic transitions from the uv/por state to the soft-start state when en pin is high, the input voltage is above uvlo, the vins pin is above 0.64v, and the startup delay softstart timer has timed out. the delay timer is set by i 2 c register en_startdly[3:1] in register 0x0bh. table 1 shows the allowable delay times. 1ms is typically an acceptable delay time, but longer times can be programmed if the input voltage source rises extremely slowly. table 1: softstart delay en_startdly[3:1] startup delay time 000 not valid 001 1ms 010 5ms 011 10ms 100 20ms 101 40ms 110 80ms 111 125ms softstart state in the softstart state, the ic slowly turns on the efuse to minimize inrush currents. the ss pin directly controls the maximum output voltage dv/dt. the ic stays in the softstart state until vin-vout < 200mv and a 1ms timer times out. pg_vo goes high when the ic exits the softstart state. normal state the normal state is the normal operating state. the efuse is fully on, vout = vin, and the ic provides full operating current. when the ic transitions from the softstart state to the normal state, the pg_vo pin immediately goes high and the ic starts charging the storage capacitors if enb is pulled high. health check state the health check state can be considered a sub- state of the normal state. the ic operates identical to the normal state with the addition of activating the circuitry that check the storage capacitor health. the ic automatically enters health state every four minutes. the user may also manually enter this state by writing a 1 into the force_hlthchk bit which is bit 1 in register 0x06h. this bit automatically resets to 0 after the health check routine completes. the ic automatically exits health check and enters supplement state in a fault condition.
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 17 supplement state the ic enters supplement state when it detects a fault condition. it opens the efuse to bi-directionally disconnect the input from the output. it automatically turn on the buck converter to power the output from the storage capacitors. the following five conditions move the ic into supplement state. 1. vins voltage below uv threshold 2. vins voltage above the ov threshold 3. input voltage above the ov threshold 4. efuse current above the oc threshold 5. vin C vout > 300mv supplement-disable state in the supplement-disable state, vout is good and can power the system, but the ic cannot transition to the supplement state. while in this state, the open drain output pg_str status at low. in typical startup sequence, when the act4921 exits the softstart state, it transitions though the normal state directly to supplement-disable state. while ic is in supplement-disable state, the blocking fet gets turned on by the enb pin or the en_bfet bit in register 0x06h. the blocking fet sources 300ma constant current to charge the storage caps to vin. then the boost converter turns on to charge the storage caps to their final voltage. when the storage capacitor is fully charged, the act4921 exits supplement-disable state and moves to normal state. the transition of pg_ str pin from low to high indicates that the ic transiti oned to the normal state. the act4921 checks the following conditions to make sure the operating conditions and external components are within speck and working properly so the ic is capable of entering supplement state to provide backup power. if the ic is operating in the normal state and one of the following becomes invalid, the ic notifies the system by pulling nirq low and then enters the supplement-disable state. 1. vout-vb < 200mv 2. die temperature <145c 3. ldo (ref) is valid 4. bootstrap capacitor at hsb pin properly connected 5. the buck compensation is present and not shorted. shutdown state shutdown disables all ic functionality to protect against extreme over temperature conditions above 155c. this includes shutting off the efuse. i 2 c functionality not available in this state. the ic transitions to soft-start when the junction temperature drops and there is no overcurrent fault. the following figures and tables help describe the act4921 states and functionality in different situations. figure 3 shows the act4921 state diagram. table 1 shows which functions are enabled in each state. table 2 shows how different operating conditions and faults affect different ic functionality. note that the current operating state can be determined by reading the i 2 c register bits current_state in register 0x00h.
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 18 uv/por efuse? soft\start? vin?\?vout??155c vin?>?uvlo efuse?not?in?oc &?t j ??155c str??135?c or?ldo?uv or?storage?cap?ov or?boot?cap?fail normal?mode health? check storage?cap??300mv vins?uv t j ?>?155c str?>?pg_thr &t j ? act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 19 table 3: ic functionality vs operating conditions. operation conditions efuse blocking fet boost buck pli pg_vo pg_str nirq ic action normal operation on on enabled off high high high high boost charges str cap as needed input oc vin - vout < 560mv on on enabled off high high high low efuse in ldo mode input oc vin - vout > 560mv on off off off on low low high low low enter supplement mode vbus short on off on off on low low high low low enter supplement mode input over voltage on off on off on low high high low low enter supplement mode input under voltage on off on off on low high high low low enter supplement mode en pin low (@ start up) off off off off low low low low ic is disabled en pin low (@ normal operation) on off off off on low low high low low enter supplement mode first, then ic is disabled enb pin low on off off off no effect no effect depends on vstr low disables boost & buck, turns off blocking fet health checking on on off off high high high high if failed, ps_str and nirq go low 120c < tj < 145 c on on enabled off high high high low sends out thermal alert 145 c < tj < 155 c on on off off high high depends on vstr low pg_stg depends on vstr tj > 155 c off off off off low low low low ic is disabled
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 20 vin vout vstr pli nirq en_uv buck_uv soft?start boost?on supplement? mode 10ms? delay 9ms?delay vb figure 4: ope ration state pin functions vin vin is the input the efuse. connect a 0.1uf ceramic capacitor between vin and pgnd. vin is directly connected to vout in normal operation. the efuse disconnects vin from vout when the ic enters supplement mode. en the en pin provides a digital input to turn the ic on or off. when en is low when input power is applied, the ic remains disabled. pulling en high moves the ic into the softstart state. when en is pulled low while input power is valid, the ic immediately enters supplement mode. after the storage capacitor is depleted, the ic is disabled. vins the vins pin provides both overvoltage and undervoltage protection thresholds. the vins pin contains two precision comparators with hysteresis. it can be directly driven from a digital input to turn the efuse on and off. the en pin is typically used with a resistor divider from vin to agnd to program an efuse startup voltage higher than the ics uvlo value. the efuse turns on when the input en is high and the vins voltage goes above the vins_uv_ref threshold. once the efuse is on, it turns off and enters supplement mode if the vins pin goes above the vins_ov_ref threshold or below the vins_uv_ref threshold. the vins pin should not be left floating. it can be driven from standard logic signals greater than vins_uv_ref. it can also be driven with open-drain logic to provide. when driving it with an open-drain, ensure that the pullup voltage is not higher than the vins_ov_ref setting. vins_uv_ref is fixed at 0.64v. however, the vins_ov_ref can be programmed by i 2 c bits vins_ov_ref [2:0]. th e default vins_ov_ref voltage is set by the ics cmi.
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 21 table 4: over voltage reference settings vins_ov_ref[2:0] ov threshold (v) 000 disabled 001 0.82 010 0.92 011 1.00 100 1.08 101 1.16 110 1.24 111 1.32 enb the enb pin enables the blocking fet, the buck converter, and the boost converter. they are disabled when enb is low and enabled when enb is high. enb provides two main system level functions. the first is to isolate the storage capacitors as startup to allow faster system startup. enb is typically held low by the system processor at startup. after the system starts up, the processor pulls enb high to allow the boost converter to charge the storage caps. the second function is to provide fault isolation. in the event of a storage capacitor failure, enb can be pulled low to isolate the capacitors from the system. this allows the system to continue operating until it can be safely shutdown. str str is the output to the storage capacitor bank. in normal operation the internal boost converter charges the storage capacitors through the str pin. when the ic enters supplement mode, the internal buck converter uses the str pin as its input to power the system. the str pin is typically connected to hundreds of microfarads of storage capacitance. it always requires a 22uf or greater ceramic capacitor. see the buck converter section for more information. nirqinterrupt act4921 has an interrupt pin to inform the host of any fault conditions. in general, any ic function with a status bit asserts nirq pin low if the status changes. the status changes can be masked by setting their corresponding register bits. if nirq is asserted low, the fault must be read before the ic deasserts nirq. if the fault remains after reading the status bits, nirq remains asserted. the status changes shown below assert the nirq pin: ? input overvoltage, undervoltage ? thermal warning, thermal shutdown ? efuse vin to vout over limits ? efuse current warning and limit ? vb pin is not valid (vb or str short) ? storage capacitor overvoltage, undervoltage ? supplemental mode active ? buck operation faults ? buck undervoltage shutdown ? ref ldo undervoltage nirq is an open-drain output and should be pulled up to an appropriate supply voltage with a 10k? or greater pull-up resistor. scl, sda scl and sda are the i 2 c clock and data pins to the ic they have standard i 2 c functionality. they are open- drain outputs and each require a pull-up resistor. the pull-up resistor is typically tied to the systems up io pins. the pullup voltage can range from 1.8v to 5.0v. ref the ref pin is an internal bias voltage output pin. connect a 1f capacitor between ref and agnd. do not apply an external load to the ref pin. bset bset sets the boost converter output voltage. the output voltage is a function of both a resistor connected between bset and agnd as well as internal i 2 c register settings. see the storage boost converter section for more information. iset iset sets the efuse current limit with a resistor connected to agnd. see the efuse section for more information. ss the ss pin uses a capacitor to agnd to control the efuse softstart timing. see the efuse section for more information. pgnd the pgnd pin is the buck and boost converters power ground. the internal fets connect directly to the pgnd pins. the power supply input and output capacitors should connect to the pgnd pins.
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 22 agnd the agnd pin is the ics analog ground pin. it is a quiet ground pin that is separate and isolated from the high power, high current carrying pgnd ground plane. connect the non-power components to agnd. agnd must be kelvin connected to the pgnd pin in a single location. comp comp is the output of a transconductance amplifier that is used to compensate the internal buck converter. the compensation components, which are typically a standard type-2 compensation should be grounded to the agnd pin. see the application section for more information on compensating the internal buck converter. pli pli (power loss indicator) goes high after softstart and stays high in normal operation. pli immediately goes low when the ic enters supplement mode. this setting is used to let the system up know that power loss is imminent. the pli pin is an open-drain output and is 5v compliant. fb the fb pin is used to regulate the buck converter output voltage when the ic i s in supplement mode. hsb hsb provides power to the internal high-side mosfet gate driver circuitry. connect a 47nf capacitor from hsb pin to sw pin. sw sw is the switch node for the internal buck and boost converters. connect the inductor to the sw pin. vout vout is the output of the efuse and connects to the system load. the efuse connects vout to vin in normal operation, and it disconnects it in supplement mode. vb vb is the output pin from the blocking fet. depending on the operating mode, power either flows into or out of vb. in normal operation, power flows from vin, through the efuse and blocking fets and out of vb to provide input power to the boost converter. enb must be pulled high to enable this functionality. during supplement mode, the buck converter output power flows into vb, through the blocking fet, and out of vout to the system. dischg dischg is the discharge pin for the storage capacitors. when the ic enters the uv/por state, dischg is internally connected to pgnd through an internal fet. connect a resistor between dischg and str to quickly discharge the storage capacitance. the user can manually turn on the dischg fet by setting the dischg_str bit to 1. the discharge function is typically only used during product development and evaluation. it allows the user to quickly discharge large storage capacitor values between testing to ensure the next power cycle starts with discharged capacitors. if the function is not used in production, the discharge resistor can be removed from the board and the dischg pin can be connected to pgnd or left open. the discharge resistor should be chosen to keep the discharge current less than 100ma. pg_str pg_str is a power good indicator for the storage capacitors. it goes high when the storage capacitor voltage goes into regulati on. it goes low when the voltage drops below 95% of the setpoint. it also goes low when either the buck or boost converter is disabled. it is open drain and is 5v compliant. pg_vo pg_vo is a power good indicator for vout. it goes high when the efuse is fully turned on. in supplement mode, it starts high and then goes low when the fb pin drops below 95% of v fb_ref (0.8v). it is open drain and is 5v compliant. general description efuse the act4921 efuse is an electronic fuse that disconnects the input from the output. it has considerable advantages over mechanical fuses because it has adjustable current thresholds and it resets after the fault condition is gone. the efuse consists of two back-to-back mosfets to provide bi- directional protection. this provides protection against both input and output short circuit conditions by preventing current flow in both directions. hot swap functionality is provided by the efuse softstart function and current limiting circuitry. this prevents large inrush
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 23 currents from pulling down the input voltage. the efuse also provides protection against high input voltage transients up to 7v by opening when the input voltage goes above the programmed threshold. the efuse turns off in the following conditions. 1. vins voltage below uv threshold 2. vins voltage above the ov threshold 3. input voltage above the ov threshold 4. efuse current above the oc threshold 5. vin C vout > 300mv blocking fet the blocking fet is an internal mosfet that provides isolation between the system output voltage (vout) and the storage capacitors. it provides system level fault tolerance that allows the system to continue operating normally in the event of a storage capacitor failure. during the blocking fet softstart, it provides 300ma constant current. the blocking fet stays in softstart until the voltage across it (vout-vb) approaches 0v. after softstart is complete, the blocking fet turns on fully, and has a 1.8a current limit setting. the blocking fet enters softstart again when vout- vb < 560mv. during startup, the 300ma constant current source linearly charges up the storage capacitors. if the storage capacitors are not charged up to vin within 1s, the blocking fet turns off for 1s and then retries. with extremely large storage capacitors such as supercapacitors, the blocking fet will turn on and off at a 2s period. this is expected functionality and minimizes the power dissipation in the ic. in normal operation, when the blocking fet is fully turned on, it applies power to the boost converter, allowing the storage capacitors to charge up to their final value. when the ic enters supplement mode, the buck output power flows into the vb pin, through the blocking fet, and out of vout to the system. the blocking fet limits a storage capacitor overload condition to 1.8a. this causes the voltage at vb to drop, generates a vb undervoltage fault, and the ic pulls nirq low. if vb voltage drops below vout- 560mv, the current limit drops from 1.8a to 300ma. during this condition, the efuse stays on and system continues to operate normally. if the overload condition remains for longer than 1s, the blocking fet enters a hiccup mode where it turns on and off for a 2s period. hiccup mode applies to both normal startup with very large storage capacitors and to short circuit conditions. note that the ic enters the supplement-disable state during both startup and short circuit conditions. the blocking fet can be manually turned on and off by the enb pin or the en_bfet bit in register 0x06h. when register en_enb_reg = 0, the enb pin controls the blocking fet. pulling enb low turns it off and pulling enb high turns it on. when register en_enb_reg = 1, the en_bfet bit pin controls the blocking fet. setting en_bf et = 0 turns it off and setting en_bfet high turns it on. note that disabling the blocking fet also disables the boost converter. this allows systems to startup faster by keeping the boost disabl ed until the system is up and running. current limit setting a resistor connected between the iset pin and vss programs the act4921 efuse maximum dc current limits. the input current limit is linearly proportional to the resistor value on the iset pin. the following equation calculates the correct resistor value to get the desired current limit threshold. equation 1 where r ilim is the current limit resistor in ohms and i ilim is the desired current limit threshold in amperes. figure 5 shows the current limit setting vs r ilim value. note that the maximum allowable efuse current limit setting is 6a, which corresponds to a 3.32kohm resistor. figure 5: current limit threshold vs r ilim
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 24 note that the efuse current can be measured using the ilim pin. if efuse current is measured via the ilim pin, the measurement circuit must have a high impedance input to minimize errors. the current flowing out of ilim is 1/20000 of the current through the efuse. the following equation calculates the efuse current when measured via the ilim pin. ? equation 2 where r ilim is the current limit resistor in ohms and v ilim is the voltage measured on the ilim pin in volts. when the efuse reaches the current limit threshold, it clamps the output current. if the load tries to draw additional current, the efuse opens. soft-start the ss pin controls the efuse start-up. the ss pin drives a constant 5a internal current source into the external soft-start capacitor to provide a linear ramping voltage at the ss pin. the output voltage linearly ramps with the ss pin voltage, resulting in a well-controlled linear softstart ramp on vout, regardless of the load conditions. the following equation calculates the required soft-start capacitance. equation 3 where the t ss is the soft-start time in ms and v out is the output voltage. the softstart current must be less than 90% of the programmed efuse current limit. if the softstart current is greater than 90% of the efuse current limit, the ic enters the shutdown state, turns off the efuse, and then retries to softstart again. the following equation calculates the minimum allowable softstart time. _ ? .? equation 4 where c out is the sum of the output capacitance and storage capacitance in mf, v out is the output voltage in volts, and i ilim is the efuse current limit in amperes programmed by the ilim resistor. buck converter general description the act4921 contains current-mode, synchronous pwm step-down converter that achieves peak efficiencies of 95%. the buck converter minimizes noise in sensitive applications and allows the use of small external components. it is highly flexible with external component selection and can be reconfigured via i 2 c registers. external components set the output voltage and compensation while i 2 c registers set the switching frequency and current limit. the buck converter operates in fixed frequency pwm mode. its switching frequency is programmable between 562khz to 2250 khz via the i 2 c register bk_freq[1:0] which allows the system to be optimized for different applications. it has two peak current limit options of 6a and 10a allowing for further system optimization. overcurrent is set by a non- i 2 c bit bkilim_opt in register 0x0eh. refer to the cmi section at the back of the datasheet for each ics specific setting. the buck output voltage is externally programmable between 1.8v and 6v. the buck converter generates a regulated output voltage at the vb pin from the storage capacitors when the ic enters supplement mode. this provides the backup power when the system experiences fault conditions. note that the buck output voltage goes into the vb pin, through the blocking fet and out of the vout pin to the system. after the ic exits the softstart state, the buck converter is enabled but remains turned off. it automatically turns on when the ic enters supplement mode, and remains on until the storage capacitors discharge to 3.0v. note that enb must be pulled high to enable the buck converter. most systems wait until the system is up and running before enabling the buck and boost with the enb pin. frequency setting higher switching frequencies result in smaller solution sizes at the cost of slightly lower efficiency. lower switching frequencies result in larger solution sizes with higher efficiency. the following table gives the maximum allowable switching frequency as a function of storage voltage.
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 25 table 5: maximum allowable buck switching frequency storage voltage maximum buck switching frequency < 18v 2.25mhz 18v to 25v 1.5mhz > 25v to 28v 1.125mhz output voltage setting the buck converter output voltage is programmed by an external resistor divider connected between the vb pin and agnd, with the center tap connected to the fb pin. the buck output voltage can be set above, below, or equal to the input voltage supplement threshold. when the input voltage goes outside the normal operating voltage set by the vins pin, the ic enters supplement mode and regulates the output voltage to the programmed buck voltage. although the buck converter immediately starts up when the ic enters supplement mode, the output voltage still has a small, but finite drop in output voltage between the time the efuse turns off and the buck converter is fully on. this voltage drop should be considered when setting the output voltage. the following equation calculates the correct resistor values to set the desired output voltage. 1 r2 ? 1 equation 5 where r1 is the top feedback resistor, r2 is the bottom feedback resistor, v buck is the desired output voltage, and v fb is the fixed 0.8v reference voltage on the fb pin. choose r2 in the range of 10kohm. smaller resistor values are acceptable, but larger values will affect voltage accuracy due to bias currents into the fb pin. protection the buck converter has several protection mechanisms to insure safe operation. it stops operation when input voltage from storage cap drops below str_uvlo (3.0v) or when the output voltage drops below the power good threshold which is fixed at 93% of the output setpoint. note that the output undervoltage protection is masked by default, but can be unmasked by the i 2 c register bit mask_bk_uv reg0x11 [0]. the buck converter provides overcurrent and short circuit protection. overcurrent protection is achieved with cycle-by-cycle current limiting. the peak current threshold is set to either 6a or 10a by bkilim_opt. if the peak current reaches the programmed threshold, the ic turns off the power fet. this condition typically results in shutdown due to an output voltage uv condition due to the shortened switching cycle. a short circuit condition that results in the peak switch current being 122.5% of bkilim_opt immediately shuts down the supply and asserts nirq low. a buck overcurrent, undervoltage, or overvoltage condition moves the ic into the uv/por state. compensation the buck regulator ut ilizes type 2 external compensation placed on the comp pin. contact the factory for compensation details. input capacitor selection the str pin is the input voltage to the buck converter. it requires a dedicated high quality, low-esr, ceramic input capacitor that is optimally placed to minimize the power routing. for optimal pcb layout considerations, 1206 or 1210 sized input capacitors are recommended. a 22uf capacitor is typically suitable, but the actual value is application dependent. the input capacitor can be increased without limit. choose the input capacitor value to keep the input voltage ripple less than 50mv ? ? ? equation 6 where iout is the maximum efuse load current in amperes, v str is the maximum storage voltage, v buck is the buck output voltage, f sw is the switching frequency, and v ripple is the maximum allowable ripple voltage on the input of the buck converter. note that the storage capacitor values should not be considered when calculating the input voltage ripple because they are not typically designed for high frequency functionality. be sure to consider the input capacitors dc bias effects. a capacitors actual capacitance is strongly affected by its dc bias characteristic s. the input capacitor is typically an x5r, x7r, or similar dielectric. use of y5u, z5u, or similar dielectrics is not recommended. input capacitor placement is critical for proper operation. the bucks input capacitor must be placed as close to the ic as possible. the traces from str to the capacitor and from the capacitor to pgnd should as short and wide as possible.
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 26 inductor selection the buck regulator utilizes current-mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over their full operating range. the act4921 is optimized for operation with 1uh to 3.3uh inductors. choose an inductor with a low dc-resistance, and avoid inductor saturation by choosing inductors with dc ratings that exceed the maximum output current by at least 30%. due to the requirement for the buck converter to start up as quickly as possible, the inductor should be designed to give a maximum ripple current, i l , of 50% to 60% of the maximum output current. the following equation calculates the recommended inductor value. ? ?? equation 7 where l is the inductor value in h, v buck is the output voltage, v str is the maximum storage voltage, f sw is the switching frequency in hz, and i l is the desired ripple current in amperes. output capacitor selection the buck converter is designed to take advantage of the benefits of ceramic capacitors, namely small size and very-low esr. the buck converter is designed to operate with 44f output capacitor over most of its operating ranges, although more capacitance may be desired depending on the duty cycle and load step requirements. choose a ripple voltage that is approximately 1% of the output voltage setpoint. note that the output capacitance must be placed at the output of the buck converter. additional downstream capacitance will be placed at the loads, but this capacitance should not be considered when calculating the buck output capacitance. however, the downstream capacitance should be considered when compensating the power supply. the following equation calculates the output voltage ripple as a function of output capacitance. note that the worst case ripple voltage occurs at the beginning of supplement mode when the storage capacitors are fully charged. c out ? ? ? equation 8 where v ripple is the desired output ripple voltage, f sw is the switching frequency in hz, and i l is the maximum ripple current in amperes. as with the input capacitor selection, use x5r or x7r dielectrics and be sure to consider the capacitors dc bias effects. storage boost converter general description the act4921 contains an integrated peak current- mode, synchronous boost converter. it minimizes system level costs by using the same components as the buck converter. the peak current is adjustable between 250ma and 950ma, allowing for system optimization. the output voltage is adjustable between 5v and 28v via i 2 c registers and an external resistor. the peak current-mode control topology eliminates the need for compensation. the boost automatically charges up the storage capacitors from the input voltage so they are ready to provide backup power in the event of a system fault. startup the boost converter automatically starts when the ic exits the softstart state and the enb pin is pulled high. note that the ic exits the softstart state 10ms after the output voltage is within 200mv of the input voltage. most systems wait until the system is up and running before enabling the buck and boost with the enb pin. when the storage voltage reaches regulation, the boost enters standby mode and monitors the storage voltage. it automatically turns back on and tops off the storage capacitors when the storage voltage drops below 95% of the programmed voltage. the boost converter automatically turns off if it is topping off the storage capacitors when the ic enters supplement mode. the average input current when the boost charges the storage capacitors is approximately ? of the peak switching current. the peak switch current is programed by register bst_clim[1:0]. table 6: boost peak current settings bst_clim[1:0] (ma) 00 250 01 500 10 950 11 1500
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 27 operating mode the boost converter operates in peak current mode, non-fixed frequency mode. the power fet stays on until its current reaches programmed peak current. it then turns off until the inductor current drops to 0a, at which time it turns on again. storage capacitor voltage setting the buck converter output voltage is set by either the i 2 c register bstvset[4:0], or a combination the register and a resistor placed between the bset pin to vss. when using only the bstvset[4:0] leave the bset pin floating. table 6 shows the programmed storage voltage. the default value is determined by the ics specific cmi option. note that the ic accepts bstvset values between 11000 and 11111 and each of these values sets the boost voltage to 28v. table 7: storage capacitor voltage settings with bset pin open bstvset[3:0] bstvset[4] 0 1 0000 5v 21v 0001 5.6v 22v 0010 7v 23v 0011 8v 24v 0100 9v 25v 0101 10v 26v 0110 11v 27v 0111 12v 28v 1000 13v 28v 1001 14v 28v 1010 15v 28v 1011 16v 28v 1100 17v 28v 1101 18v 28v 1110 19v 28v 1111 20v 28v using both the bstvset[4:0] register and an external resistor provides additional output voltage resolution. in this configuration, the following equation calculates the output voltage. ? ? equation 8 where v bstvset is the voltage set by the bstvset register in table 6 and r bset is the resistor on the bset pin in ohms. as an example, to set the storage voltage to 12.8v when the default bstvset[4:0] = 10111, first look up the storage voltage when the bset pin is open per table 7. this sets v bstvset = 28v. using equation 8, setting r bset = 27.4k? sets v str = 12.8v. note that r bset should be set between 20k? and 60k?. setting r bset below 20k? gives the same result as using a 20k? resistor. setting r bset above 60k? gives the same result as using a 60k? resistor. using r bset outside the range is acceptable and does not damage the ic. input capacitor selection there are no special considerations for the boost converter input capacitor. the ic topology uses the buck converter output capacitor for the boost input capacitor. proper selection of the buck converter output capacitor automatically results in an acceptable boost converter input capacitor. output inductor selection there are no special considerations for the boost converter inductor. the ic topology uses the buck converter inductor for the boost converter inductor. proper selection of the buck converter output capacitor automatically results in an acceptable boost converter input capacitor. output capacitor selection the ic topology uses the buck converter input capacitor for the boost converter output capacitor. note that the storage capacitors are also included in the boost converter output capacitors. proper selection of the buck converter input capacitor typically results in an acceptable boost converter output capacitor. the boost output capacitor has two crite ria. the first is that it must consist of at least 10f of high quality x5r or x7r ceramic capacitance placed directly between the str pin and pgnd. the second criteria is that the sum of the ceramic capacitor and storage capacitors must be greater than 100f. there is no requirement for the additional capacitance dielectric material. this provides flexibility for the storage capacitors, which allows the use of super capacitors, electrolytic, polymer, tantalum, ceramic, or any capacitors in the design. output voltage uvlo setting the storage capacitor power good signal indicates that the str voltage is above the uvlo threshold. the uvlo threshold is shared with the storage capacitor
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 28 health check, and is set by the i 2 c register hmon_thr [3:0]. the default value is determined by the ics specific cmi option. table 8: storage capacitor pg threshold hmon_thr[2:0] hmon_thr[3] 0 1 000 95.0% 96.6% 001 95.2% 96.8% 010 95.4% 97.0% 011 95.6% 97.2% 100 95.8% 97.4% 101 96.0% 97.6% 110 96.2% 97.8% 111 96.4% 98.0% storage capacitor health monitor general description the act4921 has an internal health monitor for the storage capacitors. it applies a constant current sink to the capacitors and monitors the voltage drop. if the voltage drops below a predetermined threshold, the ic asserts nirq to indicate that the storage capacitance has dropped below the allowable threshold. health monitoring is completely autonomous, but can also be manually initiated by the system up. health monitoring can also be configured so that it is only a manual operation so it can be triggered on demand to avoid any critical system operations. the health monitor parameters are adjustable via i 2 c registers to allow flexibility for different capacitor values. health monitor algorithm the health check algorithm sinks 10ma into the str pin for a time determined by i 2 c register hmon_tset. it then sinks 50ma for 200us. it monitors the voltage on the str pin, and if the voltage drops more than the percentage set by i 2 c register hmon_thr, it asserts nirq low and sets the fault bit. the ics specific cmi option sets the default hmon_tset and hmon_thr settings. after the hmon_tset time, the boost turns back on to recharge the storage capacitor. the health check function can be enabled and disabled by the dis_health_chk bit 0x0bh [4]. it also can be forced to perform a one-shot health check by the force_hlthchk bit 0x06h [1]. forcing a single health check is valid even when the dis_health_chk bit = 1. if set in continuous mode, the ic performs a health check every 4 minutes. this timing can be configured for every 8 minutes or 16 minutes by bits scale_hchk _2x and scale_hchk _4x in register 0x10h [1:0]. the act4921 allows for very flexible health checking routines by allowing the system to manually enable the 10ma discharge current by setting the en_str10masink bit 0x06h [2] = 1. in this situation, the system manually turns the discharge current on and off. the storage capacitor voltage threshold is still determined by the hmon_thr register. this function is useful for checking extremely large capacitor values which need very long discharge times. pg_thr (programmable) v str initial charge health testing top-off maintain v 10ma 50ma i 200us pr og ra mm ab le discharge time pr ogramm able interval time t t 0 0 st ora ge c a p v ol tag e discharge current figure 6: storage voltage at different stages the register hmon_tset [3:0] sets the health check discharge time as shown in table 9. table 9: health check discharge time hmon_tset[2:0] hmon_tset[3] (ms) 0 1 000 2 384 001 4 512 010 8 640 011 16 768 100 32 896 101 64 1024 110 128 1152 111 256 1280 pc board layout guidance proper parts placement and pcb layout are critical to the operation of switching power supplies. follow the
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 29 following layout guidelines when designing the act4921 pcb. refer to the active-semi act4921 evaluation kit for layout guidance. place the buck input capacitors as close as possible to the ic. connect the input capacitors directly between str and pgnd pins on the top layer. routing these traces on the top layer eliminates the need for vias. 1. minimize the switch node trace length between the sw pin and the inductor. optimal switch node routing is to run the trace between the in- put capacitors pads. using 1206 or larger sized input capacitors is recommended. avoid routing sensitive analog signals near these high fre- quency, high dv/dt traces. 2. the buck output capacitors should be placed by the vout pin and connected directly to the vout pin and ground plane with short and wide traces. note that the buck output capacitors do not connect to the vb pin or inductor. the out- put capacitor ground should make a short con- nection to the input capacitor ground. if required, use multiple vias. 3. the fb pin should be kelvin connected to the output capacitor through the shortest possible route, while keeping sufficient distance from switching node to prevent noise injection. the ic regulates the output voltage to this kelvin connection. 4. connect the pgnd and agnd ground pins must be electrically connected together. the agnd ground plane should be isolated from the rest of the pcb power ground. 5. remember that all open drain outputs need pull-up resistors. 6. connect the exposed pad directly to the top layer ground plane. connect the top layer ground plane to both internal ground planes and the pcb backside ground plane with ther- mal vias. provide ground plane routing on mul- tiple layers to allow the ics heat to flow into the pcb and then spread radially from the ic. avoid cutting the ground planes or adding vias that re- strict the radial flow of heat. 7. the following components should be con- nected to the agnd plane. ss cap bset resistor iset resistor comp resistor and capacitors fb resistor vins resistor 8. the act4921 footprint should connect pins 31, 32, and 33 on the top layer. it should connect pins 28 and 29 on the top layer. it should con- nect pins 25, 26, 27, and 35 on the top layer. it should connect pins 9 and 10 to the exposed pad on the top layer. refer to the evaluation kit layout for
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 30 typical operating characteristics
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 31
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 32
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 33
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 34 cmi options this section provides the basic default configuration settings for each available act4921 cmi option. cmi 301: act4921qi301 cmi 301 is designed for standard 3.3v input applications. cmi 3 01 default settings are appropriate for most typical applications. it operates with a buck switching frequency of 1. 125mhz to provide an optimal tradeoff between overall size and efficiency. table 10 shows the default register settin gs. table 10: cmi 301 default register settings function value register register settings storage voltage 28v 0x0dh bst_vset[4:0] = 10111 boost current limit 950ma 0x0dh bst_clim[1:0] = 10 buck switching frequency 1125khz 0x10h bk_freq[1:0] = 01 buck peak current limit 6a 0x0fh bkilim_opt = 1 buck undervoltage threshold 80% 0x0fh bkuv[1:0] = 10 input voltage overvoltage reference 0.82v 0x0eh vins_ov_ref[2:0 ] = 001 health monitor time 32ms 0x0bh hmon_tset[3:0] = 0100 health monitor threshold 95% 0x0ch hmon_thr[3:0] = 0000 startup delay 1ms 0x0ch en_startdly[2:0] = 001 latch supplement mode yes 0x0ch en_latch_splmnt = 1 blocking fet control pin enabled 0x0bh en_enb_reg = 0 7-bit i 2 c address 0x5ah n/a n/a cmi identification 0x00h 0x2ah cmi_id[7:0] = 0x00h i2c address the cmi 301 7-bit i2c address is 0x5ah. this results in 0xb4h f or a write address and 0xb5h for a read address. cmi identification the cmi 301 cmi identification (register 0x2ah) = 0x00h. this r egister can be used to distinguish between different cmi versions.
act4921qi rev 1.0, 18-jan-2018 innovative power tm www.active-semi.com activeswitcher tm is a trademark of active-semi copyright ? 2018 active -semi, inc. 35 package outline and dimensions qfn4x4-32 top view side v iew all dimensions are in millimeters dimensioning and tolerancing per jeded mo-232 see active semi application note an-104, qfn pcb layout guideli nes for more information on generating the act4921 land pattern.

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