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  differential lvcmos Datasheet PDF File

For differential lvcmos Found Datasheets File :: 3390    Search Time::1.172ms    
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    ICS87973I-147 87973DYI-147 87973DYI-147LF 87973DYI-147LFT 87973DYI-147T

Integrated Device Technology
Part No. ICS87973I-147 87973DYI-147 87973DYI-147LF 87973DYI-147LFT 87973DYI-147T
OCR Text ...e feedback, one sync Selectable differential CLK, nCLK inputs or lvcmos/LVTTL reference clock inputs CLK0, CLK1 can accept the following input levels: lvcmos or LVTTL CLK, nCLK pair can accept the following differential input levels: LVPECL...
Description LOW SKEW, 1-TO-12 lvcmos/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER

File Size 1,075.95K  /  19 Page

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    Motorola
Part No. MPC9456
OCR Text ...ffers 10 low-skew outputs and a differential LVPECL clock input. The outputs are configurable and support 1:1 and 1:2 output to input freque...lvcmos clock distribution buffer MPC9456 LOW VOLTAGE SINGLE OR DUAL SUPPLY 2.5V AND 3.3V LVCMO...
Description MPC9456 2.5V and 3.3V lvcmos Clock Fanout Buffer
2.5V and 3.3V lvcmos Clock Fanout Buffer

File Size 133.67K  /  12 Page

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    ICS
Part No. M2026
OCR Text ... Reference clock inputs support differential LVDS, LVPECL, as well as single-ended lvcmos, LVTTL Loss of Lock (LOL) output pin; Narrow Bandwidth control input (NBW pin) AutoSwitch (AUTO pin) - automatic (non-revertive) reference clock res...
Description SAW PLL for Frequency Translation with automatic reference clock reselection, Loss of Lock indicator, and Hitless Switching options

File Size 333.73K  /  12 Page

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    Motorola
Part No. MPC9239
OCR Text ...z to 900 MHz and the support of differential LVPECL output signals the device meets the needs of the most demanding clock applications. M...lvcmos compatible control inputs On-chip crystal oscillator for reference frequency generation Alter...
Description 900 MHz Low Voltage LVPECL Clock Synthesizer
900 MHz Low Voltage LVPECL Clock Syntheslzer

File Size 174.72K  /  12 Page

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    HD74SSTV16859TEL

Renesas Electronics Corporation
Part No. HD74SSTV16859TEL
OCR Text ...om D to QA, QB is controlled by differential clock pins (CLK, CLK) and the RESET. Data is triggered on the positive edge of the positive clo...lvcmos reset (RESET) input / SSTL_2 data (D) inputs and CLK input ) differential SSTL_2 (Stub series...
Description 1:2 13-bit SSTL_2 Registered Buffer

File Size 3,350.93K  /  11 Page

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    SSTUB32866EC/G SSTUB32866EC/S

NXP Semiconductors
Part No. SSTUB32866EC/G SSTUB32866EC/S
OCR Text ...correct parity error processing differential clock (CK and CK) inputs Supports lvcmos switching levels on the control and RESET inputs Single 1.8 V supply operation (1.7 V to 2.0 V) Available in 96-ball, 13.5 mm x 5.5 mm, 0.8 mm ball pitch ...
Description 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications

File Size 146.12K  /  29 Page

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