| |
|
 |
Pericom Technology
|
| Part No. |
PI6C2516A
|
| OCR Text |
...cations. ? zero input-to-output delay: distribute one clock input to four banks of four outputs, with separate output enables for each bank...locked loop (pll) clock driver, distributing high-frequency clock signals for sdram, server and netw... |
| Description |
Phase-Locked Loop Clock Driver with 16 Clock Outputs
|
| File Size |
297.91K /
7 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
Pericom Technology
|
| Part No. |
PI6C2502
|
| OCR Text |
...ck fb_in input, the propagation delay from the clk_in input to any clock output will be nearly zero. product features high-performance phase-locked-loop clock distribution for networking, synchronous dram modules for server/workstation/ p... |
| Description |
Phase-Locked Loop Clock Driver
|
| File Size |
367.25K /
6 Page |
View
it Online |
Download Datasheet |
| |
|
|
Unisonic Technologies Co., Ltd.
|
| Part No. |
9170-XXCS08LF
|
| OCR Text |
...ontinuous input clock with zero delay (1ns at 5v v dd ). using ics?s proprietary phase- locked loop (pll) ana-log cmos technology, the av9170 is useful for regenerating clocks in high speed systems where skew is a major concern. by the use... |
| Description |
107 MHz, OTHER CLOCK GENERATOR, PDSO8 0.150 INCH, ROHS COMPLIANT, SOIC-8
|
| File Size |
183.61K /
12 Page |
View
it Online |
Download Datasheet |
| |
|
|
Integrated Circuit System
|
| Part No. |
ICS1562B
|
| OCR Text |
...t-scaler. Reset of the pipeline delay on Brooktree RAMDAC s may be performed under register control. Outputs may also be set to desired stat...locked clock generation capability External feedback loop capability (-201 option only) Compact - 16... |
| Description |
User-programmable differential Output Graphics Clock Generator
|
| File Size |
331.67K /
20 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|
