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delay-locked Datasheet PDF File

For delay-locked Found Datasheets File :: 4344 Search Time::1.11ms
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				ETC
Part No.	BCM3520
OCR Text	...rap filter - Programmable group delay compensation filter - Analog Composite Video Baseband Signal (CVBS) output - FM demod output supports ...locked loops, referenced to a single external crystal. Chip configuration, channel acquisition, and ...
Description	CONNEC TV PLUG AND PLAY DTV RECEIVER
File Size	118.03K / 2 Page	View it Online	Download Datasheet

				ETC[ETC]
Part No.	QL8050 QL8150 QL8250 QL8025 QL8325
OCR Text	...ns with a single level of logic delay while other architectures require two or more levels of delay. 4XLFN/RJLF &RUSRUDWLRQ Prelimin...Locked Loops, please refer to QuickLogic Application Note 58. 3// 0RGHV RI 2SHUDWLRQ QuickLogic ...
Description	LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM
File Size	442.48K / 49 Page	View it Online	Download Datasheet

				ONSEMI[ON Semiconductor]
Part No.	74HC4046 MC74HC4046A MC74HC4046AD MC74HC4046ADR2 MC74HC4046AF MC74HC4046AFEL MC74HC4046AN MC74HC4046A-D
OCR Text	...L Parameter Maximum Propagation Delay, SIGIN/COMPIN to PC1OUT (Figure 1) Maximum Propagation Delay, SIGIN/COMPIN to PCPOUT (Figure 1) VCC Vo...locked, the output of phase comparator 2 will be disabled except for minor corrections at the leadin...
Description	Phase-Locked Loop High-Performance Silicon-Gate CMOS
File Size	290.10K / 16 Page	View it Online	Download Datasheet

				PHILIPS[Philips Semiconductors]
Part No.	74HC4059 74HC4059D 74HC4059N 74HC4059N3 74HCT4059 74HCT4059D 74HCT4059N 74HCT4059N3
OCR Text	...max CI CPD Notes propagation delay CP to Q maximum clock frequency input capacitance power dissipation capacitance per package CL = 15...locked-loop (PLL) for a FM band synthesizer. Calculating the minimum and maximum divide-by-n valu...
Description	Programmable divide-by-n counter
File Size	147.77K / 20 Page	View it Online	Download Datasheet

				PHILIPS[Philips Semiconductors]
Part No.	74HCT297 74HC297
OCR Text	...PHL/ tPLH PARAMETER propagation delay I/DCP to I/DOUT A1, B to XORPDOUT B, A2 to ECPDOUT fmax maximum clock frequency KCP I/DCP CI CPD Notes...locked-loop filter PIN DESCRIPTION PIN NO. 2, 1, 15, 14 3 4 5 6 7 8 9, 10, 13 11 12 16 SYMBOL A, B,...
Description	Digital phase-locked-loop filter
File Size	96.54K / 12 Page	View it Online	Download Datasheet

				Analog Devices, Inc. AD[Analog Devices]
Part No.	ADM6315
OCR Text	...RATURE COEFFICIENT VCC TO RESET DELAY RESET ACTIVE TIMEOUT PERIOD 1 20 140 1120 0.8 60 35 1.4 28 200 1570 2.6 53 370 2960 VCC = Falling at 1 mV/s ADM6315xxD1 ADM6315xxD2 ADM6315xxD3 ADM6315xxD4 VTH > 4.0 V (VIL) VTH > 4.0 V (VIH) VTH ...
Description	Open-Drain Microprocessor Supervisory Circuit in 4-Lead SOT-143
File Size	96.40K / 8 Page	View it Online	Download Datasheet

				ANALOG DEVICES INC Analog Devices, Inc. AD[Analog Devices]
Part No.	ADM811 ADM811-3TART-REEL ADM811-3TART-RL7 ADM811LART-REEL ADM811LART-REEL-7 ADM811MART-REEL ADM811MART-REEL-7 ADM811RART-REEL ADM811RART-REEL-7 ADM811SART-REEL ADM811SART-REEL-7 ADM811TART-REEL ADM811TART-REEL-7 ADM812 ADM812TART-REEL-7 ADM812LART-REEL ADM812LART-REEL-7 ADM812MART-REEL ADM812MART-REEL-7 ADM812RART-REEL ADM812RART-REEL-7 ADM812SART-REEL ADM812SART-REEL-7 ADM812TART-REEL ANALOGDEVICESINC-ADM812RART-REEL-7
OCR Text	... COEFFICIENT VCC TO RESET/RESET DELAY RESET ACTIVE TIMEOUT PERIOD MANUAL RESET Minimum Pulsewidth Glitch Immunity RESET/RESET Propagation Delay Pull-Up Resistance The Manual Reset Circuit Will Act On An Input Rising Above An Input Falling B...
Description	Microprocessors Supervisory Circuit in 4-Lead SOT-143 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO4 Linear 1-cell Li-Ion Battery Charger w/Integrated FET, One LED 20-HTSSOP 0 to 70 PRECISION THERM Micorprocessor Supervisory Circuit in 4-Pin SOT143 Microprocessors Supervisory Circuit in 4-Lead SOT-143, Logic High RESET Output
File Size	83.45K / 6 Page	View it Online	Download Datasheet

				AD[Analog Devices]
Part No.	ADV7129 ADV7129KS
OCR Text	...High Time, t3 LOADIN to LOADOUT Delay, t4 Pixel Setup Time, t5 Pixel Hold Time, t6 4 (VAA2 = +5 V, VREF = +1.235 V, RRSET, RGSET, RBSET = 280 , RL = 25 3 MIN to TMAX unless otherwise noted.) Conditions Min 10 16.67 6.67 6.67 1 4 10 10 ...
Description	192-Bit, 360 MHz True-Color Video DAC with Onboard PLL
File Size	381.53K / 20 Page	View it Online	Download Datasheet

For delay-locked Found Datasheets File :: 4344 Search Time::1.11ms
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