...ote in 3-bit input mode, unused i/O pins must be held at the L level. To use for module, the back side of iC chip must be held at the VSS (GND) level.
4
Data Sheet S13685EJ1V0DS00
PD16340
TRUTH TABLE
Shift Register Block
input ...
...EE V1 STB FRMB DOFFB' L1 L2 DiR i i i i i i input/Output Pad No. Function 5 V power for level shifter GND power for level shifter Power for ...o X240 when H (DiR = VDD), X240 o X1 Liquid-crystal drive output Selects and outputs one of VDD, VEE...
...FRM /DOFF' L1 L2 DiR X1 to X160 i i i i i i O input/Output Pad No. Function 5 V power for level shifter GND for level shifter Power for logic, liquid-crystal drive level power Power for logic, liquid-crystal drive level power (GND) Liquid-c...
Description
160-OUTPUT LCD ROW DRiVER 160输出的液晶显示器列驱 STN-LCD common driver, 160-outputs, 40V
...erters to support digital voice i/O * Supports iSA bus subset * Power supply voltage: VDD2 = 2.5 V (internal), VDD3 = 3.3 V (external) (131 MHz model) * Package: 224-pin fine-pitch FBGA
APPLiCATiONS
* Battery-driven portable information...
... for up to 16 bytes of data.
i/O CONTROL LOGiC
MEMORY CONTROL LOGiC
XDEC
EEPROM ARRAY PAGE LATCHES
SDA
SCL YDEC
VCC VSS
SENSE AMP R/W CONTROL
i2C is a trademark of Philips Corporation.
(c) 1997 Microchip Techno...
...DRAM contents remain unchanged. i/D: Set Cursor Moving Direction i/D=1: increment i/D=0: Decrement S: Specify Shift of Display S=1: The disp...o changing DD RAM contents S/C=0: Cursor Shift (RAM unchanged) S/C=1: Display Shift (RAM unchanged) ...
Description
0.0-6.5V; 5x7dots with cursor; 16characters x 1lines; dot size:0.55x0.75mm; AZ display SPECiFiCATiONS FOR LiQUiD CRYSTAL DiSPLAY 2.7-5.5V; 16characters x 1lines; dot size:0.55x0.75mm; liquid crystal display
...tocol uses CLOCK (SCL) and DATA i/O (SDA) lines to synchronously clock data between the master (for example a microprocessor) and the slave EEPROM device(s). The contents of the non-volatile memory allows the CPU to determine the capacity o...
Description
2K-Bit Standard 2-Wire Bus interface Serial EEPROM with Full Array Write Protect
...tocol uses CLOCK (SCL) and DATA i/O (SDA) lines to synchronously clock data between the master (for example a microprocessor) and the slave EEPROM device(s). The contents of the non-volatile memory allows the CPU to determine the capacity o...
Description
2K-Bit Standard 2-Wire Bus interface Serial EEPROM with Full Array Write Protect
iNTEGRATED CiRCUiTS
DATA SHEET
PCF5077T Power amplifier controller for GSM and PCN systems
Preliminary specification File under integ...O) 14
VD1
BAND GAP VDDA1 ibias Vref 8 DAC8 DACA QRSA -0.8 100 mV DACA POWER LEVEL REGiSTER 8-b...
Description
Power amplifier controller for GSM and PCN systems
iNTEGRATED CiRCUiTS
DATA SHEET
PCF5083 GSM signal processing iC
Objective specification File under integrated Circuits, iC17 1996 Oct...O-port Real Time Clock Setting the real time clock DESCRiPTiON OF THE DSP CORE interface description...