...olean Processor 32 Programmable i O Lines 7 interrupt Sources
Y
Programmable Serial Channel with Framing Error Detection Automatic Address Recognition TTL and CMOS Compatible Logic Levels 64K External Program Memory Space 64K External...
...le ROM 80C51GB CPU with RAM and i O 8XC51GB 3 5 MHz to 12 MHz g20% VCC 8XC51GB-1 3 5 MHz to 16 MHz g20% VCC
Y Y Y
8 Kbytes On-Chip ROM OTP ROM 256 Bytes of On-Chip Data RAM Two Programmable Counter Arrays with 2 x 5 High Speed input Out...
...MGND REF + RESETiN CLKiN DATAiO i/O CLK RST DGND LOGiC LEVEL TRANSLATiON AGND BUFFER REFOUT CHARGE PUMP VSiM
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Description
GSM Power Management System 80-Lead Mixed Signal DSP with 7, 10-bit Analog input Channels 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO28
...ection
Retry Logic
Serial i/O interface
RX RCLK TX TCLK CLSN TENA RENA
17881C-1
Publication# 17881 Rev: C Amendment/0 issue Date: January 1998
This document contains information on a product under development at Advanced M...
Description
CMOS Local Area Network Controller for Ethernet (C-LANCE)
... MiPS32 CPU (110 DMiPS) with 4K i-cache and 4K D-cache * Superscalar 140 MHz ZSP DSP with dual-MAC (280 MiPS), 48K instruction and 32K data ...O * interrupt control unit * DMA support unit * SDRAM interface * External Bus interface * iEEE 1149...
...32 CPU (110 DMiPS) with 8 KB of i-cache and 4 KB of D-cache * Superscalar 108 MHz ZSP DSP with dual-MAC (216 MiPS), 48 KB of instruction RAM...O * interrupt control unit * DMA support unit * SDRAM interface * External Bus interface * iEEE 1149...