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  ddr-i -ii Datasheet PDF File

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    BCM7320

Electronic Theatre Controls, Inc.
ETC
Part No. BCM7320
OCR Text ... ISO7816 (2) EBI EJTAG DDR-SDRAM Controller Peripheral Smart Card ROM (FLASH) Test ICE DDR-DRAM IR/LED/KEY/uART S...I/F from an external hard disk drive, (or combination), and display the resulting decoded audio and ...
Description SINGLE CHIP SATELLITESET TOP BOX DECODER

File Size 92.86K  /  2 Page

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    NE57811 NE57811S

NXP Semiconductors N.V.
PHILIPS[Philips Semiconductors]
Part No. NE57811 NE57811S
OCR Text DDR memory termination power with shutdown Product data Supersedes data of 2002 Jul 16 2003 Apr 02 Philips Semiconductors Philips Sem...I (VDD = 2.5 V) or ddr-iI (VDD = 1.8 V) SDRAM systems SIMPLIFIED SYSTEM DIAGRAM DIMM0 DIMM1 ...
Description Advanced DDR memory termination power with shutdown 先进的DDR存储器终端电源与关机

File Size 131.81K  /  13 Page

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    EM658160 EM658160TS-33 EM658160TS-35 EM658160TS-4 EM658160TS-5 EM658160TS-6 EM658160TS-7 EM658160TS-8

ETRON[Etron Technology, Inc.]
ETRON[Etron Technology Inc.]
Part No. EM658160 EM658160TS-33 EM658160TS-35 EM658160TS-4 EM658160TS-5 EM658160TS-6 EM658160TS-7 EM658160TS-8
OCR Text DDR Synchronous DRAM (SDRAM) Features Fast clock rate: 300/285/250/200/166/143/125MHz Differential Clock CK & /CK Bi-directional DQS DLL e...I/O Interface * Package: 66 Pin TSOP II, 0.65mm pin pitch * * * * * * * * Pin Assignment (Top Vie...
Description 4M x 16 DDR Synchronous DRAM (SDRAM)

File Size 154.94K  /  26 Page

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    FAN5236QSC FAN5236QSCX FAN5236MTC FAN5236MTCX FAN5236

FAIRCHILD[Fairchild Semiconductor]
Part No. FAN5236QSC FAN5236QSCX FAN5236MTC FAN5236MTCX FAN5236
OCR Text DDR / Dual-output PWM Controller Features * Highly flexible dual synchronous switching PWM controller includes modes for: - DDR mode wit...I/O, chip-sets, and memory banks in high-performance notebook computers, PDAs and Internet appliance...
Description Dual Mobile-Friendly DDR / Dual-output PWM Controller

File Size 196.28K  /  20 Page

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    HD74CDCV857

HITACHI[Hitachi Semiconductor]
Part No. HD74CDCV857
OCR Text ...cifically designed for use with DDR (Double Data Rate) synchronous DRAMs. Features * Supports 60 MHz to 200 MHz operation range * Distributes one differential clock input pair to ten differential clock outputs pairs * Supports spread sp...
Description 2.5-V Phase-lock Loop Clock Driver

File Size 60.37K  /  15 Page

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    ICS9248-128 ICS9248YF-128 AV9248F-128

ICST[Integrated Circuit Systems]
Integrated Device Technology, Inc.
Part No. ICS9248-128 ICS9248YF-128 AV9248F-128
OCR Text ...32, 34,35,37,38 P in name V DDR/X RE F0 M ode GND X1 X2 V DDP CI FS 1 P CICLK _F P CICLK 0 FS 2 P CICLK (4:1) S DRA M 12, S DRA M (7:0) ...I 2 C serial input. Clock input of I 2 C input This input pin controls the frequency of the S IO. If...
Description Frequency generator and integrated buffer
Single Chip, SIS 530/620 System Clock with AMD 533MHz Freq. and Overclocking
Frequency Generator & Integrated Buffers
133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 0.300 INCH, SSOP-48
Frequency Generator & Integrated Buffers

File Size 184.16K  /  16 Page

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    ICSSSTV16857 ICSSSTV16857YL-T ICS16857 ICSSSTV16857YG-T ICSSSTV16857YGLF-T

Integrated Circuit Syst...
ICST[Integrated Circuit Systems]
NXP Semiconductors N.V.
DOMINANT Opto Technologies Sdn. Bhd.
Part No. ICSSSTV16857 ICSSSTV16857YL-T ICS16857 ICSSSTV16857YG-T ICSSSTV16857YGLF-T
OCR Text DDR 14-Bit Registered Buffer Recommended Application: DDR Memory Modules Product Features: * Differential clock signal * Meets SSTL_2 signal data * Supports SSTL_2 class I & II specifications * low-voltage operation VDD = 2.3V to 2.7V * 48...
Description SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 0.240 INCH, 0.50 MM PITCH, TSSOP-48
DDR 14-Bit Registered Buffer 复员14位注册缓冲区

File Size 112.85K  /  8 Page

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    ICSSSTV16859 ICSSSTV16859YK

ICST[Integrated Circuit Systems]
Part No. ICSSSTV16859 ICSSSTV16859YK
OCR Text DDR 13-Bit to 26-Bit Registered Buffer Recommended Application: DDR Memory Modules Product Features: * Differential clock signals * Meets S...I/O Levels except for the RESET# input which is LVCMOS. Data flow from D to Q is controlled by the d...
Description DDR 13-Bit to 26-Bit Registered Buffer

File Size 231.88K  /  8 Page

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    IDT74SSTV16857 IDT74SSTV16857PA IDT74SSTV16857PAG IDT74SSTV16857PAG8 IDT74SSTV16857PA8

IDT[Integrated Device Technology]
Integrated Device Technology, Inc.
Part No. IDT74SSTV16857 IDT74SSTV16857PA IDT74SSTV16857PAG IDT74SSTV16857PAG8 IDT74SSTV16857PA8
OCR Text ...S: * Ideally suited for DIMM DDR registered applications FUNCTIONAL BLOCK DIAGRAM RESET 34 CK CK 38 39 VREF 35 D1 4...I/O INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION Q1 Q2 GND VDDQ Q3 Q4 Q5 GND VDDQ Q6 Q7 VDD...
Description 14-BIT REGISTERED BUFFER WITH SSTL I/O

File Size 52.38K  /  6 Page

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    SSTV16857 SSTV16857MTD

Fairchild Semiconductor
Part No. SSTV16857 SSTV16857MTD
OCR Text ...ed for use with 184 and 232 pin ddr-i memory modules. The device has a differential input clock, SSTL-2 compatible data inputs and a LVCMOS compatible RESET input. The device has been designed for compliance with the JEDEC DDR module and re...
Description From old datasheet system
14-Bit Register with SSTL-2 Compatible I/O and Reset

File Size 75.80K  /  6 Page

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