lvecl/HSTL Clock and Data Driver
General Description Features
o Guaranteed 400mV Differential Output at 1.5GHz o Selectable Single-Ended o...lvpecl signals, this device operates over a +3.0V to +3.8V supply range, allowing high-performance c...
Description
1:5 Differential lvpecl/lvecl/HSTL Clock and Data Driver LINE DRIVER, PDSO20
...clock distribution in mind. The lvecl/lvpecl input signal pairs can be differential or used single-ended (with VBB output reference bypassed and connected to the unused input of a pair). Either of two fully differential clock inputs may be ...
Description
0.345A, 2.7-5.5V Quad (2In/ 4Out) Hi-Side MOSFET, Fault Report, Act-Low Enable 16-SOIC 0 to 85 Low Voltage 1:15 Differential ±1±2 ECL/PECL Clock Driver From old datasheet system MARKING DIAGRAM Low Voltage 1:15 Differential 12 ECL/PECL Clock Driver Low Voltage 1:15 Differential ÷1÷2 ECL/PECL Clock Driver
... a differential or single-ended lvecl or, if positive power supplies are used, lvpecl input signal. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device (see Interfacing section of the ECLinPSTM Data B...
Description
, /6 Clock Generation Chip 2, 4/6 Clock Generation Chip From old datasheet system ±2, ±4/6 Clock Generation Chip
... a differential or single-ended lvecl or, if positive power supplies are used, lvpecl input signal. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device (see Interfacing section of the ECLinPSTM Data B...
Description
±2/4,±4/6 Clock Generation Chip From old datasheet system 2/4 /4/6 Clock Generation Chip 2/44/6 Clock Generation Chip 2/4,4/6 Clock Generation Chip
lvecl/lvpecl/LVEPECL/HSTL Clock Driver
The MC100LVEP111 is a low skew 1-to-10 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The lvecl/lvpecl input signals can be eithe...
Description
From old datasheet system Low-Voltage 1:10 Differential lvecl/lvpecl/LVEPECL/HSTL Clock Driver
lvecl/lvpecl/LVEPECL/HSTL Clock Driver
The MC100LVEP14 is a low skew 1-to-5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The lvecl/lvpecl input signals can be either ...
lvecl/lvpecl/LVEPECL/HSTL Clock Driver
The MC100LVEP210 is a low skew 1-to-5 dual differential driver, designed with clock distribution in mind. The lvecl/lvpecl input signals can be either differential or single-ended if the VBB output is...
Description
Low-Voltage 1:5 Dual Diff.lvecl/lvpecl/LVEPECL/HSTL Clock Driver 100LVE SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 From old datasheet system
...cur.
DC CHARACTERISTICS, ECL/lvecl (VCC = 0V, VEE = -5.5V to -3.0V) (Note 3.)
-40C Symbol IEE VOH VOL VIH VIL IIH Characteristic Power S...lvpecl (VCC = 3.3V 0.3V, VEE = 0V) (Note 6.)
-40C Symbol IEE VOH VOL VIH VIL IIH Characteristic Po...